| /dalvik/dexgen/src/com/android/dexgen/rop/code/ |
| RegisterSpecSet.java | 33 * {@code null} or is an instance whose {@code reg}
163 * @param reg {@code >= 0;} the desired register number
167 public RegisterSpec get(int reg) {
169 return specs[reg];
172 throw new IllegalArgumentException("bogus reg");
201 for (int reg = 0; reg < length; reg++) {
202 RegisterSpec s = specs[reg];
226 for (int reg = 0; reg < length; reg++)
273 int reg = spec.getReg(); local
[all...] |
| /dalvik/dx/src/com/android/dx/rop/code/ |
| RegisterSpecSet.java | 32 * {@code null} or is an instance whose {@code reg}
162 * @param reg {@code >= 0;} the desired register number
166 public RegisterSpec get(int reg) {
168 return specs[reg];
171 throw new IllegalArgumentException("bogus reg");
200 for (int reg = 0; reg < length; reg++) {
201 RegisterSpec s = specs[reg];
225 for (int reg = 0; reg < length; reg++)
272 int reg = spec.getReg(); local
[all...] |
| /external/dexmaker/src/dx/java/com/android/dx/rop/code/ |
| RegisterSpecSet.java | 32 * {@code null} or is an instance whose {@code reg}
162 * @param reg {@code >= 0;} the desired register number
166 public RegisterSpec get(int reg) {
168 return specs[reg];
171 throw new IllegalArgumentException("bogus reg");
200 for (int reg = 0; reg < length; reg++) {
201 RegisterSpec s = specs[reg];
225 for (int reg = 0; reg < length; reg++)
272 int reg = spec.getReg(); local
[all...] |
| /art/compiler/dex/quick/arm64/ |
| int_arm64.cc | 56 OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg);
57 NewLIR4(kA64Csinc4rrrc, rl_result.reg.GetReg(), rwzr, rwzr, kArmCondEq);
58 NewLIR4(kA64Csneg4rrrc, rl_result.reg.GetReg(), rl_result.reg.GetReg(),
59 rl_result.reg.GetReg(), kArmCondGe);
85 OpRegRegReg(op, rl_result.reg, rl_src1.reg, As64BitReg(rl_shift.reg));
187 OpRegImm(kOpCmp, rl_src.reg, 0)
1402 int reg = *reg1 + first_bit_set; local
[all...] |
| /frameworks/native/include/private/ui/ |
| RegionHelper.h | 198 void advance(region& reg, TYPE& aTop, TYPE& aBottom) {
200 size_t count = reg.count;
201 RECT const * rects = reg.rects;
209 aTop = rects->top + reg.dy;
210 aBottom = rects->bottom + reg.dy;
215 reg.rects = rects;
216 reg.count = count;
279 void advance(region& reg, TYPE& left, TYPE& right) {
280 if (reg.rects && reg.count)
[all...] |
| /art/compiler/dex/quick/ |
| gen_common.cc | 61 void Mir2Lir::GenDivZeroCheck(RegStorage reg) {
62 LIR* branch = OpCmpImmBranch(kCondEq, reg, 0, nullptr);
138 LIR* Mir2Lir::GenNullCheck(RegStorage reg) {
153 LIR* branch = OpCmpImmBranch(kCondEq, reg, 0, nullptr);
199 void Mir2Lir::ForceImplicitNullCheck(RegStorage reg, int opt_flags) {
208 LIR* load = Load32Disp(reg, 0, tmp);
261 OpCmpImmBranch(cond, rl_src1.reg, mir_graph_->ConstantValue(rl_src2), taken);
271 OpCmpImmBranch(cond, rl_src1.reg, 0, taken);
277 OpCmpBranch(cond, rl_src1.reg, rl_src2.reg, taken)
[all...] |
| /external/lldb/tools/debugserver/source/MacOSX/ppc/ |
| DNBArchImpl.cpp | 17 #define PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(reg) __##reg
19 #define PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(reg) reg
421 DNBArchMachPPC::GetRegisterValue(int set, int reg, DNBRegisterValue *value) const
425 switch (reg)
429 reg = e_regNumGPR_srr0;
434 reg = e_regNumGPR_r1;
446 reg = e_regNumGPR_lr;
451 reg = e_regNumGPR_srr1
[all...] |
| /art/compiler/utils/mips/ |
| managed_register_mips.h | 44 std::ostream& operator<<(std::ostream& os, const RegisterPair& reg);
210 MipsManagedRegister reg(reg_id);
211 CHECK(reg.IsValidManagedRegister());
212 return reg;
216 std::ostream& operator<<(std::ostream& os, const MipsManagedRegister& reg);
221 mips::MipsManagedRegister reg(id_);
222 CHECK(reg.IsNoRegister() || reg.IsValidManagedRegister());
223 return reg;
|
| /art/compiler/utils/x86/ |
| managed_register_x86.h | 45 std::ostream& operator<<(std::ostream& os, const RegisterPair& reg);
207 X86ManagedRegister reg(reg_id);
208 CHECK(reg.IsValidManagedRegister());
209 return reg;
213 std::ostream& operator<<(std::ostream& os, const X86ManagedRegister& reg);
218 x86::X86ManagedRegister reg(id_);
219 CHECK(reg.IsNoRegister() || reg.IsValidManagedRegister());
220 return reg;
|
| /dalvik/dx/src/com/android/dx/ssa/back/ |
| RegisterAllocator.java | 76 * @param reg register
79 protected final int getCategoryForSsaReg(int reg) {
80 SsaInsn definition = ssaMeth.getDefinitionForRegister(reg);
83 // an undefined reg
93 * @param reg {@code >= 0;} SSA register
97 protected final RegisterSpec getDefinitionSpecForSsaReg(int reg) {
98 SsaInsn definition = ssaMeth.getDefinitionForRegister(reg);
107 * @param reg register in question
110 protected boolean isDefinitionMoveParam(int reg) {
111 SsaInsn defInsn = ssaMeth.getDefinitionForRegister(reg);
[all...] |
| /development/perftests/panorama/feature_mos/src/mosaic/ |
| AlignFeatures.cpp | 52 return reg.profile_string;
80 if (!reg.Initialized())
82 reg.Init(width, height, motion_model_type, 20, linear_polish, quarter_res,
92 if (reg.Initialized())
113 reg.AddFrame(m_rows, Hcurr, true); // Force this to be a reference frame
114 int num_corner_ref = reg.GetNrRefCorners();
123 reg.AddFrame(m_rows, Hcurr, false);
136 int num_inliers = reg.GetNrInliers();
181 reg.UpdateReference(m_rows,quarter_res,false);
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
| r300_fragprog_swizzle.c | 107 static int r300_swizzle_is_native(rc_opcode opcode, struct rc_src_register reg)
117 if (reg.Abs || reg.Negate)
121 unsigned int swz = GET_SWZ(reg.Swizzle, j);
134 if (GET_SWZ(reg.Swizzle, j) != RC_SWIZZLE_UNUSED)
137 if ((reg.Negate & relevant) && ((reg.Negate & relevant) != relevant))
140 sd = lookup_native_swizzle(reg.Swizzle);
141 if (!sd || (reg.File == RC_FILE_PRESUB && sd->srcp_stride == 0))
|
| /external/dexmaker/src/dx/java/com/android/dx/ssa/back/ |
| RegisterAllocator.java | 78 * @param reg register
81 protected final int getCategoryForSsaReg(int reg) {
82 SsaInsn definition = ssaMeth.getDefinitionForRegister(reg);
85 // an undefined reg
95 * @param reg {@code >= 0;} SSA register
99 protected final RegisterSpec getDefinitionSpecForSsaReg(int reg) {
100 SsaInsn definition = ssaMeth.getDefinitionForRegister(reg);
109 * @param reg register in question
112 protected boolean isDefinitionMoveParam(int reg) {
113 SsaInsn defInsn = ssaMeth.getDefinitionForRegister(reg);
[all...] |
| /external/llvm/lib/CodeGen/ |
| LiveRegMatrix.cpp | 76 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI)
78 assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment");
79 VRM->assignVirt2Phys(VirtReg.reg, PhysReg);
90 unsigned PhysReg = VRM->getPhys(VirtReg.reg);
91 DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI)
93 VRM->clearVirt(VirtReg.reg);
107 if (RegMaskVirtReg != VirtReg.reg || RegMaskTag != UserTag) {
108 RegMaskVirtReg = VirtReg.reg;
124 CoalescerPair CP(VirtReg.reg, PhysReg, *TRI);
|
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| r300_fragprog_swizzle.c | 107 static int r300_swizzle_is_native(rc_opcode opcode, struct rc_src_register reg)
117 if (reg.Abs || reg.Negate)
121 unsigned int swz = GET_SWZ(reg.Swizzle, j);
134 if (GET_SWZ(reg.Swizzle, j) != RC_SWIZZLE_UNUSED)
137 if ((reg.Negate & relevant) && ((reg.Negate & relevant) != relevant))
140 sd = lookup_native_swizzle(reg.Swizzle);
141 if (!sd || (reg.File == RC_FILE_PRESUB && sd->srcp_stride == 0))
|
| /packages/apps/Camera/jni/feature_mos/src/mosaic/ |
| AlignFeatures.cpp | 52 return reg.profile_string;
80 if (!reg.Initialized())
82 reg.Init(width, height, motion_model_type, 20, linear_polish, quarter_res,
92 if (reg.Initialized())
113 reg.AddFrame(m_rows, Hcurr, true); // Force this to be a reference frame
114 int num_corner_ref = reg.GetNrRefCorners();
123 reg.AddFrame(m_rows, Hcurr, false);
136 int num_inliers = reg.GetNrInliers();
181 reg.UpdateReference(m_rows,quarter_res,false);
|
| /packages/apps/LegacyCamera/jni/feature_mos/src/mosaic/ |
| AlignFeatures.cpp | 52 return reg.profile_string;
80 if (!reg.Initialized())
82 reg.Init(width, height, motion_model_type, 20, linear_polish, quarter_res,
92 if (reg.Initialized())
113 reg.AddFrame(m_rows, Hcurr, true); // Force this to be a reference frame
114 int num_corner_ref = reg.GetNrRefCorners();
123 reg.AddFrame(m_rows, Hcurr, false);
136 int num_inliers = reg.GetNrInliers();
181 reg.UpdateReference(m_rows,quarter_res,false);
|
| /system/core/debuggerd/mips/ |
| machine.cpp | 54 for (int reg = 0; reg < 32; reg++) {
56 if (reg == 0 // $0
57 || reg == 26 // $k0
58 || reg == 27 // $k1
59 || reg == 31 // $ra (done below)
63 uintptr_t addr = R(r.regs[reg]);
71 _LOG(log, logtype::MEMORY, "\nmemory near %.2s:\n", ®_NAMES[reg * 2]);
|
| /art/compiler/dex/quick/mips/ |
| fp_mips.cc | 66 NewLIR3(op, rl_result.reg.GetReg(), rl_src1.reg.GetReg(), rl_src2.reg.GetReg());
112 NewLIR3(op, rl_result.reg.GetReg(), rl_src1.reg.GetReg(), rl_src2.reg.GetReg());
160 NewLIR2(op, rl_result.reg.GetReg(), rl_src.reg.GetReg());
219 OpRegRegImm(kOpAdd, rl_result.reg, rl_src.reg, 0x80000000)
[all...] |
| /external/ltrace/sysdeps/linux-gnu/metag/ |
| trace.c | 118 get_regval_from_unit(enum metag_unitnum unit, unsigned int reg,
122 * Check if reg has a sane value.
127 if (reg >= ((sizeof(regs->ax)/N_UNITS/REG_SIZE)))
130 if (reg >= ((sizeof(regs->dx)/N_UNITS/REG_SIZE)))
136 return regs->ax[reg][1];
138 return regs->dx[reg][0];
140 return regs->dx[reg][1];
142 return regs->ax[reg][0];
153 reg, unit);
163 unsigned int unit = 0, reg; local
[all...] |
| /art/compiler/optimizing/ |
| parallel_move_test.cc | 35 << move->GetSource().reg().RegId()
37 << move->GetDestination().reg().RegId()
47 << move->GetSource().reg().RegId()
49 << move->GetDestination().reg().RegId()
53 virtual void SpillScratch(int reg) {}
54 virtual void RestoreScratch(int reg) {}
|
| /dalvik/dx/src/com/android/dx/ssa/ |
| SsaInsn.java | 112 * Returns whether or not the specified reg is the result reg.
114 * @param reg register to test
118 public boolean isResultReg(int reg) {
119 return result != null && result.getReg() == reg;
127 * @param reg new result register
129 public void changeResultReg(int reg) {
131 result = result.withReg(reg);
212 * @param reg the register in question
213 * @return true if the reg is a sourc
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600RegisterInfo.cpp | 69 unsigned R600RegisterInfo::getHWRegIndex(unsigned reg) const
71 switch(reg) {
84 default: return getHWRegIndexGen(reg);
88 unsigned R600RegisterInfo::getHWRegChan(unsigned reg) const
90 switch(reg) {
103 default: return getHWRegChanGen(reg);
|
| /external/lldb/source/Plugins/Process/POSIX/ |
| RegisterContext_i386.h | 38 GetRegisterInfoAtIndex(size_t reg);
50 GetRegisterName(unsigned reg);
53 ReadRegisterValue(uint32_t reg, lldb_private::Scalar &value);
56 ReadRegisterBytes(uint32_t reg, lldb_private::DataExtractor &data);
66 WriteRegisterValue(uint32_t reg, const lldb_private::Scalar &value);
69 WriteRegisterBytes(uint32_t reg, lldb_private::DataExtractor &data,
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600RegisterInfo.cpp | 69 unsigned R600RegisterInfo::getHWRegIndex(unsigned reg) const
71 switch(reg) {
84 default: return getHWRegIndexGen(reg);
88 unsigned R600RegisterInfo::getHWRegChan(unsigned reg) const
90 switch(reg) {
103 default: return getHWRegChanGen(reg);
|
