| /external/llvm/lib/Target/XCore/ |
| XCoreFrameLowering.cpp | 51 unsigned Reg;
52 StackSlotInfo(int f, int o, int r) : FI(f), Offset(o), Reg(r){};
201 BuildMI(MBB, MBBI, dl, TII.get(Opcode), SpillList[i].Reg)
286 MBB.addLiveIn(SpillList[i].Reg);
288 .addReg(SpillList[i].Reg, RegState::Kill)
293 unsigned DRegNum = MRI->getDwarfRegNum(SpillList[i].Reg, true);
329 MRI->getDwarfRegNum(SpillList[0].Reg, true),
332 MRI->getDwarfRegNum(SpillList[1].Reg, true),
426 unsigned Reg = it->getReg();
427 assert(Reg != XCore::LR && !(Reg == XCore::R10 && hasFP(*MF)) &
[all...] |
| XCoreInstrInfo.h | 47 /// the source reg along with the FrameIndex of the loaded stack slot. If
85 // Emit code before MBBI to load immediate value into physical register Reg.
89 unsigned Reg, uint64_t Value) const;
|
| /external/llvm/include/llvm/CodeGen/ |
| ScheduleDAGInstrs.h | 38 VReg2SUnit(unsigned reg, SUnit *su): VirtReg(reg), SU(su) {}
50 unsigned Reg;
52 PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {}
54 unsigned getSparseSetIndex() const { return Reg; }
|
| MachineInstrBundle.h | 170 /// Clobbers - Reg or an overlapping register is defined, or a regmask
171 /// clobbers Reg.
174 /// Defines - Reg or a super-register is defined.
180 /// ReadsOverlap - Reg or an overlapping register is read.
183 /// DefinesDead - All defs of a Reg or a super-register are dead.
186 /// There is a kill of Reg or a super-register.
194 /// @param Reg The virtual register to analyze.
196 /// each operand referring to Reg.
198 VirtRegInfo analyzeVirtReg(unsigned Reg,
205 /// @param Reg The physical register to analyze
[all...] |
| /external/llvm/lib/CodeGen/ |
| CalcSpillWeights.cpp | 36 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
37 if (MRI.reg_nodbg_empty(Reg))
39 VRAI.calculateSpillWeightAndHint(LIS.getInterval(Reg));
43 // Return the preferred allocation register for reg, given a COPY instruction.
44 static unsigned copyHint(const MachineInstr *mi, unsigned reg,
48 if (mi->getOperand(0).getReg() == reg) {
64 const TargetRegisterClass *rc = mri.getRegClass(reg);
70 // reg:sub should match the physreg hreg.
110 bool noHint = mri.getRegAllocationHint(li.reg).first != 0;
116 I = mri.reg_instr_begin(li.reg), E = mri.reg_instr_end()
[all...] |
| PHIElimination.cpp | 86 bool isLiveIn(unsigned Reg, MachineBasicBlock *MBB);
87 bool isLiveOutPastPHIs(unsigned Reg, MachineBasicBlock *MBB);
232 assert(MPhi->getOperand(0).getSubReg() == 0 && "Can't handle sub-reg PHIs");
558 unsigned Reg = BBI->getOperand(i).getReg();
578 if (!isLiveOutPastPHIs(Reg, PreMBB) && !SplitAllCriticalEdges)
581 DEBUG(dbgs() << PrintReg(Reg) << " live-out before critical edge BB#"
585 // If Reg is not live-in to MBB, it means it must be live-in to some
589 // If Reg *is* live-in to MBB, the interference is inevitable and a copy
593 bool ShouldSplit = !isLiveIn(Reg, &MBB) || SplitAllCriticalEdges;
621 bool PHIElimination::isLiveIn(unsigned Reg, MachineBasicBlock *MBB)
[all...] |
| BranchFolding.cpp | 145 unsigned Reg = I->getOperand(0).getReg();
146 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
163 unsigned Reg = MO.getReg();
164 if (ImpDefRegs.count(Reg))
[all...] |
| LiveRangeCalc.cpp | 40 void LiveRangeCalc::createDeadDefs(LiveRange &LR, unsigned Reg) {
43 // Visit all def operands. If the same instruction has multiple defs of Reg,
45 for (MachineOperand &MO : MRI->def_operands(Reg)) {
63 void LiveRangeCalc::extendToUses(LiveRange &LR, unsigned Reg) {
66 // Visit all operands that read Reg. This may include partial defs.
67 for (MachineOperand &MO : MRI->reg_nodbg_operands(Reg)) {
74 // MI is reading Reg. We may have visited MI before if it happens to be
75 // reading Reg multiple times. That is OK, extend() is idempotent.
83 // PHI operands are paired: (Reg, PredMBB).
101 extend(LR, Idx, Reg);
[all...] |
| TailDuplication.cpp | 343 static bool isDefLiveOut(unsigned Reg, MachineBasicBlock *BB,
345 for (MachineInstr &UseMI : MRI->use_instructions(Reg)) {
437 unsigned Reg = MO.getReg();
438 if (!TargetRegisterInfo::isVirtualRegister(Reg))
441 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
444 LocalVRMap.insert(std::make_pair(Reg, NewReg));
445 if (isDefLiveOut(Reg, TailBB, MRI) || UsedByPhi.count(Reg))
446 AddSSAUpdateEntry(Reg, NewReg, PredBB);
448 DenseMap<unsigned, unsigned>::iterator VI = LocalVRMap.find(Reg);
[all...] |
| /external/llvm/lib/MC/MCParser/ |
| COFFAsmParser.cpp | 581 unsigned Reg;
582 if (ParseSEHRegisterNumber(Reg))
589 getStreamer().EmitWinCFIPushReg(Reg);
594 unsigned Reg;
596 if (ParseSEHRegisterNumber(Reg))
613 getStreamer().EmitWinCFISetFrame(Reg, Off);
635 unsigned Reg;
637 if (ParseSEHRegisterNumber(Reg))
655 getStreamer().EmitWinCFISaveReg(Reg, Off);
662 unsigned Reg;
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMMachineFunctionInfo.h | 210 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; }
|
| Thumb2SizeReduction.cpp | 262 unsigned Reg = MO.getReg();
263 if (Reg == 0 || Reg == ARM::CPSR)
265 Defs.insert(Reg);
271 unsigned Reg = MO.getReg();
272 if (Defs.count(Reg))
344 unsigned Reg = MO.getReg();
345 if (Reg == 0 || Reg == ARM::CPSR)
347 if (isPCOk && Reg == ARM::PC
[all...] |
| ARMBaseRegisterInfo.cpp | 208 static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI) {
209 for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers)
255 unsigned Reg = Order[I];
256 if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd)
259 unsigned Paired = getPairedGPR(Reg, !Odd, this);
262 Hints.push_back(Reg);
267 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
270 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
274 // If 'Reg' is one of the even / odd register pair and it's now change
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | 86 unsigned &Reg, unsigned &Imm,
154 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
160 /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
165 /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
171 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2'
184 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
242 /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
258 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand
[all...] |
| ARMTargetStreamer.cpp | 51 void ARMTargetStreamer::emitMovSP(unsigned Reg, int64_t Offset) {}
|
| ARMUnwindOpAsm.h | 58 void EmitSetSP(uint16_t Reg);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonCopyToCombine.cpp | 204 static bool isEvenReg(unsigned Reg) {
205 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
206 Hexagon::IntRegsRegClass.contains(Reg));
207 return (Reg - Hexagon::R0) % 2 == 0;
260 // uses I2's use reg we need to modify that (first) instruction to now kill
261 // this reg.
269 // * modifies I2's use reg
270 // * modifies I2's def reg
271 // * reads I2's def reg
314 // * modifies I1's use reg
[all...] |
| /external/llvm/lib/Target/Sparc/Disassembler/ |
| SparcDisassembler.cpp | 122 unsigned Reg = IntRegDecoderTable[RegNo];
123 Inst.addOperand(MCOperand::CreateReg(Reg));
133 unsigned Reg = IntRegDecoderTable[RegNo];
134 Inst.addOperand(MCOperand::CreateReg(Reg));
145 unsigned Reg = FPRegDecoderTable[RegNo];
146 Inst.addOperand(MCOperand::CreateReg(Reg));
157 unsigned Reg = DFPRegDecoderTable[RegNo];
158 Inst.addOperand(MCOperand::CreateReg(Reg));
170 unsigned Reg = QFPRegDecoderTable[RegNo];
171 if (Reg == ~0U
[all...] |
| /external/clang/lib/StaticAnalyzer/Core/ |
| ProgramState.cpp | 699 if (const MemRegion *Reg = V.getAsRegion())
700 return isTainted(Reg, Kind);
704 bool ProgramState::isTainted(const MemRegion *Reg, TaintTagType K) const {
705 if (!Reg)
710 if (const ElementRegion *ER = dyn_cast<ElementRegion>(Reg))
713 if (const SymbolicRegion *SR = dyn_cast<SymbolicRegion>(Reg))
716 if (const SubRegion *ER = dyn_cast<SubRegion>(Reg))
761 DynamicTypeInfo ProgramState::getDynamicTypeInfo(const MemRegion *Reg) const {
762 Reg = Reg->StripCasts()
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.cpp | 142 CodeGenRegister *Reg = RegBank.getReg(Aliases[i]);
143 ExplicitAliases.push_back(Reg);
144 Reg->ExplicitAliases.push_back(this);
495 // Make sure all sub-registers have been visited first, so the super-reg
586 Record *Reg = Lists[i][n];
588 Name += Reg->getName();
589 Tuple.push_back(DefInit::get(Reg));
591 unsigned(Reg->getValueAsInt("CostPerUse")));
691 const CodeGenRegister *Reg = RegBank.getReg((*Elements)[i]);
692 Members.insert(Reg);
[all...] |
| /external/llvm/lib/Target/Sparc/MCTargetDesc/ |
| SparcMCTargetDesc.cpp | 39 unsigned Reg = MRI.getDwarfRegNum(SP::O6, true);
40 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0);
48 unsigned Reg = MRI.getDwarfRegNum(SP::O6, true);
49 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 2047);
|
| /external/llvm/lib/Target/Mips/ |
| MipsDelaySlotFiller.cpp | 89 bool checkRegDefsUses(BitVector &NewDefs, BitVector &NewUses, unsigned Reg,
92 /// Returns true if Reg or its alias is in RegSet.
93 bool isRegInSet(const BitVector &RegSet, unsigned Reg) const;
366 unsigned Reg, bool IsDef) const {
368 NewDefs.set(Reg);
369 // check whether Reg has already been defined or used.
370 return (isRegInSet(Defs, Reg) || isRegInSet(Uses, Reg));
373 NewUses.set(Reg);
374 // check whether Reg has already been defined
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIInsertWaits.cpp | 142 unsigned Reg = Op.getReg();
143 unsigned Size = TRI->getMinimalPhysRegClass(Reg)->getSize();
192 unsigned Reg = Op.getReg();
193 unsigned Size = TRI->getMinimalPhysRegClass(Reg)->getSize();
198 Result.first = TRI->getEncodingValue(Reg);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 100 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
174 // Create the reg, emit the copy.
199 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
200 if (TargetRegisterInfo::isVirtualRegister(Reg))
201 return Reg;
216 // If the specific node value is only used by a CopyToReg and the dest reg
248 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
249 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
250 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
252 VRBase = Reg;
[all...] |
| /art/compiler/utils/ |
| assembler_test.h | 37 template<typename Ass, typename Reg, typename Imm>
55 std::string RepeatR(void (Ass::*f)(Reg), std::string fmt) {
56 const std::vector<Reg*> registers = GetRegisters();
58 for (auto reg : registers) {
59 (assembler_.get()->*f)(*reg);
62 size_t reg_index = base.find("{reg}");
65 sreg << *reg; local
80 std::string RepeatRR(void (Ass::*f)(Reg, Reg), std::string fmt) {
81 const std::vector<Reg*> registers = GetRegisters()
129 sreg << *reg; local
[all...] |
