| /external/chromium_org/chrome/browser/resources/chromeos/chromevox/common/ |
| braille_util.js | 353 if (goog.isDef(opt_selStart)) {
354 opt_selEnd = goog.isDef(opt_selEnd) ? opt_selEnd : opt_selStart;
388 if (goog.isDef(opt_displayPosition) &&
|
| spannable.js | 34 if (goog.isDef(opt_annotation)) {
200 var end = goog.isDef(opt_end) ? opt_end : this.string_.length;
|
| /external/llvm/lib/CodeGen/ |
| RegisterCoalescer.cpp | 818 assert(MO.isDef() && MO.isImplicit() && MO.isDead() &&
845 true /*IsDef*/,
[all...] |
| EarlyIfConversion.cpp | 239 if (MO->isDef() && TargetRegisterInfo::isPhysicalRegister(Reg))
295 if (MO->isDef())
|
| MachineCopyPropagation.cpp | 255 if (MO.isDef()) {
|
| ScheduleDAGInstrs.cpp | 223 if (!MO.isReg() || MO.isDef()) continue;
254 assert(MO.isDef() && "expect physreg def");
329 if (!MO.isDef()) {
824 if (MO.isDef()) {
[all...] |
| LiveIntervalAnalysis.cpp | 636 LiveIntervals::getSpillWeight(bool isDef, bool isUse,
641 return (isDef + isUse) * (Freq.getFrequency() * Scale);
[all...] |
| MachineRegisterInfo.cpp | 200 if (MO->isDef()) {
|
| MachineVerifier.cpp | 825 else if (!MO->isDef() && !MCOI.isOptionalDef())
835 if (MO->isDef() && !MCOI.isOptionalDef())
[all...] |
| TwoAddressInstructionPass.cpp | 203 if (!MO.isDef())
328 if (MO.isDef() && DI->second > LastDef)
806 if (MO.isDef())
849 if (MO.isDef()) {
[all...] |
| LiveVariables.cpp | 216 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
247 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
260 false/*IsDef*/,
270 LastDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
384 true/*IsDef*/, true/*IsImp*/));
400 LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/,
577 } else /*MO.isDef()*/ {
804 if (I->isDef())
|
| TargetInstrInfo.cpp | 450 if (MI->getOperand(Ops[i]).isDef())
629 if (MO.isDef() && Reg != DefReg)
|
| /external/chromium_org/third_party/skia/src/svg/ |
| SkSVGPaintState.cpp | 101 bool SkSVGPaint::flush(SkSVGParser& parser, bool isFlushable, bool isDef) {
119 if (isDef == true) {
|
| /external/llvm/lib/Target/ARM/ |
| ARMLoadStoreOptimizer.cpp | 496 bool isDef = (isi32Load(Opcode) || Opcode == ARM::VLDRS ||
542 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef)
650 if (!MO->isReg() || !MO->isDef() || !MO->isImplicit() || MO->isDead())
784 if (MO.isDef() && MO.getReg() == ARM::CPSR && !MO.isDead())
[all...] |
| /external/llvm/lib/Target/Mips/ |
| Mips16InstrInfo.cpp | 344 if (MO.isReg() && MO.getReg() != 0 && !MO.isDef() &&
361 if (MO.isReg() && MO.isDef()) {
|
| MipsDelaySlotFiller.cpp | 90 bool IsDef) const;
273 if (!MO.isReg() || !MO.isDef() || !(R = MO.getReg()))
356 HasHazard |= checkRegDefsUses(NewDefs, NewUses, MO.getReg(), MO.isDef());
366 unsigned Reg, bool IsDef) const {
367 if (IsDef) {
|
| /external/skia/src/svg/ |
| SkSVGPaintState.cpp | 101 bool SkSVGPaint::flush(SkSVGParser& parser, bool isFlushable, bool isDef) {
119 if (isDef == true) {
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonHardwareLoops.cpp | 860 if (!MO.isReg() || !MO.isDef())
897 if (!MO.isReg() || !MO.isDef())
917 if (!OPO.isReg() || !OPO.isDef())
[all...] |
| HexagonPeephole.cpp | 232 false /*isDef*/,
331 Dst.ChangeToRegister(Src.getReg(), Src.isDef(), Src.isImplicit(),
|
| HexagonInstrInfo.cpp | 838 && MI->getOperand(MI->getNumOperands()-1).isDef()
877 MI->getOperand(oper+1).ChangeToRegister(MO.getReg(), MO.isDef(),
920 MI->getOperand(oper+1).ChangeToRegister(PredMO.getReg(), PredMO.isDef(),
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FixupLEAs.cpp | 178 if (opnd.isDef())
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64CollectLOH.cpp | 306 (ADRPMode && (!IsADRP || !MO.isDef())))
346 if (!MO.isReg() || !MO.isDef())
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| GVN.cpp | 301 if (!local_dep.isDef() && !local_dep.isNonLocal()) {
306 if (local_dep.isDef()) {
343 if (!I->getResult().isDef() || cdep != nullptr) {
[all...] |
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| AsmPrinterInlineAsm.cpp | 436 for (; MI->getOperand(NumDefs).isReg() && MI->getOperand(NumDefs).isDef();
|
| /external/llvm/lib/Target/R600/ |
| R600MachineScheduler.cpp | 368 if (MO.isReg() && !MO.isDef() &&
|
