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  /external/llvm/test/CodeGen/ARM/
zero-cycle-zero.ll 1 ; RUN: llc -mtriple=armv8 -mcpu=cyclone < %s | FileCheck %s --check-prefix=CHECK-CYCLONE
7 ; CHECK-CYCLONE-LABEL: test_vec64:
12 ; CHECK-CYCLONE-NOT: vmov.f64 d0,
13 ; CHECK-CYCLONE: vmov.i32 d0, #0
14 ; CHECK-CYCLONE: bl
15 ; CHECK-CYCLONE: vmov.i32 d0, #0
16 ; CHECK-CYCLONE: bl
31 ; CHECK-CYCLONE-LABEL: test_vec128:
36 ; CHECK-CYCLONE-NOT: vmov.f64 [[ZEROREG:d[0-9]+]]
    [all...]
  /external/clang/test/Driver/
arm64-as.s 1 // Make sure the arm64 default on cyclone when compiling for apple.
5 // TARGET: "-target-cpu" "cyclone"
  /external/llvm/test/MC/AArch64/
arm64-target-specific-sysreg.s 4 // RUN: llvm-mc -triple arm64 -mcpu=cyclone -show-encoding < %s 2>&1 | \
5 // RUN: FileCheck %s --check-prefix=CHECK-CYCLONE
10 // CHECK-CYCLONE: msr CPM_IOACC_CTL_EL3, x0 // encoding: [0x00,0xf2,0x1f,0xd5]
  /external/llvm/test/CodeGen/AArch64/
arm64-zero-cycle-regmov.ll 1 ; RUN: llc -mtriple=arm64-apple-ios -mcpu=cyclone < %s | FileCheck %s
arm64-simd-scalar-to-vector.ll 1 ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -mcpu=cyclone | FileCheck %s
2 ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -O0 -mcpu=cyclone | FileCheck %s --check-prefix=CHECK-FAST
arm64-2012-05-07-MemcpyAlignBug.ll 1 ; RUN: llc < %s -march arm64 -mcpu=cyclone | FileCheck %s
arm64-alloca-frame-pointer-offset.ll 1 ; RUN: llc -march=arm64 -mcpu=cyclone < %s | FileCheck %s
arm64-dagcombiner-dead-indexed-load.ll 1 ; RUN: llc -mcpu=cyclone < %s | FileCheck %s
arm64-elf-globals.ll 1 ; RUN: llc -mtriple=arm64-linux-gnu -o - %s -mcpu=cyclone | FileCheck %s
2 ; RUN: llc -mtriple=arm64-linux-gnu -o - %s -O0 -mcpu=cyclone | FileCheck %s --check-prefix=CHECK-FAST
3 ; RUN: llc -mtriple=arm64-linux-gnu -relocation-model=pic -o - %s -mcpu=cyclone | FileCheck %s --check-prefix=CHECK-PIC
4 ; RUN: llc -mtriple=arm64-linux-gnu -O0 -relocation-model=pic -o - %s -mcpu=cyclone | FileCheck %s --check-prefix=CHECK-FAST-PIC
fp-cond-sel.ll 1 ; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-none-linux-gnu -mcpu=cyclone | FileCheck %s --check-prefix=CHECK
literal_pools_float.ll 1 ; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-none-linux-gnu -mcpu=cyclone | FileCheck %s
2 ; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-none-linux-gnu -code-model=large -mcpu=cyclone | FileCheck --check-prefix=CHECK-LARGE %s
arm64-addp.ll 1 ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -mcpu=cyclone | FileCheck %s
arm64-zero-cycle-zeroing.ll 1 ; RUN: llc -mtriple=arm64-apple-ios -mcpu=cyclone < %s | FileCheck %s
eliminate-trunc.ll 1 ; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-none-apple-ios7.0 -mcpu=cyclone | FileCheck %s
floatdp_2source.ll 1 ; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-linux-gnu -mcpu=cyclone | FileCheck %s
arm64-stp.ll 1 ; RUN: llc < %s -march=arm64 -aarch64-stp-suppress=false -verify-machineinstrs -mcpu=cyclone | FileCheck %s
3 ; RUN: -verify-machineinstrs -mcpu=cyclone | FileCheck -check-prefix=STUR_CHK %s
arm64-long-shift.ll 1 ; RUN: llc < %s -march=arm64 -mcpu=cyclone | FileCheck %s
arm64-vpopcnt.ll 1 ; RUN: llc < %s -march=arm64 -mcpu=cyclone | FileCheck %s
arm64-vshr.ll 1 ; RUN: llc -march=arm64 -aarch64-neon-syntax=apple < %s -mcpu=cyclone | FileCheck %s
  /external/llvm/test/Analysis/CostModel/AArch64/
store.ll 1 ; RUN: opt < %s -cost-model -analyze -mtriple=arm64-apple-ios -mcpu=cyclone | FileCheck %s
select.ll 1 ; RUN: opt < %s -cost-model -analyze -mtriple=arm64-apple-ios -mcpu=cyclone | FileCheck %s
  /external/llvm/lib/Target/AArch64/
AArch64.td 35 /// Cyclone has register move instructions which are "free".
39 /// Cyclone has instructions which zero registers for "free".
80 def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
81 "Cyclone",
94 def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
AArch64Subtarget.h 35 enum ARMProcFamilyEnum {Others, CortexA53, CortexA57, Cyclone};
102 bool isCyclone() const { return CPUString == "cyclone"; }
AArch64SchedCyclone.td 1 //=- ARMSchedCyclone.td - AArch64 Cyclone Scheduling Defs ----*- tablegen -*-=//
10 // This file defines the machine model for AArch64 Cyclone to support
23 // Define each kind of processor resource and number available on Cyclone.
94 // Define scheduler read/write resources and latency on Cyclone.
242 def : SchedAlias<WriteLDIdx, CyWriteLDIdx>; // Map AArch64->Cyclone type.
248 def : SchedAlias<WriteSTIdx, CyWriteSTIdx>; // Map AArch64->Cyclone type.
256 def : SchedAlias<ReadAdrBase, CyReadAdrBase>; // Map AArch64->Cyclone type.
304 // Define some longer latency vector op types for Cyclone.
317 // TODO: Add Cyclone-specific zero-cycle zeros. LLVM currently
  /external/llvm/test/Transforms/LoopStrengthReduce/AArch64/
lsr-memcpy.ll 1 ; RUN: llc -mtriple=arm64-unknown-unknown -mcpu=cyclone -pre-RA-sched=list-hybrid < %s | FileCheck %s

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