Home | History | Annotate | Download | only in AArch64
      1 ; RUN: opt < %s  -cost-model -analyze -mtriple=arm64-apple-ios -mcpu=cyclone | FileCheck %s
      2 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
      3 ; CHECK-LABEL: store
      4 define void @store() {
      5     ; Stores of <2 x i64> should be expensive because we don't split them and
      6     ; and unaligned 16b stores have bad performance.
      7     ; CHECK: cost of 12 {{.*}} store
      8     store <2 x i64> undef, <2 x i64> * undef
      9 
     10     ; We scalarize the loads/stores because there is no vector register name for
     11     ; these types (they get extended to v.4h/v.2s).
     12     ; CHECK: cost of 16 {{.*}} store
     13     store <2 x i8> undef, <2 x i8> * undef
     14     ; CHECK: cost of 64 {{.*}} store
     15     store <4 x i8> undef, <4 x i8> * undef
     16     ; CHECK: cost of 16 {{.*}} load
     17     load <2 x i8> * undef
     18     ; CHECK: cost of 64 {{.*}} load
     19     load <4 x i8> * undef
     20 
     21     ret void
     22 }
     23