| /external/llvm/lib/CodeGen/ |
| LiveRegMatrix.cpp | 75 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) {
77 << " to " << PrintReg(PhysReg, TRI) << ':');
79 VRM->assignVirt2Phys(VirtReg.reg, PhysReg);
80 MRI->setPhysRegUsed(PhysReg);
81 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
90 unsigned PhysReg = VRM->getPhys(VirtReg.reg);
92 << " from " << PrintReg(PhysReg, TRI) << ':');
94 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
103 unsigned PhysReg) {
114 // The BitVector is indexed by PhysReg, not register unit
[all...] |
| InterferenceCache.h | 39 /// of PhysReg in all basic blocks.
41 /// PhysReg - The register currently represented.
42 unsigned PhysReg;
63 /// RegUnitInfo - Information tracked about each RegUnit in PhysReg.
86 /// Info for each RegUnit in PhysReg. It is very rare ofr a PHysReg to have
97 Entry() : PhysReg(0), Tag(0), RefCount(0), Indexes(nullptr), LIS(nullptr) {}
101 PhysReg = 0;
107 unsigned getPhysReg() const { return PhysReg; }
115 /// valid - Return true if this is a valid entry for physReg
[all...] |
| RegAllocFast.cpp | 74 unsigned PhysReg; // Currently held here.
79 : LastUse(nullptr), VirtReg(v), PhysReg(0), LastOpNum(0), Dirty(false){}
124 // Mark a physreg as used in this instruction.
125 void markRegUsedInInstr(unsigned PhysReg) {
126 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units)
130 // Check if a physreg or any of its aliases are used in this instruction.
131 bool isRegUsedInInstr(unsigned PhysReg) const {
132 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units)
178 void definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState);
179 unsigned calcSpillCost(unsigned PhysReg) const
[all...] |
| InterferenceCache.cpp | 55 InterferenceCache::Entry *InterferenceCache::get(unsigned PhysReg) {
56 unsigned E = PhysRegEntries[PhysReg];
57 if (E < CacheEntries && Entries[E].getPhysReg() == PhysReg) {
73 Entries[E].reset(PhysReg, LIUArray, TRI, MF);
74 PhysRegEntries[PhysReg] = E;
88 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i)
92 void InterferenceCache::Entry::reset(unsigned physReg,
99 PhysReg = physReg;
105 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units)
[all...] |
| VirtRegMap.cpp | 250 // assigned PhysReg must be marked as live-in to those blocks.
251 unsigned PhysReg = VRM->getPhys(VirtReg);
252 assert(PhysReg != VirtRegMap::NO_PHYS_REG && "Unmapped virtual register.");
260 if (!LiveIn[i]->isLiveIn(PhysReg))
261 LiveIn[i]->addLiveIn(PhysReg);
327 // If we encounter a VirtReg or PhysReg then get at the PhysReg and add
328 // it to the physreg bitset. Later we use only the PhysRegs that were
339 unsigned PhysReg = VRM->getPhys(VirtReg);
340 assert(PhysReg != VirtRegMap::NO_PHYS_REG &
[all...] |
| RegisterClassInfo.cpp | 98 unsigned PhysReg = RawOrder[i];
100 if (Reserved.test(PhysReg))
102 unsigned Cost = TRI->getCostPerUse(PhysReg);
105 if (CSRNum[PhysReg])
106 // PhysReg aliases a CSR, save it for later.
107 CSRAlias.push_back(PhysReg);
111 RCI.Order[N++] = PhysReg;
120 unsigned PhysReg = CSRAlias[i];
121 unsigned Cost = TRI->getCostPerUse(PhysReg);
124 RCI.Order[N++] = PhysReg;
[all...] |
| RegAllocGreedy.cpp | 248 unsigned PhysReg;
253 // Interference for PhysReg.
261 PhysReg = Reg;
281 /// Candidate info for each PhysReg in AllocationOrder.
338 unsigned canReassign(LiveInterval &VirtReg, unsigned PhysReg);
343 bool mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg,
365 unsigned PhysReg, unsigned &CostPerUseLimit,
572 unsigned PhysReg;
573 while ((PhysReg = Order.next()))
574 if (!Matrix->checkInterference(VirtReg, PhysReg))
[all...] |
| RegAllocBasic.cpp | 112 bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
164 // Spill or split all live virtual registers currently unified under PhysReg
167 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
174 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
186 DEBUG(dbgs() << "spilling " << TRI->getName(PhysReg) <<
190 // Spill each interfering vreg allocated to PhysReg or an alias.
228 while (unsigned PhysReg = Order.next()) {
229 // Check for interference in PhysReg
230 switch (Matrix->checkInterference(VirtReg, PhysReg)) {
232 // PhysReg is available, allocate it
[all...] |
| AllocationOrder.h | 79 /// Return true if PhysReg is a preferred register.
80 bool isHint(unsigned PhysReg) const {
81 return std::find(Hints.begin(), Hints.end(), PhysReg) != Hints.end();
|
| ProcessImplicitDefs.cpp | 96 // This is a physreg implicit-def.
120 DEBUG(dbgs() << "Physreg user: " << *UserMI);
126 // Leave the physreg IMPLICIT_DEF, but trim any extra operands.
129 DEBUG(dbgs() << "Keeping physreg: " << *MI);
|
| RegisterCoalescer.h | 57 /// is a physreg. This register class may be a super-register of both
66 /// Create a CoalescerPair representing a virtreg-to-physreg copy.
68 CoalescerPair(unsigned VirtReg, unsigned PhysReg,
70 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
|
| DeadMachineInstructionElim.cpp | 72 // Don't delete live physreg defs, or any reserved register defs.
115 // Now scan the instructions and delete dead ones, tracking physreg
145 // Record the physreg defs.
163 // Record the physreg uses, after the defs, in case a physreg is
|
| CalcSpillWeights.cpp | 66 // Only allow physreg hints in rc.
70 // reg:sub should match the physreg hreg.
105 // Find the best physreg hint and the best virtreg hint.
168 // Always prefer the physreg hint.
|
| /external/llvm/include/llvm/CodeGen/ |
| LiveRegMatrix.h | 20 // in the physreg.
86 /// assigned to PhysReg or its aliases. This interference could be resolved
96 /// regmask operand that doesn't preserve PhysReg. This typically means
97 /// VirtReg is live across a call, and PhysReg isn't call-preserved.
101 /// Check for interference before assigning VirtReg to PhysReg.
102 /// If this function returns IK_Free, it is legal to assign(VirtReg, PhysReg).
105 InterferenceKind checkInterference(LiveInterval &VirtReg, unsigned PhysReg);
107 /// Assign VirtReg to PhysReg.
109 /// update VirtRegMap. The live range is expected to be available in PhysReg.
110 void assign(LiveInterval &VirtReg, unsigned PhysReg);
[all...] |
| RegisterClassInfo.h | 108 /// overlaps PhysReg, or 0 if Reg doesn't overlap a CSR.
109 unsigned getLastCalleeSavedAlias(unsigned PhysReg) const {
110 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg));
111 if (unsigned N = CSRNum[PhysReg])
|
| VirtRegMap.h | 105 void assignVirt2Phys(unsigned virtReg, unsigned physReg) {
107 TargetRegisterInfo::isPhysicalRegister(physReg));
111 Virt2PhysMap[virtReg] = physReg;
129 /// @brief returns true if VirtReg is assigned to its preferred physreg.
|
| MachineRegisterInfo.h | 540 /// isConstantPhysReg - Returns true if PhysReg is unallocatable and constant
542 /// a physreg.
543 bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const;
594 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
696 /// canReserveReg - Returns true if PhysReg can be used as a reserved
699 bool canReserveReg(unsigned PhysReg) const {
700 return !reservedRegsFrozen() || ReservedRegs.test(PhysReg);
713 /// isReserved - Returns true when PhysReg is a reserved register.
718 bool isReserved(unsigned PhysReg) const {
719 return getReservedRegs().test(PhysReg);
[all...] |
| /external/llvm/test/CodeGen/X86/ |
| 2011-06-14-PreschedRegalias.ll | 3 ; Test interference between physreg aliases during preRAsched.
|
| misched-copy.ll | 8 ; MUL_HiLo PhysReg use copies should be just above the mul.
9 ; MUL_HiLo PhysReg def copies should be just below the mul.
|
| phys_subreg_coalesce-3.ll | 4 ; This requires physreg joining, %vreg13 is live everywhere:
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| SIAssignInterpRegs.cpp | 39 unsigned physReg, unsigned virtReg);
124 unsigned physReg, unsigned virtReg)
127 if (!MRI.isLiveIn(physReg)) {
128 MRI.addLiveIn(physReg, virtReg);
129 MF->front().addLiveIn(physReg);
132 .addReg(physReg);
134 MRI.replaceRegWith(virtReg, MRI.getLiveInVirtReg(physReg));
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIAssignInterpRegs.cpp | 39 unsigned physReg, unsigned virtReg);
124 unsigned physReg, unsigned virtReg)
127 if (!MRI.isLiveIn(physReg)) {
128 MRI.addLiveIn(physReg, virtReg);
129 MF->front().addLiveIn(physReg);
132 .addReg(physReg);
134 MRI.replaceRegWith(virtReg, MRI.getLiveInVirtReg(physReg));
|
| /external/llvm/test/CodeGen/PowerPC/ |
| 2010-10-11-Fast-Varargs.ll | 6 ; RegAllocFast requires that each physreg only be used once. The varargs
|
| 2012-11-16-mischedcall.ll | 3 ; PR14315: misched should not move the physreg copy of %t below the calls.
|
| /external/llvm/test/CodeGen/Generic/ |
| 2006-07-03-schedulers.ll | 7 ; targets that use physreg defs.
|
