| /external/llvm/lib/Target/X86/ |
| X86InstrCMovSetCC.td | 1 //===-- X86InstrCMovSetCC.td - Conditional Move and SetCC --*- tablegen -*-===//
16 // SetCC instructions.
82 // SetCC instructions.
83 multiclass SETCC<bits<8> opc, string Mnemonic, PatLeaf OpNode> {
96 defm SETO : SETCC<0x90, "seto", X86_COND_O>; // is overflow bit set
97 defm SETNO : SETCC<0x91, "setno", X86_COND_NO>; // is overflow bit not set
98 defm SETB : SETCC<0x92, "setb", X86_COND_B>; // unsigned less than
99 defm SETAE : SETCC<0x93, "setae", X86_COND_AE>; // unsigned greater or equal
100 defm SETE : SETCC<0x94, "sete", X86_COND_E>; // equal to
101 defm SETNE : SETCC<0x95, "setne", X86_COND_NE>; // not equal t
[all...] |
| X86TargetTransformInfo.cpp | 693 { ISD::SETCC, MVT::v2f64, 1 },
694 { ISD::SETCC, MVT::v4f32, 1 },
695 { ISD::SETCC, MVT::v2i64, 1 },
696 { ISD::SETCC, MVT::v4i32, 1 },
697 { ISD::SETCC, MVT::v8i16, 1 },
698 { ISD::SETCC, MVT::v16i8, 1 },
702 { ISD::SETCC, MVT::v4f64, 1 },
703 { ISD::SETCC, MVT::v8f32, 1 },
705 { ISD::SETCC, MVT::v4i64, 4 },
706 { ISD::SETCC, MVT::v8i32, 4 }
[all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| setcc-takes-i32.ll | 4 ; correctly. Previously LLVM thought that i64 was the appropriate SetCC output,
8 ; It was expecting the smallest legal promotion of i1 to be the preferred SetCC
|
| aarch64-neon-v1i1-setcc.ll | 2 ; arm64 has a separate copy as aarch64-neon-v1i1-setcc.ll
4 ; This file test the DAG node like "v1i1 SETCC v1i64, v1i64". As the v1i1 type
6 ; As the v1i64 operands of SETCC are legal types, they will not be scalarized.
8 ; operands of SETCC have been legalized.
10 ; "v1i1 SETCC" correctly, these test cases are not needed.
|
| /external/chromium_org/v8/test/cctest/ |
| test-disasm-arm.cc | 107 COMPARE(and_(r2, r3, Operand(r4), SetCC),
114 COMPARE(eor(r4, r5, Operand(r7, LSL, 1), SetCC),
118 COMPARE(eor(r4, r5, Operand(r9, LSL, 3), SetCC, cs),
123 COMPARE(sub(r5, r6, Operand(r10, LSL, 30), SetCC, cc),
127 COMPARE(sub(r5, r6, Operand(r10, LSL, 16), SetCC, mi),
134 COMPARE(rsb(r6, r7, Operand(fp, LSR, 0), SetCC),
143 COMPARE(add(r7, r8, Operand(ip), SetCC),
145 COMPARE(add(r7, r8, Operand(ip, ASR, 31), SetCC, vs),
152 COMPARE(adc(r5, sp, Operand(ip), SetCC),
154 COMPARE(adc(r8, lr, Operand(ip, ASR, 31), SetCC, vc)
[all...] |
| /external/llvm/test/CodeGen/Mips/ |
| sitofp-selectcc-opt.ll | 8 ; (sint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
|
| /external/llvm/test/CodeGen/R600/ |
| legalizedag-bug-expand-setcc.ll | 5 ; setcc to select_cc.
|
| fcmp.ll | 17 ; This test checks that a setcc node with f32 operands is lowered to a
|
| /external/llvm/test/Transforms/LoopStrengthReduce/ |
| exit_compare_live_range.ll | 2 ; having overlapping live ranges that result in copies. We want the setcc
|
| /external/llvm/test/Transforms/ConstProp/ |
| 2002-09-03-SetCC-Bools.ll | 0 ; SetCC on boolean values was not implemented!
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.td | [all...] |
| /art/compiler/utils/arm/ |
| assembler_arm32.h | 200 void Lsl(Register rd, Register rm, uint32_t shift_imm, bool setcc = false,
202 void Lsr(Register rd, Register rm, uint32_t shift_imm, bool setcc = false,
204 void Asr(Register rd, Register rm, uint32_t shift_imm, bool setcc = false,
206 void Ror(Register rd, Register rm, uint32_t shift_imm, bool setcc = false,
208 void Rrx(Register rd, Register rm, bool setcc = false,
211 void Lsl(Register rd, Register rm, Register rn, bool setcc = false,
213 void Lsr(Register rd, Register rm, Register rn, bool setcc = false,
215 void Asr(Register rd, Register rm, Register rn, bool setcc = false,
217 void Ror(Register rd, Register rm, Register rn, bool setcc = false,
|
| assembler_thumb2.h | 231 void Lsl(Register rd, Register rm, uint32_t shift_imm, bool setcc = false,
233 void Lsr(Register rd, Register rm, uint32_t shift_imm, bool setcc = false,
235 void Asr(Register rd, Register rm, uint32_t shift_imm, bool setcc = false,
237 void Ror(Register rd, Register rm, uint32_t shift_imm, bool setcc = false,
239 void Rrx(Register rd, Register rm, bool setcc = false,
242 void Lsl(Register rd, Register rm, Register rn, bool setcc = false,
244 void Lsr(Register rd, Register rm, Register rn, bool setcc = false,
246 void Asr(Register rd, Register rm, Register rn, bool setcc = false,
248 void Ror(Register rd, Register rm, Register rn, bool setcc = false,
419 void EmitShift(Register rd, Register rm, Shift shift, uint8_t amount, bool setcc = false)
[all...] |
| assembler_arm32.cc | [all...] |
| assembler_thumb2.cc | 1092 void Thumb2Assembler::EmitShift(Register rd, Register rm, Shift shift, uint8_t amount, bool setcc) {
1107 0xf << 16 | (setcc ? B20 : 0);
[all...] |
| assembler_arm.h | 583 virtual void Lsl(Register rd, Register rm, uint32_t shift_imm, bool setcc = false,
585 virtual void Lsr(Register rd, Register rm, uint32_t shift_imm, bool setcc = false,
587 virtual void Asr(Register rd, Register rm, uint32_t shift_imm, bool setcc = false,
589 virtual void Ror(Register rd, Register rm, uint32_t shift_imm, bool setcc = false,
591 virtual void Rrx(Register rd, Register rm, bool setcc = false,
594 virtual void Lsl(Register rd, Register rm, Register rn, bool setcc = false,
596 virtual void Lsr(Register rd, Register rm, Register rn, bool setcc = false,
598 virtual void Asr(Register rd, Register rm, Register rn, bool setcc = false,
600 virtual void Ror(Register rd, Register rm, Register rn, bool setcc = false,
|
| /external/llvm/include/llvm/Target/ |
| TargetSelectionDAG.td | 144 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
398 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
[all...] |
| /external/chromium_org/third_party/icu/source/tools/gennorm2/ |
| n2builder.h | 59 void setCC(UChar32 c, uint8_t cc);
|
| /external/icu/icu4c/source/tools/gennorm2/ |
| n2builder.h | 59 void setCC(UChar32 c, uint8_t cc);
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXVector.td | [all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| SIISelLowering.cpp | 62 setTargetDAGCombine(ISD::SETCC);
318 ISD::SETCC,
384 SDValue Cond = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, CC);
403 // i1 selectcc(l, r, -1, 0, cc) -> i1 setcc(l, r, cc)
409 return DAG.getNode(ISD::SETCC, DL, VT, N->getOperand(0),
415 case ISD::SETCC: {
422 // i1 setcc (sext(i1), 0, setne) -> i1 setcc(i1, 0, setne)
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIISelLowering.cpp | 62 setTargetDAGCombine(ISD::SETCC);
318 ISD::SETCC,
384 SDValue Cond = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, CC);
403 // i1 selectcc(l, r, -1, 0, cc) -> i1 setcc(l, r, cc)
409 return DAG.getNode(ISD::SETCC, DL, VT, N->getOperand(0),
415 case ISD::SETCC: {
422 // i1 setcc (sext(i1), 0, setne) -> i1 setcc(i1, 0, setne)
|
| /external/llvm/test/CodeGen/SystemZ/ |
| setcc-01.ll | 1 ; Test SETCC for every integer condition. The tests here assume that
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 50 /// SetCC - Operand 0 is condition code, and operand 1 is the flag
52 SETCC,
|
| /external/llvm/test/Transforms/InstCombine/ |
| 2004-11-27-SetCCForCastLargerAndConstant.ll | 8 ; cast operands, and types of setCC operators. In all cases, the cast should
9 ; be eliminated. In many cases the setCC is also eliminated based on the
|
