| /external/llvm/test/CodeGen/X86/ |
| avx2-cmp.ll | 25 define <32 x i8> @v32i8-cmp(<32 x i8> %i, <32 x i8> %j) nounwind readnone {
53 define <32 x i8> @v32i8-cmpeq(<32 x i8> %i, <32 x i8> %j) nounwind readnone {
|
| avx-cmp.ll | 83 define <32 x i8> @v32i8-cmp(<32 x i8> %i, <32 x i8> %j) nounwind readnone {
127 define <32 x i8> @v32i8-cmpeq(<32 x i8> %i, <32 x i8> %j) nounwind readnone {
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineValueType.h | 70 v32i8 = 24, // 32 x i8 enumerator in enum:llvm::MVT::SimpleValueType
219 SimpleTy == MVT::v32i8 || SimpleTy == MVT::v16i16 ||
279 case v32i8:
317 case v32i8:
416 case v32i8:
523 if (NumElements == 32) return MVT::v32i8;
|
| ValueTypes.td | 47 def v32i8 : ValueType<256, 24>; // 32 x i8 vector value
|
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 142 case MVT::v32i8: return "v32i8";
210 case MVT::v32i8: return VectorType::get(Type::getInt8Ty(Context), 32);
|
| /external/llvm/lib/Target/X86/ |
| X86CallingConv.td | 49 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
249 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
271 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
295 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
419 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
427 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
|
| X86TargetTransformInfo.cpp | 219 { ISD::SHL, MVT::v32i8, 42 }, // cmpeqb sequence.
222 { ISD::SRL, MVT::v32i8, 32*10 }, // Scalarized.
225 { ISD::SRA, MVT::v32i8, 32*10 }, // Scalarized.
230 { ISD::SDIV, MVT::v32i8, 32*20 },
234 { ISD::UDIV, MVT::v32i8, 32*20 },
446 {ISD::VECTOR_SHUFFLE, MVT::v32i8, 9}
708 { ISD::SETCC, MVT::v32i8, 4 },
715 { ISD::SETCC, MVT::v32i8, 1 },
[all...] |
| X86InstrSSE.td | 343 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
344 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
360 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
416 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
420 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
425 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
427 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
428 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>
[all...] |
| X86RegisterInfo.td | 438 def VR256 : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
463 def VR256X : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
|
| X86InstrAVX512.td | 55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>
[all...] |
| X86ISelLowering.cpp | [all...] |
| X86InstrFragmentsSIMD.td | 479 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
|
| /external/llvm/lib/Target/R600/ |
| SIRegisterInfo.td | 173 def SReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add SGPR_256)>;
188 def VReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add VGPR_256)>;
|
| SIInstructions.td | [all...] |
| SIInstrInfo.td | 51 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
|
| SIISelLowering.cpp | 36 addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass);
[all...] |
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86InstComments.cpp | 83 DecodePALIGNRMask(MVT::v32i8,
173 DecodeUNPCKHMask(MVT::v32i8, ShuffleMask);
246 DecodeUNPCKLMask(MVT::v32i8, ShuffleMask);
|
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 83 case MVT::v32i8: return "MVT::v32i8";
|
| /external/llvm/include/llvm/IR/ |
| Intrinsics.td | 156 def llvm_v32i8_ty : LLVMType<v32i8>; // 32 x i8
|