| /external/llvm/lib/Target/ARM/ |
| ARMLoadStoreOptimizer.cpp | 213 case ARM::VLDRD:
497 Opcode == ARM::VLDRD);
735 case ARM::VLDRD:
877 case ARM::VLDRD:
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| Thumb1FrameLowering.cpp | 341 // Unwind MBBI to point to first LDR / VLDRD.
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| ARMBaseRegisterInfo.cpp | 518 case ARM::VLDRS: case ARM::VLDRD:
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| ARMBaseInstrInfo.cpp | [all...] |
| ARMFrameLowering.cpp | 598 // Unwind MBBI to point to first LDR / VLDRD.
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| ARMInstrVFP.td | 96 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),
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| ARMScheduleSwift.td | [all...] |
| ARMFastISel.cpp | 501 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
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| ARMConstantIslandPass.cpp | 770 case ARM::VLDRD:
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| /art/compiler/utils/arm/ |
| assembler_arm32.h | 150 void vldrd(DRegister dd, const Address& ad, Condition cond = AL) OVERRIDE;
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| assembler_arm32.cc | 903 void Arm32Assembler::vldrd(DRegister dd, const Address& ad, Condition cond) { function in class:art::arm::Arm32Assembler
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| assembler_thumb2.h | 179 void vldrd(DRegister dd, const Address& ad, Condition cond = AL) OVERRIDE;
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| assembler_thumb2.cc | 1788 void Thumb2Assembler::vldrd(DRegister dd, const Address& ad, Condition cond) { function in class:art::arm::Thumb2Assembler
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| assembler_arm.h | 475 virtual void vldrd(DRegister dd, const Address& ad, Condition cond = AL) = 0;
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| /art/compiler/dex/quick/arm/ |
| assemble_arm.cc | 412 * Note: The encoding map entries for vldrd and vldrs include REG_DEF_LR, even though
419 * another use of lr could be moved across a vldrd/vldrs. By setting REG_DEF_LR, we
420 * prevent that from happening. Note that we set REG_DEF_LR on all vldrd/vldrs - even those
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