1 /* 2 * Copyright (C) 2011 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #include "arm64_lir.h" 18 #include "codegen_arm64.h" 19 #include "dex/quick/mir_to_lir-inl.h" 20 21 namespace art { 22 23 // The macros below are exclusively used in the encoding map. 24 25 // Most generic way of providing two variants for one instructions. 26 #define CUSTOM_VARIANTS(variant1, variant2) variant1, variant2 27 28 // Used for instructions which do not have a wide variant. 29 #define NO_VARIANTS(variant) \ 30 CUSTOM_VARIANTS(variant, 0) 31 32 // Used for instructions which have a wide variant with the sf bit set to 1. 33 #define SF_VARIANTS(sf0_skeleton) \ 34 CUSTOM_VARIANTS(sf0_skeleton, (sf0_skeleton | 0x80000000)) 35 36 // Used for instructions which have a wide variant with the size bits set to either x0 or x1. 37 #define SIZE_VARIANTS(sizex0_skeleton) \ 38 CUSTOM_VARIANTS(sizex0_skeleton, (sizex0_skeleton | 0x40000000)) 39 40 // Used for instructions which have a wide variant with the sf and n bits set to 1. 41 #define SF_N_VARIANTS(sf0_n0_skeleton) \ 42 CUSTOM_VARIANTS(sf0_n0_skeleton, (sf0_n0_skeleton | 0x80400000)) 43 44 // Used for FP instructions which have a single and double precision variants, with he type bits set 45 // to either 00 or 01. 46 #define FLOAT_VARIANTS(type00_skeleton) \ 47 CUSTOM_VARIANTS(type00_skeleton, (type00_skeleton | 0x00400000)) 48 49 /* 50 * opcode: ArmOpcode enum 51 * variants: instruction skeletons supplied via CUSTOM_VARIANTS or derived macros. 52 * a{n}k: key to applying argument {n} \ 53 * a{n}s: argument {n} start bit position | n = 0, 1, 2, 3 54 * a{n}e: argument {n} end bit position / 55 * flags: instruction attributes (used in optimization) 56 * name: mnemonic name 57 * fmt: for pretty-printing 58 * fixup: used for second-pass fixes (e.g. adresses fixups in branch instructions). 59 */ 60 #define ENCODING_MAP(opcode, variants, a0k, a0s, a0e, a1k, a1s, a1e, a2k, a2s, a2e, \ 61 a3k, a3s, a3e, flags, name, fmt, fixup) \ 62 {variants, {{a0k, a0s, a0e}, {a1k, a1s, a1e}, {a2k, a2s, a2e}, \ 63 {a3k, a3s, a3e}}, opcode, flags, name, fmt, 4, fixup} 64 65 /* Instruction dump string format keys: !pf, where "!" is the start 66 * of the key, "p" is which numeric operand to use and "f" is the 67 * print format. 68 * 69 * [p]ositions: 70 * 0 -> operands[0] (dest) 71 * 1 -> operands[1] (src1) 72 * 2 -> operands[2] (src2) 73 * 3 -> operands[3] (extra) 74 * 75 * [f]ormats: 76 * d -> decimal 77 * D -> decimal*4 or decimal*8 depending on the instruction width 78 * E -> decimal*4 79 * F -> decimal*2 80 * G -> ", lsl #2" or ", lsl #3" depending on the instruction width 81 * c -> branch condition (eq, ne, etc.) 82 * t -> pc-relative target 83 * p -> pc-relative address 84 * s -> single precision floating point register 85 * S -> double precision floating point register 86 * f -> single or double precision register (depending on instruction width) 87 * I -> 8-bit immediate floating point number 88 * l -> logical immediate 89 * M -> 16-bit shift expression ("" or ", lsl #16" or ", lsl #32"...) 90 * B -> dmb option string (sy, st, ish, ishst, nsh, hshst) 91 * H -> operand shift 92 * T -> register shift (either ", lsl #0" or ", lsl #12") 93 * e -> register extend (e.g. uxtb #1) 94 * o -> register shift (e.g. lsl #1) for Word registers 95 * w -> word (32-bit) register wn, or wzr 96 * W -> word (32-bit) register wn, or wsp 97 * x -> extended (64-bit) register xn, or xzr 98 * X -> extended (64-bit) register xn, or sp 99 * r -> register with same width as instruction, r31 -> wzr, xzr 100 * R -> register with same width as instruction, r31 -> wsp, sp 101 * 102 * [!] escape. To insert "!", use "!!" 103 */ 104 /* NOTE: must be kept in sync with enum ArmOpcode from arm64_lir.h */ 105 const ArmEncodingMap Arm64Mir2Lir::EncodingMap[kA64Last] = { 106 ENCODING_MAP(WIDE(kA64Adc3rrr), SF_VARIANTS(0x1a000000), 107 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16, 108 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12, 109 "adc", "!0r, !1r, !2r", kFixupNone), 110 ENCODING_MAP(WIDE(kA64Add4RRdT), SF_VARIANTS(0x11000000), 111 kFmtRegROrSp, 4, 0, kFmtRegROrSp, 9, 5, kFmtBitBlt, 21, 10, 112 kFmtBitBlt, 23, 22, IS_QUAD_OP | REG_DEF0_USE1, 113 "add", "!0R, !1R, #!2d!3T", kFixupNone), 114 ENCODING_MAP(WIDE(kA64Add4rrro), SF_VARIANTS(0x0b000000), 115 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16, 116 kFmtShift, -1, -1, IS_QUAD_OP | REG_DEF0_USE12, 117 "add", "!0r, !1r, !2r!3o", kFixupNone), 118 ENCODING_MAP(WIDE(kA64Add4RRre), SF_VARIANTS(0x0b200000), 119 kFmtRegROrSp, 4, 0, kFmtRegROrSp, 9, 5, kFmtRegR, 20, 16, 120 kFmtExtend, -1, -1, IS_QUAD_OP | REG_DEF0_USE12, 121 "add", "!0r, !1r, !2r!3e", kFixupNone), 122 // Note: adr is binary, but declared as tertiary. The third argument is used while doing the 123 // fixups and contains information to identify the adr label. 124 ENCODING_MAP(kA64Adr2xd, NO_VARIANTS(0x10000000), 125 kFmtRegX, 4, 0, kFmtImm21, -1, -1, kFmtUnused, -1, -1, 126 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0 | NEEDS_FIXUP, 127 "adr", "!0x, #!1d", kFixupAdr), 128 ENCODING_MAP(WIDE(kA64And3Rrl), SF_VARIANTS(0x12000000), 129 kFmtRegROrSp, 4, 0, kFmtRegR, 9, 5, kFmtBitBlt, 22, 10, 130 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1, 131 "and", "!0R, !1r, #!2l", kFixupNone), 132 ENCODING_MAP(WIDE(kA64And4rrro), SF_VARIANTS(0x0a000000), 133 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16, 134 kFmtShift, -1, -1, IS_QUAD_OP | REG_DEF0_USE12, 135 "and", "!0r, !1r, !2r!3o", kFixupNone), 136 ENCODING_MAP(WIDE(kA64Asr3rrd), CUSTOM_VARIANTS(0x13007c00, 0x9340fc00), 137 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtBitBlt, 21, 16, 138 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1, 139 "asr", "!0r, !1r, #!2d", kFixupNone), 140 ENCODING_MAP(WIDE(kA64Asr3rrr), SF_VARIANTS(0x1ac02800), 141 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16, 142 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12, 143 "asr", "!0r, !1r, !2r", kFixupNone), 144 ENCODING_MAP(kA64B2ct, NO_VARIANTS(0x54000000), 145 kFmtBitBlt, 3, 0, kFmtBitBlt, 23, 5, kFmtUnused, -1, -1, 146 kFmtUnused, -1, -1, IS_BINARY_OP | IS_BRANCH | USES_CCODES | 147 NEEDS_FIXUP, "b.!0c", "!1t", kFixupCondBranch), 148 ENCODING_MAP(kA64Blr1x, NO_VARIANTS(0xd63f0000), 149 kFmtRegX, 9, 5, kFmtUnused, -1, -1, kFmtUnused, -1, -1, 150 kFmtUnused, -1, -1, 151 IS_UNARY_OP | REG_USE0 | IS_BRANCH | REG_DEF_LR, 152 "blr", "!0x", kFixupNone), 153 ENCODING_MAP(kA64Br1x, NO_VARIANTS(0xd61f0000), 154 kFmtRegX, 9, 5, kFmtUnused, -1, -1, kFmtUnused, -1, -1, 155 kFmtUnused, -1, -1, IS_UNARY_OP | REG_USE0 | IS_BRANCH, 156 "br", "!0x", kFixupNone), 157 ENCODING_MAP(kA64Brk1d, NO_VARIANTS(0xd4200000), 158 kFmtBitBlt, 20, 5, kFmtUnused, -1, -1, kFmtUnused, -1, -1, 159 kFmtUnused, -1, -1, IS_UNARY_OP | IS_BRANCH, 160 "brk", "!0d", kFixupNone), 161 ENCODING_MAP(kA64B1t, NO_VARIANTS(0x14000000), 162 kFmtBitBlt, 25, 0, kFmtUnused, -1, -1, kFmtUnused, -1, -1, 163 kFmtUnused, -1, -1, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, 164 "b", "!0t", kFixupT1Branch), 165 ENCODING_MAP(WIDE(kA64Cbnz2rt), SF_VARIANTS(0x35000000), 166 kFmtRegR, 4, 0, kFmtBitBlt, 23, 5, kFmtUnused, -1, -1, 167 kFmtUnused, -1, -1, 168 IS_BINARY_OP | REG_USE0 | IS_BRANCH | NEEDS_FIXUP, 169 "cbnz", "!0r, !1t", kFixupCBxZ), 170 ENCODING_MAP(WIDE(kA64Cbz2rt), SF_VARIANTS(0x34000000), 171 kFmtRegR, 4, 0, kFmtBitBlt, 23, 5, kFmtUnused, -1, -1, 172 kFmtUnused, -1, -1, 173 IS_BINARY_OP | REG_USE0 | IS_BRANCH | NEEDS_FIXUP, 174 "cbz", "!0r, !1t", kFixupCBxZ), 175 ENCODING_MAP(WIDE(kA64Cmn3rro), SF_VARIANTS(0x2b00001f), 176 kFmtRegR, 9, 5, kFmtRegR, 20, 16, kFmtShift, -1, -1, 177 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | SETS_CCODES, 178 "cmn", "!0r, !1r!2o", kFixupNone), 179 ENCODING_MAP(WIDE(kA64Cmn3Rre), SF_VARIANTS(0x2b20001f), 180 kFmtRegROrSp, 9, 5, kFmtRegR, 20, 16, kFmtExtend, -1, -1, 181 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | SETS_CCODES, 182 "cmn", "!0R, !1r!2e", kFixupNone), 183 ENCODING_MAP(WIDE(kA64Cmn3RdT), SF_VARIANTS(0x3100001f), 184 kFmtRegROrSp, 9, 5, kFmtBitBlt, 21, 10, kFmtBitBlt, 23, 22, 185 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, 186 "cmn", "!0R, #!1d!2T", kFixupNone), 187 ENCODING_MAP(WIDE(kA64Cmp3rro), SF_VARIANTS(0x6b00001f), 188 kFmtRegR, 9, 5, kFmtRegR, 20, 16, kFmtShift, -1, -1, 189 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | SETS_CCODES, 190 "cmp", "!0r, !1r!2o", kFixupNone), 191 ENCODING_MAP(WIDE(kA64Cmp3Rre), SF_VARIANTS(0x6b20001f), 192 kFmtRegROrSp, 9, 5, kFmtRegR, 20, 16, kFmtExtend, -1, -1, 193 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | SETS_CCODES, 194 "cmp", "!0R, !1r!2e", kFixupNone), 195 ENCODING_MAP(WIDE(kA64Cmp3RdT), SF_VARIANTS(0x7100001f), 196 kFmtRegROrSp, 9, 5, kFmtBitBlt, 21, 10, kFmtBitBlt, 23, 22, 197 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, 198 "cmp", "!0R, #!1d!2T", kFixupNone), 199 ENCODING_MAP(WIDE(kA64Csel4rrrc), SF_VARIANTS(0x1a800000), 200 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16, 201 kFmtBitBlt, 15, 12, IS_QUAD_OP | REG_DEF0_USE12 | USES_CCODES, 202 "csel", "!0r, !1r, !2r, !3c", kFixupNone), 203 ENCODING_MAP(WIDE(kA64Csinc4rrrc), SF_VARIANTS(0x1a800400), 204 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16, 205 kFmtBitBlt, 15, 12, IS_QUAD_OP | REG_DEF0_USE12 | USES_CCODES, 206 "csinc", "!0r, !1r, !2r, !3c", kFixupNone), 207 ENCODING_MAP(WIDE(kA64Csinv4rrrc), SF_VARIANTS(0x5a800000), 208 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16, 209 kFmtBitBlt, 15, 12, IS_QUAD_OP | REG_DEF0_USE12 | USES_CCODES, 210 "csinv", "!0r, !1r, !2r, !3c", kFixupNone), 211 ENCODING_MAP(WIDE(kA64Csneg4rrrc), SF_VARIANTS(0x5a800400), 212 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16, 213 kFmtBitBlt, 15, 12, IS_QUAD_OP | REG_DEF0_USE12 | USES_CCODES, 214 "csneg", "!0r, !1r, !2r, !3c", kFixupNone), 215 ENCODING_MAP(kA64Dmb1B, NO_VARIANTS(0xd50330bf), 216 kFmtBitBlt, 11, 8, kFmtUnused, -1, -1, kFmtUnused, -1, -1, 217 kFmtUnused, -1, -1, IS_UNARY_OP | IS_VOLATILE, 218 "dmb", "#!0B", kFixupNone), 219 ENCODING_MAP(WIDE(kA64Eor3Rrl), SF_VARIANTS(0x52000000), 220 kFmtRegROrSp, 4, 0, kFmtRegR, 9, 5, kFmtBitBlt, 22, 10, 221 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1, 222 "eor", "!0R, !1r, #!2l", kFixupNone), 223 ENCODING_MAP(WIDE(kA64Eor4rrro), SF_VARIANTS(0x4a000000), 224 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16, 225 kFmtShift, -1, -1, IS_QUAD_OP | REG_DEF0_USE12, 226 "eor", "!0r, !1r, !2r!3o", kFixupNone), 227 ENCODING_MAP(WIDE(kA64Extr4rrrd), SF_N_VARIANTS(0x13800000), 228 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16, 229 kFmtBitBlt, 15, 10, IS_QUAD_OP | REG_DEF0_USE12, 230 "extr", "!0r, !1r, !2r, #!3d", kFixupNone), 231 ENCODING_MAP(FWIDE(kA64Fabs2ff), FLOAT_VARIANTS(0x1e20c000), 232 kFmtRegF, 4, 0, kFmtRegF, 9, 5, kFmtUnused, -1, -1, 233 kFmtUnused, -1, -1, IS_BINARY_OP| REG_DEF0_USE1, 234 "fabs", "!0f, !1f", kFixupNone), 235 ENCODING_MAP(FWIDE(kA64Fadd3fff), FLOAT_VARIANTS(0x1e202800), 236 kFmtRegF, 4, 0, kFmtRegF, 9, 5, kFmtRegF, 20, 16, 237 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12, 238 "fadd", "!0f, !1f, !2f", kFixupNone), 239 ENCODING_MAP(FWIDE(kA64Fcmp1f), FLOAT_VARIANTS(0x1e202008), 240 kFmtRegF, 9, 5, kFmtUnused, -1, -1, kFmtUnused, -1, -1, 241 kFmtUnused, -1, -1, IS_UNARY_OP | REG_USE0 | SETS_CCODES, 242 "fcmp", "!0f, #0", kFixupNone), 243 ENCODING_MAP(FWIDE(kA64Fcmp2ff), FLOAT_VARIANTS(0x1e202000), 244 kFmtRegF, 9, 5, kFmtRegF, 20, 16, kFmtUnused, -1, -1, 245 kFmtUnused, -1, -1, IS_BINARY_OP | REG_USE01 | SETS_CCODES, 246 "fcmp", "!0f, !1f", kFixupNone), 247 ENCODING_MAP(FWIDE(kA64Fcvtzs2wf), FLOAT_VARIANTS(0x1e380000), 248 kFmtRegW, 4, 0, kFmtRegF, 9, 5, kFmtUnused, -1, -1, 249 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, 250 "fcvtzs", "!0w, !1f", kFixupNone), 251 ENCODING_MAP(FWIDE(kA64Fcvtzs2xf), FLOAT_VARIANTS(0x9e380000), 252 kFmtRegX, 4, 0, kFmtRegF, 9, 5, kFmtUnused, -1, -1, 253 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, 254 "fcvtzs", "!0x, !1f", kFixupNone), 255 ENCODING_MAP(kA64Fcvt2Ss, NO_VARIANTS(0x1e22C000), 256 kFmtRegD, 4, 0, kFmtRegS, 9, 5, kFmtUnused, -1, -1, 257 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, 258 "fcvt", "!0S, !1s", kFixupNone), 259 ENCODING_MAP(kA64Fcvt2sS, NO_VARIANTS(0x1e624000), 260 kFmtRegS, 4, 0, kFmtRegD, 9, 5, kFmtUnused, -1, -1, 261 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, 262 "fcvt", "!0s, !1S", kFixupNone), 263 ENCODING_MAP(kA64Fcvtms2ws, NO_VARIANTS(0x1e300000), 264 kFmtRegW, 4, 0, kFmtRegS, 9, 5, kFmtUnused, -1, -1, 265 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, 266 "fcvtms", "!0w, !1s", kFixupNone), 267 ENCODING_MAP(kA64Fcvtms2xS, NO_VARIANTS(0x9e700000), 268 kFmtRegX, 4, 0, kFmtRegD, 9, 5, kFmtUnused, -1, -1, 269 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, 270 "fcvtms", "!0x, !1S", kFixupNone), 271 ENCODING_MAP(FWIDE(kA64Fdiv3fff), FLOAT_VARIANTS(0x1e201800), 272 kFmtRegF, 4, 0, kFmtRegF, 9, 5, kFmtRegF, 20, 16, 273 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12, 274 "fdiv", "!0f, !1f, !2f", kFixupNone), 275 ENCODING_MAP(FWIDE(kA64Fmax3fff), FLOAT_VARIANTS(0x1e204800), 276 kFmtRegF, 4, 0, kFmtRegF, 9, 5, kFmtRegF, 20, 16, 277 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12, 278 "fmax", "!0f, !1f, !2f", kFixupNone), 279 ENCODING_MAP(FWIDE(kA64Fmin3fff), FLOAT_VARIANTS(0x1e205800), 280 kFmtRegF, 4, 0, kFmtRegF, 9, 5, kFmtRegF, 20, 16, 281 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12, 282 "fmin", "!0f, !1f, !2f", kFixupNone), 283 ENCODING_MAP(FWIDE(kA64Fmov2ff), FLOAT_VARIANTS(0x1e204000), 284 kFmtRegF, 4, 0, kFmtRegF, 9, 5, kFmtUnused, -1, -1, 285 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1 | IS_MOVE, 286 "fmov", "!0f, !1f", kFixupNone), 287 ENCODING_MAP(FWIDE(kA64Fmov2fI), FLOAT_VARIANTS(0x1e201000), 288 kFmtRegF, 4, 0, kFmtBitBlt, 20, 13, kFmtUnused, -1, -1, 289 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0, 290 "fmov", "!0f, #!1I", kFixupNone), 291 ENCODING_MAP(kA64Fmov2sw, NO_VARIANTS(0x1e270000), 292 kFmtRegS, 4, 0, kFmtRegW, 9, 5, kFmtUnused, -1, -1, 293 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, 294 "fmov", "!0s, !1w", kFixupNone), 295 ENCODING_MAP(kA64Fmov2Sx, NO_VARIANTS(0x9e670000), 296 kFmtRegD, 4, 0, kFmtRegX, 9, 5, kFmtUnused, -1, -1, 297 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, 298 "fmov", "!0S, !1x", kFixupNone), 299 ENCODING_MAP(kA64Fmov2ws, NO_VARIANTS(0x1e260000), 300 kFmtRegW, 4, 0, kFmtRegS, 9, 5, kFmtUnused, -1, -1, 301 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, 302 "fmov", "!0w, !1s", kFixupNone), 303 ENCODING_MAP(kA64Fmov2xS, NO_VARIANTS(0x9e660000), 304 kFmtRegX, 4, 0, kFmtRegD, 9, 5, kFmtUnused, -1, -1, 305 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, 306 "fmov", "!0x, !1S", kFixupNone), 307 ENCODING_MAP(FWIDE(kA64Fmul3fff), FLOAT_VARIANTS(0x1e200800), 308 kFmtRegF, 4, 0, kFmtRegF, 9, 5, kFmtRegF, 20, 16, 309 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12, 310 "fmul", "!0f, !1f, !2f", kFixupNone), 311 ENCODING_MAP(FWIDE(kA64Fneg2ff), FLOAT_VARIANTS(0x1e214000), 312 kFmtRegF, 4, 0, kFmtRegF, 9, 5, kFmtUnused, -1, -1, 313 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, 314 "fneg", "!0f, !1f", kFixupNone), 315 ENCODING_MAP(FWIDE(kA64Frintp2ff), FLOAT_VARIANTS(0x1e24c000), 316 kFmtRegF, 4, 0, kFmtRegF, 9, 5, kFmtUnused, -1, -1, 317 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, 318 "frintp", "!0f, !1f", kFixupNone), 319 ENCODING_MAP(FWIDE(kA64Frintm2ff), FLOAT_VARIANTS(0x1e254000), 320 kFmtRegF, 4, 0, kFmtRegF, 9, 5, kFmtUnused, -1, -1, 321 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, 322 "frintm", "!0f, !1f", kFixupNone), 323 ENCODING_MAP(FWIDE(kA64Frintn2ff), FLOAT_VARIANTS(0x1e244000), 324 kFmtRegF, 4, 0, kFmtRegF, 9, 5, kFmtUnused, -1, -1, 325 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, 326 "frintn", "!0f, !1f", kFixupNone), 327 ENCODING_MAP(FWIDE(kA64Frintz2ff), FLOAT_VARIANTS(0x1e25c000), 328 kFmtRegF, 4, 0, kFmtRegF, 9, 5, kFmtUnused, -1, -1, 329 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, 330 "frintz", "!0f, !1f", kFixupNone), 331 ENCODING_MAP(FWIDE(kA64Fsqrt2ff), FLOAT_VARIANTS(0x1e61c000), 332 kFmtRegF, 4, 0, kFmtRegF, 9, 5, kFmtUnused, -1, -1, 333 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, 334 "fsqrt", "!0f, !1f", kFixupNone), 335 ENCODING_MAP(FWIDE(kA64Fsub3fff), FLOAT_VARIANTS(0x1e203800), 336 kFmtRegF, 4, 0, kFmtRegF, 9, 5, kFmtRegF, 20, 16, 337 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12, 338 "fsub", "!0f, !1f, !2f", kFixupNone), 339 ENCODING_MAP(kA64Ldrb3wXd, NO_VARIANTS(0x39400000), 340 kFmtRegW, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 21, 10, 341 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD_OFF, 342 "ldrb", "!0w, [!1X, #!2d]", kFixupNone), 343 ENCODING_MAP(kA64Ldrb3wXx, NO_VARIANTS(0x38606800), 344 kFmtRegW, 4, 0, kFmtRegXOrSp, 9, 5, kFmtRegX, 20, 16, 345 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12 | IS_LOAD, 346 "ldrb", "!0w, [!1X, !2x]", kFixupNone), 347 ENCODING_MAP(WIDE(kA64Ldrsb3rXd), CUSTOM_VARIANTS(0x39c00000, 0x39800000), 348 kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 21, 10, 349 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD_OFF, 350 "ldrsb", "!0r, [!1X, #!2d]", kFixupNone), 351 ENCODING_MAP(WIDE(kA64Ldrsb3rXx), CUSTOM_VARIANTS(0x38e06800, 0x38a06800), 352 kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, kFmtRegX, 20, 16, 353 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12 | IS_LOAD, 354 "ldrsb", "!0r, [!1X, !2x]", kFixupNone), 355 ENCODING_MAP(kA64Ldrh3wXF, NO_VARIANTS(0x79400000), 356 kFmtRegW, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 21, 10, 357 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD_OFF, 358 "ldrh", "!0w, [!1X, #!2F]", kFixupNone), 359 ENCODING_MAP(kA64Ldrh4wXxd, NO_VARIANTS(0x78606800), 360 kFmtRegW, 4, 0, kFmtRegXOrSp, 9, 5, kFmtRegX, 20, 16, 361 kFmtBitBlt, 12, 12, IS_QUAD_OP | REG_DEF0_USE12 | IS_LOAD_OFF, 362 "ldrh", "!0w, [!1X, !2x, lsl #!3d]", kFixupNone), 363 ENCODING_MAP(WIDE(kA64Ldrsh3rXF), CUSTOM_VARIANTS(0x79c00000, 0x79800000), 364 kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 21, 10, 365 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD_OFF, 366 "ldrsh", "!0r, [!1X, #!2F]", kFixupNone), 367 ENCODING_MAP(WIDE(kA64Ldrsh4rXxd), CUSTOM_VARIANTS(0x78e06800, 0x78906800), 368 kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, kFmtRegX, 20, 16, 369 kFmtBitBlt, 12, 12, IS_QUAD_OP | REG_DEF0_USE12 | IS_LOAD_OFF, 370 "ldrsh", "!0r, [!1X, !2x, lsl #!3d]", kFixupNone), 371 ENCODING_MAP(FWIDE(kA64Ldr2fp), SIZE_VARIANTS(0x1c000000), 372 kFmtRegF, 4, 0, kFmtBitBlt, 23, 5, kFmtUnused, -1, -1, 373 kFmtUnused, -1, -1, 374 IS_BINARY_OP | REG_DEF0 | REG_USE_PC | IS_LOAD | NEEDS_FIXUP, 375 "ldr", "!0f, !1p", kFixupLoad), 376 ENCODING_MAP(WIDE(kA64Ldr2rp), SIZE_VARIANTS(0x18000000), 377 kFmtRegR, 4, 0, kFmtBitBlt, 23, 5, kFmtUnused, -1, -1, 378 kFmtUnused, -1, -1, 379 IS_BINARY_OP | REG_DEF0 | REG_USE_PC | IS_LOAD | NEEDS_FIXUP, 380 "ldr", "!0r, !1p", kFixupLoad), 381 ENCODING_MAP(FWIDE(kA64Ldr3fXD), SIZE_VARIANTS(0xbd400000), 382 kFmtRegF, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 21, 10, 383 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD_OFF, 384 "ldr", "!0f, [!1X, #!2D]", kFixupNone), 385 ENCODING_MAP(WIDE(kA64Ldr3rXD), SIZE_VARIANTS(0xb9400000), 386 kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 21, 10, 387 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD_OFF, 388 "ldr", "!0r, [!1X, #!2D]", kFixupNone), 389 ENCODING_MAP(FWIDE(kA64Ldr4fXxG), SIZE_VARIANTS(0xbc606800), 390 kFmtRegF, 4, 0, kFmtRegXOrSp, 9, 5, kFmtRegX, 20, 16, 391 kFmtBitBlt, 12, 12, IS_QUAD_OP | REG_DEF0_USE12 | IS_LOAD, 392 "ldr", "!0f, [!1X, !2x!3G]", kFixupNone), 393 ENCODING_MAP(WIDE(kA64Ldr4rXxG), SIZE_VARIANTS(0xb8606800), 394 kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, kFmtRegX, 20, 16, 395 kFmtBitBlt, 12, 12, IS_QUAD_OP | REG_DEF0_USE12 | IS_LOAD, 396 "ldr", "!0r, [!1X, !2x!3G]", kFixupNone), 397 ENCODING_MAP(WIDE(kA64LdrPost3rXd), SIZE_VARIANTS(0xb8400400), 398 kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 20, 12, 399 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF01 | REG_USE1 | IS_LOAD, 400 "ldr", "!0r, [!1X], #!2d", kFixupNone), 401 ENCODING_MAP(WIDE(kA64Ldp4ffXD), CUSTOM_VARIANTS(0x2d400000, 0x6d400000), 402 kFmtRegF, 4, 0, kFmtRegF, 14, 10, kFmtRegXOrSp, 9, 5, 403 kFmtBitBlt, 21, 15, IS_QUAD_OP | REG_USE2 | REG_DEF01 | IS_LOAD_OFF, 404 "ldp", "!0f, !1f, [!2X, #!3D]", kFixupNone), 405 ENCODING_MAP(WIDE(kA64Ldp4rrXD), SF_VARIANTS(0x29400000), 406 kFmtRegR, 4, 0, kFmtRegR, 14, 10, kFmtRegXOrSp, 9, 5, 407 kFmtBitBlt, 21, 15, IS_QUAD_OP | REG_USE2 | REG_DEF01 | IS_LOAD_OFF, 408 "ldp", "!0r, !1r, [!2X, #!3D]", kFixupNone), 409 ENCODING_MAP(WIDE(kA64LdpPost4rrXD), CUSTOM_VARIANTS(0x28c00000, 0xa8c00000), 410 kFmtRegR, 4, 0, kFmtRegR, 14, 10, kFmtRegXOrSp, 9, 5, 411 kFmtBitBlt, 21, 15, IS_QUAD_OP | REG_USE2 | REG_DEF012 | IS_LOAD, 412 "ldp", "!0r, !1r, [!2X], #!3D", kFixupNone), 413 ENCODING_MAP(FWIDE(kA64Ldur3fXd), CUSTOM_VARIANTS(0xbc400000, 0xfc400000), 414 kFmtRegF, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 20, 12, 415 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD, 416 "ldur", "!0f, [!1X, #!2d]", kFixupNone), 417 ENCODING_MAP(WIDE(kA64Ldur3rXd), SIZE_VARIANTS(0xb8400000), 418 kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 20, 12, 419 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD, 420 "ldur", "!0r, [!1X, #!2d]", kFixupNone), 421 ENCODING_MAP(WIDE(kA64Ldxr2rX), SIZE_VARIANTS(0x885f7c00), 422 kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, kFmtUnused, -1, -1, 423 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1 | IS_LOADX, 424 "ldxr", "!0r, [!1X]", kFixupNone), 425 ENCODING_MAP(WIDE(kA64Ldaxr2rX), SIZE_VARIANTS(0x885ffc00), 426 kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, kFmtUnused, -1, -1, 427 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1 | IS_LOADX, 428 "ldaxr", "!0r, [!1X]", kFixupNone), 429 ENCODING_MAP(WIDE(kA64Lsl3rrr), SF_VARIANTS(0x1ac02000), 430 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16, 431 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12, 432 "lsl", "!0r, !1r, !2r", kFixupNone), 433 ENCODING_MAP(WIDE(kA64Lsr3rrd), CUSTOM_VARIANTS(0x53007c00, 0xd340fc00), 434 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtBitBlt, 21, 16, 435 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1, 436 "lsr", "!0r, !1r, #!2d", kFixupNone), 437 ENCODING_MAP(WIDE(kA64Lsr3rrr), SF_VARIANTS(0x1ac02400), 438 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16, 439 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12, 440 "lsr", "!0r, !1r, !2r", kFixupNone), 441 ENCODING_MAP(WIDE(kA64Movk3rdM), SF_VARIANTS(0x72800000), 442 kFmtRegR, 4, 0, kFmtBitBlt, 20, 5, kFmtBitBlt, 22, 21, 443 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE0, 444 "movk", "!0r, #!1d!2M", kFixupNone), 445 ENCODING_MAP(WIDE(kA64Movn3rdM), SF_VARIANTS(0x12800000), 446 kFmtRegR, 4, 0, kFmtBitBlt, 20, 5, kFmtBitBlt, 22, 21, 447 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0, 448 "movn", "!0r, #!1d!2M", kFixupNone), 449 ENCODING_MAP(WIDE(kA64Movz3rdM), SF_VARIANTS(0x52800000), 450 kFmtRegR, 4, 0, kFmtBitBlt, 20, 5, kFmtBitBlt, 22, 21, 451 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0, 452 "movz", "!0r, #!1d!2M", kFixupNone), 453 ENCODING_MAP(WIDE(kA64Mov2rr), SF_VARIANTS(0x2a0003e0), 454 kFmtRegR, 4, 0, kFmtRegR, 20, 16, kFmtUnused, -1, -1, 455 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1 | IS_MOVE, 456 "mov", "!0r, !1r", kFixupNone), 457 ENCODING_MAP(WIDE(kA64Mvn2rr), SF_VARIANTS(0x2a2003e0), 458 kFmtRegR, 4, 0, kFmtRegR, 20, 16, kFmtUnused, -1, -1, 459 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, 460 "mvn", "!0r, !1r", kFixupNone), 461 ENCODING_MAP(WIDE(kA64Mul3rrr), SF_VARIANTS(0x1b007c00), 462 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16, 463 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12, 464 "mul", "!0r, !1r, !2r", kFixupNone), 465 ENCODING_MAP(WIDE(kA64Msub4rrrr), SF_VARIANTS(0x1b008000), 466 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 14, 10, 467 kFmtRegR, 20, 16, IS_QUAD_OP | REG_DEF0_USE123, 468 "msub", "!0r, !1r, !3r, !2r", kFixupNone), 469 ENCODING_MAP(WIDE(kA64Neg3rro), SF_VARIANTS(0x4b0003e0), 470 kFmtRegR, 4, 0, kFmtRegR, 20, 16, kFmtShift, -1, -1, 471 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1, 472 "neg", "!0r, !1r!2o", kFixupNone), 473 ENCODING_MAP(WIDE(kA64Orr3Rrl), SF_VARIANTS(0x32000000), 474 kFmtRegROrSp, 4, 0, kFmtRegR, 9, 5, kFmtBitBlt, 22, 10, 475 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1, 476 "orr", "!0R, !1r, #!2l", kFixupNone), 477 ENCODING_MAP(WIDE(kA64Orr4rrro), SF_VARIANTS(0x2a000000), 478 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16, 479 kFmtShift, -1, -1, IS_QUAD_OP | REG_DEF0_USE12, 480 "orr", "!0r, !1r, !2r!3o", kFixupNone), 481 ENCODING_MAP(kA64Ret, NO_VARIANTS(0xd65f03c0), 482 kFmtUnused, -1, -1, kFmtUnused, -1, -1, kFmtUnused, -1, -1, 483 kFmtUnused, -1, -1, NO_OPERAND | IS_BRANCH, 484 "ret", "", kFixupNone), 485 ENCODING_MAP(WIDE(kA64Rbit2rr), SF_VARIANTS(0x5ac00000), 486 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtUnused, -1, -1, 487 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, 488 "rbit", "!0r, !1r", kFixupNone), 489 ENCODING_MAP(WIDE(kA64Rev2rr), CUSTOM_VARIANTS(0x5ac00800, 0xdac00c00), 490 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtUnused, -1, -1, 491 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, 492 "rev", "!0r, !1r", kFixupNone), 493 ENCODING_MAP(WIDE(kA64Rev162rr), SF_VARIANTS(0x5ac00400), 494 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtUnused, -1, -1, 495 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, 496 "rev16", "!0r, !1r", kFixupNone), 497 ENCODING_MAP(WIDE(kA64Ror3rrr), SF_VARIANTS(0x1ac02c00), 498 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16, 499 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12, 500 "ror", "!0r, !1r, !2r", kFixupNone), 501 ENCODING_MAP(WIDE(kA64Sbc3rrr), SF_VARIANTS(0x5a000000), 502 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16, 503 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12, 504 "sbc", "!0r, !1r, !2r", kFixupNone), 505 ENCODING_MAP(WIDE(kA64Sbfm4rrdd), SF_N_VARIANTS(0x13000000), 506 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtBitBlt, 21, 16, 507 kFmtBitBlt, 15, 10, IS_QUAD_OP | REG_DEF0_USE1, 508 "sbfm", "!0r, !1r, #!2d, #!3d", kFixupNone), 509 ENCODING_MAP(FWIDE(kA64Scvtf2fw), FLOAT_VARIANTS(0x1e220000), 510 kFmtRegF, 4, 0, kFmtRegW, 9, 5, kFmtUnused, -1, -1, 511 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, 512 "scvtf", "!0f, !1w", kFixupNone), 513 ENCODING_MAP(FWIDE(kA64Scvtf2fx), FLOAT_VARIANTS(0x9e220000), 514 kFmtRegF, 4, 0, kFmtRegX, 9, 5, kFmtUnused, -1, -1, 515 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1, 516 "scvtf", "!0f, !1x", kFixupNone), 517 ENCODING_MAP(WIDE(kA64Sdiv3rrr), SF_VARIANTS(0x1ac00c00), 518 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16, 519 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12, 520 "sdiv", "!0r, !1r, !2r", kFixupNone), 521 ENCODING_MAP(WIDE(kA64Smaddl4xwwx), NO_VARIANTS(0x9b200000), 522 kFmtRegX, 4, 0, kFmtRegW, 9, 5, kFmtRegW, 20, 16, 523 kFmtRegX, 14, 10, IS_QUAD_OP | REG_DEF0_USE123, 524 "smaddl", "!0x, !1w, !2w, !3x", kFixupNone), 525 ENCODING_MAP(kA64Smulh3xxx, NO_VARIANTS(0x9b407c00), 526 kFmtRegX, 4, 0, kFmtRegX, 9, 5, kFmtRegX, 20, 16, 527 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12, 528 "smulh", "!0x, !1x, !2x", kFixupNone), 529 ENCODING_MAP(WIDE(kA64Stp4ffXD), CUSTOM_VARIANTS(0x2d000000, 0x6d000000), 530 kFmtRegF, 4, 0, kFmtRegF, 14, 10, kFmtRegXOrSp, 9, 5, 531 kFmtBitBlt, 21, 15, IS_QUAD_OP | REG_USE012 | IS_STORE_OFF, 532 "stp", "!0f, !1f, [!2X, #!3D]", kFixupNone), 533 ENCODING_MAP(WIDE(kA64Stp4rrXD), SF_VARIANTS(0x29000000), 534 kFmtRegR, 4, 0, kFmtRegR, 14, 10, kFmtRegXOrSp, 9, 5, 535 kFmtBitBlt, 21, 15, IS_QUAD_OP | REG_USE012 | IS_STORE_OFF, 536 "stp", "!0r, !1r, [!2X, #!3D]", kFixupNone), 537 ENCODING_MAP(WIDE(kA64StpPost4rrXD), CUSTOM_VARIANTS(0x28800000, 0xa8800000), 538 kFmtRegR, 4, 0, kFmtRegR, 14, 10, kFmtRegXOrSp, 9, 5, 539 kFmtBitBlt, 21, 15, IS_QUAD_OP | REG_DEF2 | REG_USE012 | IS_STORE, 540 "stp", "!0r, !1r, [!2X], #!3D", kFixupNone), 541 ENCODING_MAP(WIDE(kA64StpPre4ffXD), CUSTOM_VARIANTS(0x2d800000, 0x6d800000), 542 kFmtRegF, 4, 0, kFmtRegF, 14, 10, kFmtRegXOrSp, 9, 5, 543 kFmtBitBlt, 21, 15, IS_QUAD_OP | REG_DEF2 | REG_USE012 | IS_STORE, 544 "stp", "!0f, !1f, [!2X, #!3D]!!", kFixupNone), 545 ENCODING_MAP(WIDE(kA64StpPre4rrXD), CUSTOM_VARIANTS(0x29800000, 0xa9800000), 546 kFmtRegR, 4, 0, kFmtRegR, 14, 10, kFmtRegXOrSp, 9, 5, 547 kFmtBitBlt, 21, 15, IS_QUAD_OP | REG_DEF2 | REG_USE012 | IS_STORE, 548 "stp", "!0r, !1r, [!2X, #!3D]!!", kFixupNone), 549 ENCODING_MAP(FWIDE(kA64Str3fXD), CUSTOM_VARIANTS(0xbd000000, 0xfd000000), 550 kFmtRegF, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 21, 10, 551 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | IS_STORE_OFF, 552 "str", "!0f, [!1X, #!2D]", kFixupNone), 553 ENCODING_MAP(FWIDE(kA64Str4fXxG), CUSTOM_VARIANTS(0xbc206800, 0xfc206800), 554 kFmtRegF, 4, 0, kFmtRegXOrSp, 9, 5, kFmtRegX, 20, 16, 555 kFmtBitBlt, 12, 12, IS_QUAD_OP | REG_USE012 | IS_STORE, 556 "str", "!0f, [!1X, !2x!3G]", kFixupNone), 557 ENCODING_MAP(WIDE(kA64Str3rXD), SIZE_VARIANTS(0xb9000000), 558 kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 21, 10, 559 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | IS_STORE_OFF, 560 "str", "!0r, [!1X, #!2D]", kFixupNone), 561 ENCODING_MAP(WIDE(kA64Str4rXxG), SIZE_VARIANTS(0xb8206800), 562 kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, kFmtRegX, 20, 16, 563 kFmtBitBlt, 12, 12, IS_QUAD_OP | REG_USE012 | IS_STORE, 564 "str", "!0r, [!1X, !2x!3G]", kFixupNone), 565 ENCODING_MAP(kA64Strb3wXd, NO_VARIANTS(0x39000000), 566 kFmtRegW, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 21, 10, 567 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | IS_STORE_OFF, 568 "strb", "!0w, [!1X, #!2d]", kFixupNone), 569 ENCODING_MAP(kA64Strb3wXx, NO_VARIANTS(0x38206800), 570 kFmtRegW, 4, 0, kFmtRegXOrSp, 9, 5, kFmtRegX, 20, 16, 571 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE012 | IS_STORE, 572 "strb", "!0w, [!1X, !2x]", kFixupNone), 573 ENCODING_MAP(kA64Strh3wXF, NO_VARIANTS(0x79000000), 574 kFmtRegW, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 21, 10, 575 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | IS_STORE_OFF, 576 "strh", "!0w, [!1X, #!2F]", kFixupNone), 577 ENCODING_MAP(kA64Strh4wXxd, NO_VARIANTS(0x78206800), 578 kFmtRegW, 4, 0, kFmtRegXOrSp, 9, 5, kFmtRegX, 20, 16, 579 kFmtBitBlt, 12, 12, IS_QUAD_OP | REG_USE012 | IS_STORE, 580 "strh", "!0w, [!1X, !2x, lsl #!3d]", kFixupNone), 581 ENCODING_MAP(WIDE(kA64StrPost3rXd), SIZE_VARIANTS(0xb8000400), 582 kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 20, 12, 583 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | REG_DEF1 | IS_STORE, 584 "str", "!0r, [!1X], #!2d", kFixupNone), 585 ENCODING_MAP(FWIDE(kA64Stur3fXd), CUSTOM_VARIANTS(0xbc000000, 0xfc000000), 586 kFmtRegF, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 20, 12, 587 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | IS_STORE, 588 "stur", "!0f, [!1X, #!2d]", kFixupNone), 589 ENCODING_MAP(WIDE(kA64Stur3rXd), SIZE_VARIANTS(0xb8000000), 590 kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 20, 12, 591 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | IS_STORE, 592 "stur", "!0r, [!1X, #!2d]", kFixupNone), 593 ENCODING_MAP(WIDE(kA64Stxr3wrX), SIZE_VARIANTS(0x88007c00), 594 kFmtRegW, 20, 16, kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, 595 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12 | IS_STOREX, 596 "stxr", "!0w, !1r, [!2X]", kFixupNone), 597 ENCODING_MAP(WIDE(kA64Stlxr3wrX), SIZE_VARIANTS(0x8800fc00), 598 kFmtRegW, 20, 16, kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, 599 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12 | IS_STOREX, 600 "stlxr", "!0w, !1r, [!2X]", kFixupNone), 601 ENCODING_MAP(WIDE(kA64Sub4RRdT), SF_VARIANTS(0x51000000), 602 kFmtRegROrSp, 4, 0, kFmtRegROrSp, 9, 5, kFmtBitBlt, 21, 10, 603 kFmtBitBlt, 23, 22, IS_QUAD_OP | REG_DEF0_USE1, 604 "sub", "!0R, !1R, #!2d!3T", kFixupNone), 605 ENCODING_MAP(WIDE(kA64Sub4rrro), SF_VARIANTS(0x4b000000), 606 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16, 607 kFmtShift, -1, -1, IS_QUAD_OP | REG_DEF0_USE12, 608 "sub", "!0r, !1r, !2r!3o", kFixupNone), 609 ENCODING_MAP(WIDE(kA64Sub4RRre), SF_VARIANTS(0x4b200000), 610 kFmtRegROrSp, 4, 0, kFmtRegROrSp, 9, 5, kFmtRegR, 20, 16, 611 kFmtExtend, -1, -1, IS_QUAD_OP | REG_DEF0_USE12, 612 "sub", "!0r, !1r, !2r!3e", kFixupNone), 613 ENCODING_MAP(WIDE(kA64Subs3rRd), SF_VARIANTS(0x71000000), 614 kFmtRegR, 4, 0, kFmtRegROrSp, 9, 5, kFmtBitBlt, 21, 10, 615 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, 616 "subs", "!0r, !1R, #!2d", kFixupNone), 617 ENCODING_MAP(WIDE(kA64Tst3rro), SF_VARIANTS(0x6a000000), 618 kFmtRegR, 9, 5, kFmtRegR, 20, 16, kFmtShift, -1, -1, 619 kFmtUnused, -1, -1, IS_QUAD_OP | REG_USE01 | SETS_CCODES, 620 "tst", "!0r, !1r!2o", kFixupNone), 621 ENCODING_MAP(WIDE(kA64Ubfm4rrdd), SF_N_VARIANTS(0x53000000), 622 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtBitBlt, 21, 16, 623 kFmtBitBlt, 15, 10, IS_QUAD_OP | REG_DEF0_USE1, 624 "ubfm", "!0r, !1r, !2d, !3d", kFixupNone), 625 }; 626 627 // new_lir replaces orig_lir in the pcrel_fixup list. 628 void Arm64Mir2Lir::ReplaceFixup(LIR* prev_lir, LIR* orig_lir, LIR* new_lir) { 629 new_lir->u.a.pcrel_next = orig_lir->u.a.pcrel_next; 630 if (UNLIKELY(prev_lir == NULL)) { 631 first_fixup_ = new_lir; 632 } else { 633 prev_lir->u.a.pcrel_next = new_lir; 634 } 635 orig_lir->flags.fixup = kFixupNone; 636 } 637 638 // new_lir is inserted before orig_lir in the pcrel_fixup list. 639 void Arm64Mir2Lir::InsertFixupBefore(LIR* prev_lir, LIR* orig_lir, LIR* new_lir) { 640 new_lir->u.a.pcrel_next = orig_lir; 641 if (UNLIKELY(prev_lir == NULL)) { 642 first_fixup_ = new_lir; 643 } else { 644 DCHECK(prev_lir->u.a.pcrel_next == orig_lir); 645 prev_lir->u.a.pcrel_next = new_lir; 646 } 647 } 648 649 /* Nop, used for aligning code. Nop is an alias for hint #0. */ 650 #define PADDING_NOP (UINT32_C(0xd503201f)) 651 652 uint8_t* Arm64Mir2Lir::EncodeLIRs(uint8_t* write_pos, LIR* lir) { 653 for (; lir != nullptr; lir = NEXT_LIR(lir)) { 654 bool opcode_is_wide = IS_WIDE(lir->opcode); 655 ArmOpcode opcode = UNWIDE(lir->opcode); 656 657 if (UNLIKELY(IsPseudoLirOp(opcode))) { 658 continue; 659 } 660 661 if (LIKELY(!lir->flags.is_nop)) { 662 const ArmEncodingMap *encoder = &EncodingMap[opcode]; 663 664 // Select the right variant of the skeleton. 665 uint32_t bits = opcode_is_wide ? encoder->xskeleton : encoder->wskeleton; 666 DCHECK(!opcode_is_wide || IS_WIDE(encoder->opcode)); 667 668 for (int i = 0; i < 4; i++) { 669 ArmEncodingKind kind = encoder->field_loc[i].kind; 670 uint32_t operand = lir->operands[i]; 671 uint32_t value; 672 673 if (LIKELY(static_cast<unsigned>(kind) <= kFmtBitBlt)) { 674 // Note: this will handle kFmtReg* and kFmtBitBlt. 675 676 if (static_cast<unsigned>(kind) < kFmtBitBlt) { 677 bool is_zero = A64_REG_IS_ZR(operand); 678 679 if (kIsDebugBuild && (kFailOnSizeError || kReportSizeError)) { 680 // Register usage checks: First establish register usage requirements based on the 681 // format in `kind'. 682 bool want_float = false; // Want a float (rather than core) register. 683 bool want_64_bit = false; // Want a 64-bit (rather than 32-bit) register. 684 bool want_var_size = true; // Want register with variable size (kFmtReg{R,F}). 685 bool want_zero = false; // Want the zero (rather than sp) register. 686 switch (kind) { 687 case kFmtRegX: 688 want_64_bit = true; 689 // Intentional fall-through. 690 case kFmtRegW: 691 want_var_size = false; 692 // Intentional fall-through. 693 case kFmtRegR: 694 want_zero = true; 695 break; 696 case kFmtRegXOrSp: 697 want_64_bit = true; 698 // Intentional fall-through. 699 case kFmtRegWOrSp: 700 want_var_size = false; 701 break; 702 case kFmtRegROrSp: 703 break; 704 case kFmtRegD: 705 want_64_bit = true; 706 // Intentional fall-through. 707 case kFmtRegS: 708 want_var_size = false; 709 // Intentional fall-through. 710 case kFmtRegF: 711 want_float = true; 712 break; 713 default: 714 LOG(FATAL) << "Bad fmt for arg n. " << i << " of " << encoder->name 715 << " (" << kind << ")"; 716 break; 717 } 718 719 // want_var_size == true means kind == kFmtReg{R,F}. In these two cases, we want 720 // the register size to be coherent with the instruction width. 721 if (want_var_size) { 722 want_64_bit = opcode_is_wide; 723 } 724 725 // Now check that the requirements are satisfied. 726 RegStorage reg(operand | RegStorage::kValid); 727 const char *expected = nullptr; 728 if (want_float) { 729 if (!reg.IsFloat()) { 730 expected = "float register"; 731 } else if (reg.IsDouble() != want_64_bit) { 732 expected = (want_64_bit) ? "double register" : "single register"; 733 } 734 } else { 735 if (reg.IsFloat()) { 736 expected = "core register"; 737 } else if (reg.Is64Bit() != want_64_bit) { 738 expected = (want_64_bit) ? "x-register" : "w-register"; 739 } else if (A64_REGSTORAGE_IS_SP_OR_ZR(reg) && is_zero != want_zero) { 740 expected = (want_zero) ? "zero-register" : "sp-register"; 741 } 742 } 743 744 // Fail, if `expected' contains an unsatisfied requirement. 745 if (expected != nullptr) { 746 LOG(WARNING) << "Method: " << PrettyMethod(cu_->method_idx, *cu_->dex_file) 747 << " @ 0x" << std::hex << lir->dalvik_offset; 748 if (kFailOnSizeError) { 749 LOG(FATAL) << "Bad argument n. " << i << " of " << encoder->name 750 << "(" << UNWIDE(encoder->opcode) << ", " << encoder->fmt << ")" 751 << ". Expected " << expected << ", got 0x" << std::hex << operand; 752 } else { 753 LOG(WARNING) << "Bad argument n. " << i << " of " << encoder->name 754 << ". Expected " << expected << ", got 0x" << std::hex << operand; 755 } 756 } 757 } 758 759 // In the lines below, we rely on (operand & 0x1f) == 31 to be true for register sp 760 // and zr. This means that these two registers do not need any special treatment, as 761 // their bottom 5 bits are correctly set to 31 == 0b11111, which is the right 762 // value for encoding both sp and zr. 763 COMPILE_ASSERT((rxzr & 0x1f) == 0x1f, rzr_register_number_must_be_31); 764 COMPILE_ASSERT((rsp & 0x1f) == 0x1f, rsp_register_number_must_be_31); 765 } 766 767 value = (operand << encoder->field_loc[i].start) & 768 ((1 << (encoder->field_loc[i].end + 1)) - 1); 769 bits |= value; 770 } else { 771 switch (kind) { 772 case kFmtSkip: 773 break; // Nothing to do, but continue to next. 774 case kFmtUnused: 775 i = 4; // Done, break out of the enclosing loop. 776 break; 777 case kFmtShift: 778 // Intentional fallthrough. 779 case kFmtExtend: 780 DCHECK_EQ((operand & (1 << 6)) == 0, kind == kFmtShift); 781 value = (operand & 0x3f) << 10; 782 value |= ((operand & 0x1c0) >> 6) << 21; 783 bits |= value; 784 break; 785 case kFmtImm21: 786 value = (operand & 0x3) << 29; 787 value |= ((operand & 0x1ffffc) >> 2) << 5; 788 bits |= value; 789 break; 790 default: 791 LOG(FATAL) << "Bad fmt for arg. " << i << " in " << encoder->name 792 << " (" << kind << ")"; 793 } 794 } 795 } 796 797 DCHECK_EQ(encoder->size, 4); 798 write_pos[0] = (bits & 0xff); 799 write_pos[1] = ((bits >> 8) & 0xff); 800 write_pos[2] = ((bits >> 16) & 0xff); 801 write_pos[3] = ((bits >> 24) & 0xff); 802 write_pos += 4; 803 } 804 } 805 806 return write_pos; 807 } 808 809 // Align data offset on 8 byte boundary: it will only contain double-word items, as word immediates 810 // are better set directly from the code (they will require no more than 2 instructions). 811 #define ALIGNED_DATA_OFFSET(offset) (((offset) + 0x7) & ~0x7) 812 813 // Assemble the LIR into binary instruction format. 814 void Arm64Mir2Lir::AssembleLIR() { 815 LIR* lir; 816 LIR* prev_lir; 817 cu_->NewTimingSplit("Assemble"); 818 int assembler_retries = 0; 819 CodeOffset starting_offset = LinkFixupInsns(first_lir_insn_, last_lir_insn_, 0); 820 data_offset_ = ALIGNED_DATA_OFFSET(starting_offset); 821 int32_t offset_adjustment; 822 AssignDataOffsets(); 823 824 /* 825 * Note: generation must be 1 on first pass (to distinguish from initialized state of 0 826 * for non-visited nodes). Start at zero here, and bit will be flipped to 1 on entry to the loop. 827 */ 828 int generation = 0; 829 while (true) { 830 // TODO(Arm64): check whether passes and offset adjustments are really necessary. 831 // Currently they aren't, as - in the fixups below - LIR are never inserted. 832 // Things can be different if jump ranges above 1 MB need to be supported. 833 // If they are not, then we can get rid of the assembler retry logic. 834 835 offset_adjustment = 0; 836 AssemblerStatus res = kSuccess; // Assume success 837 generation ^= 1; 838 // Note: nodes requiring possible fixup linked in ascending order. 839 lir = first_fixup_; 840 prev_lir = NULL; 841 while (lir != NULL) { 842 /* 843 * NOTE: the lir being considered here will be encoded following the switch (so long as 844 * we're not in a retry situation). However, any new non-pc_rel instructions inserted 845 * due to retry must be explicitly encoded at the time of insertion. Note that 846 * inserted instructions don't need use/def flags, but do need size and pc-rel status 847 * properly updated. 848 */ 849 lir->offset += offset_adjustment; 850 // During pass, allows us to tell whether a node has been updated with offset_adjustment yet. 851 lir->flags.generation = generation; 852 switch (static_cast<FixupKind>(lir->flags.fixup)) { 853 case kFixupLabel: 854 case kFixupNone: 855 case kFixupVLoad: 856 break; 857 case kFixupT1Branch: { 858 LIR *target_lir = lir->target; 859 DCHECK(target_lir); 860 CodeOffset pc = lir->offset; 861 CodeOffset target = target_lir->offset + 862 ((target_lir->flags.generation == lir->flags.generation) ? 0 : offset_adjustment); 863 int32_t delta = target - pc; 864 if (!((delta & 0x3) == 0 && IS_SIGNED_IMM19(delta >> 2))) { 865 LOG(FATAL) << "Invalid jump range in kFixupT1Branch"; 866 } 867 lir->operands[0] = delta >> 2; 868 break; 869 } 870 case kFixupLoad: 871 case kFixupCBxZ: 872 case kFixupCondBranch: { 873 LIR *target_lir = lir->target; 874 DCHECK(target_lir); 875 CodeOffset pc = lir->offset; 876 CodeOffset target = target_lir->offset + 877 ((target_lir->flags.generation == lir->flags.generation) ? 0 : offset_adjustment); 878 int32_t delta = target - pc; 879 if (!((delta & 0x3) == 0 && IS_SIGNED_IMM19(delta >> 2))) { 880 LOG(FATAL) << "Invalid jump range in kFixupLoad"; 881 } 882 lir->operands[1] = delta >> 2; 883 break; 884 } 885 case kFixupAdr: { 886 LIR* target_lir = lir->target; 887 int32_t delta; 888 if (target_lir) { 889 CodeOffset target_offs = ((target_lir->flags.generation == lir->flags.generation) ? 890 0 : offset_adjustment) + target_lir->offset; 891 delta = target_offs - lir->offset; 892 } else if (lir->operands[2] >= 0) { 893 EmbeddedData* tab = reinterpret_cast<EmbeddedData*>(UnwrapPointer(lir->operands[2])); 894 delta = tab->offset + offset_adjustment - lir->offset; 895 } else { 896 // No fixup: this usage allows to retrieve the current PC. 897 delta = lir->operands[1]; 898 } 899 if (!IS_SIGNED_IMM21(delta)) { 900 LOG(FATAL) << "Jump range above 1MB in kFixupAdr"; 901 } 902 lir->operands[1] = delta; 903 break; 904 } 905 default: 906 LOG(FATAL) << "Unexpected case " << lir->flags.fixup; 907 } 908 prev_lir = lir; 909 lir = lir->u.a.pcrel_next; 910 } 911 912 if (res == kSuccess) { 913 break; 914 } else { 915 assembler_retries++; 916 if (assembler_retries > MAX_ASSEMBLER_RETRIES) { 917 CodegenDump(); 918 LOG(FATAL) << "Assembler error - too many retries"; 919 } 920 starting_offset += offset_adjustment; 921 data_offset_ = ALIGNED_DATA_OFFSET(starting_offset); 922 AssignDataOffsets(); 923 } 924 } 925 926 // Build the CodeBuffer. 927 DCHECK_LE(data_offset_, total_size_); 928 code_buffer_.reserve(total_size_); 929 code_buffer_.resize(starting_offset); 930 uint8_t* write_pos = &code_buffer_[0]; 931 write_pos = EncodeLIRs(write_pos, first_lir_insn_); 932 DCHECK_EQ(static_cast<CodeOffset>(write_pos - &code_buffer_[0]), starting_offset); 933 934 DCHECK_EQ(data_offset_, ALIGNED_DATA_OFFSET(code_buffer_.size())); 935 936 // Install literals 937 InstallLiteralPools(); 938 939 // Install switch tables 940 InstallSwitchTables(); 941 942 // Install fill array data 943 InstallFillArrayData(); 944 945 // Create the mapping table and native offset to reference map. 946 cu_->NewTimingSplit("PcMappingTable"); 947 CreateMappingTables(); 948 949 cu_->NewTimingSplit("GcMap"); 950 CreateNativeGcMap(); 951 } 952 953 size_t Arm64Mir2Lir::GetInsnSize(LIR* lir) { 954 ArmOpcode opcode = UNWIDE(lir->opcode); 955 DCHECK(!IsPseudoLirOp(opcode)); 956 return EncodingMap[opcode].size; 957 } 958 959 // Encode instruction bit pattern and assign offsets. 960 uint32_t Arm64Mir2Lir::LinkFixupInsns(LIR* head_lir, LIR* tail_lir, uint32_t offset) { 961 LIR* end_lir = tail_lir->next; 962 963 LIR* last_fixup = NULL; 964 for (LIR* lir = head_lir; lir != end_lir; lir = NEXT_LIR(lir)) { 965 ArmOpcode opcode = UNWIDE(lir->opcode); 966 if (!lir->flags.is_nop) { 967 if (lir->flags.fixup != kFixupNone) { 968 if (!IsPseudoLirOp(opcode)) { 969 lir->flags.size = EncodingMap[opcode].size; 970 lir->flags.fixup = EncodingMap[opcode].fixup; 971 } else { 972 DCHECK_NE(static_cast<int>(opcode), kPseudoPseudoAlign4); 973 lir->flags.size = 0; 974 lir->flags.fixup = kFixupLabel; 975 } 976 // Link into the fixup chain. 977 lir->flags.use_def_invalid = true; 978 lir->u.a.pcrel_next = NULL; 979 if (first_fixup_ == NULL) { 980 first_fixup_ = lir; 981 } else { 982 last_fixup->u.a.pcrel_next = lir; 983 } 984 last_fixup = lir; 985 lir->offset = offset; 986 } 987 offset += lir->flags.size; 988 } 989 } 990 return offset; 991 } 992 993 void Arm64Mir2Lir::AssignDataOffsets() { 994 /* Set up offsets for literals */ 995 CodeOffset offset = data_offset_; 996 997 offset = AssignLiteralOffset(offset); 998 999 offset = AssignSwitchTablesOffset(offset); 1000 1001 total_size_ = AssignFillArrayDataOffset(offset); 1002 } 1003 1004 } // namespace art 1005
