1 //=- AArch64RegisterInfo.td - Describe the AArch64 Regisers --*- tablegen -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // 11 //===----------------------------------------------------------------------===// 12 13 14 class AArch64Reg<bits<16> enc, string n, list<Register> subregs = [], 15 list<string> altNames = []> 16 : Register<n, altNames> { 17 let HWEncoding = enc; 18 let Namespace = "AArch64"; 19 let SubRegs = subregs; 20 } 21 22 let Namespace = "AArch64" in { 23 def sub_32 : SubRegIndex<32>; 24 25 def bsub : SubRegIndex<8>; 26 def hsub : SubRegIndex<16>; 27 def ssub : SubRegIndex<32>; 28 def dsub : SubRegIndex<32>; 29 def qhisub : SubRegIndex<64>; 30 def qsub : SubRegIndex<64>; 31 // Note: Code depends on these having consecutive numbers 32 def dsub0 : SubRegIndex<64>; 33 def dsub1 : SubRegIndex<64>; 34 def dsub2 : SubRegIndex<64>; 35 def dsub3 : SubRegIndex<64>; 36 // Note: Code depends on these having consecutive numbers 37 def qsub0 : SubRegIndex<128>; 38 def qsub1 : SubRegIndex<128>; 39 def qsub2 : SubRegIndex<128>; 40 def qsub3 : SubRegIndex<128>; 41 } 42 43 let Namespace = "AArch64" in { 44 def vreg : RegAltNameIndex; 45 def vlist1 : RegAltNameIndex; 46 } 47 48 //===----------------------------------------------------------------------===// 49 // Registers 50 //===----------------------------------------------------------------------===// 51 def W0 : AArch64Reg<0, "w0" >, DwarfRegNum<[0]>; 52 def W1 : AArch64Reg<1, "w1" >, DwarfRegNum<[1]>; 53 def W2 : AArch64Reg<2, "w2" >, DwarfRegNum<[2]>; 54 def W3 : AArch64Reg<3, "w3" >, DwarfRegNum<[3]>; 55 def W4 : AArch64Reg<4, "w4" >, DwarfRegNum<[4]>; 56 def W5 : AArch64Reg<5, "w5" >, DwarfRegNum<[5]>; 57 def W6 : AArch64Reg<6, "w6" >, DwarfRegNum<[6]>; 58 def W7 : AArch64Reg<7, "w7" >, DwarfRegNum<[7]>; 59 def W8 : AArch64Reg<8, "w8" >, DwarfRegNum<[8]>; 60 def W9 : AArch64Reg<9, "w9" >, DwarfRegNum<[9]>; 61 def W10 : AArch64Reg<10, "w10">, DwarfRegNum<[10]>; 62 def W11 : AArch64Reg<11, "w11">, DwarfRegNum<[11]>; 63 def W12 : AArch64Reg<12, "w12">, DwarfRegNum<[12]>; 64 def W13 : AArch64Reg<13, "w13">, DwarfRegNum<[13]>; 65 def W14 : AArch64Reg<14, "w14">, DwarfRegNum<[14]>; 66 def W15 : AArch64Reg<15, "w15">, DwarfRegNum<[15]>; 67 def W16 : AArch64Reg<16, "w16">, DwarfRegNum<[16]>; 68 def W17 : AArch64Reg<17, "w17">, DwarfRegNum<[17]>; 69 def W18 : AArch64Reg<18, "w18">, DwarfRegNum<[18]>; 70 def W19 : AArch64Reg<19, "w19">, DwarfRegNum<[19]>; 71 def W20 : AArch64Reg<20, "w20">, DwarfRegNum<[20]>; 72 def W21 : AArch64Reg<21, "w21">, DwarfRegNum<[21]>; 73 def W22 : AArch64Reg<22, "w22">, DwarfRegNum<[22]>; 74 def W23 : AArch64Reg<23, "w23">, DwarfRegNum<[23]>; 75 def W24 : AArch64Reg<24, "w24">, DwarfRegNum<[24]>; 76 def W25 : AArch64Reg<25, "w25">, DwarfRegNum<[25]>; 77 def W26 : AArch64Reg<26, "w26">, DwarfRegNum<[26]>; 78 def W27 : AArch64Reg<27, "w27">, DwarfRegNum<[27]>; 79 def W28 : AArch64Reg<28, "w28">, DwarfRegNum<[28]>; 80 def W29 : AArch64Reg<29, "w29">, DwarfRegNum<[29]>; 81 def W30 : AArch64Reg<30, "w30">, DwarfRegNum<[30]>; 82 def WSP : AArch64Reg<31, "wsp">, DwarfRegNum<[31]>; 83 def WZR : AArch64Reg<31, "wzr">, DwarfRegAlias<WSP>; 84 85 let SubRegIndices = [sub_32] in { 86 def X0 : AArch64Reg<0, "x0", [W0]>, DwarfRegAlias<W0>; 87 def X1 : AArch64Reg<1, "x1", [W1]>, DwarfRegAlias<W1>; 88 def X2 : AArch64Reg<2, "x2", [W2]>, DwarfRegAlias<W2>; 89 def X3 : AArch64Reg<3, "x3", [W3]>, DwarfRegAlias<W3>; 90 def X4 : AArch64Reg<4, "x4", [W4]>, DwarfRegAlias<W4>; 91 def X5 : AArch64Reg<5, "x5", [W5]>, DwarfRegAlias<W5>; 92 def X6 : AArch64Reg<6, "x6", [W6]>, DwarfRegAlias<W6>; 93 def X7 : AArch64Reg<7, "x7", [W7]>, DwarfRegAlias<W7>; 94 def X8 : AArch64Reg<8, "x8", [W8]>, DwarfRegAlias<W8>; 95 def X9 : AArch64Reg<9, "x9", [W9]>, DwarfRegAlias<W9>; 96 def X10 : AArch64Reg<10, "x10", [W10]>, DwarfRegAlias<W10>; 97 def X11 : AArch64Reg<11, "x11", [W11]>, DwarfRegAlias<W11>; 98 def X12 : AArch64Reg<12, "x12", [W12]>, DwarfRegAlias<W12>; 99 def X13 : AArch64Reg<13, "x13", [W13]>, DwarfRegAlias<W13>; 100 def X14 : AArch64Reg<14, "x14", [W14]>, DwarfRegAlias<W14>; 101 def X15 : AArch64Reg<15, "x15", [W15]>, DwarfRegAlias<W15>; 102 def X16 : AArch64Reg<16, "x16", [W16]>, DwarfRegAlias<W16>; 103 def X17 : AArch64Reg<17, "x17", [W17]>, DwarfRegAlias<W17>; 104 def X18 : AArch64Reg<18, "x18", [W18]>, DwarfRegAlias<W18>; 105 def X19 : AArch64Reg<19, "x19", [W19]>, DwarfRegAlias<W19>; 106 def X20 : AArch64Reg<20, "x20", [W20]>, DwarfRegAlias<W20>; 107 def X21 : AArch64Reg<21, "x21", [W21]>, DwarfRegAlias<W21>; 108 def X22 : AArch64Reg<22, "x22", [W22]>, DwarfRegAlias<W22>; 109 def X23 : AArch64Reg<23, "x23", [W23]>, DwarfRegAlias<W23>; 110 def X24 : AArch64Reg<24, "x24", [W24]>, DwarfRegAlias<W24>; 111 def X25 : AArch64Reg<25, "x25", [W25]>, DwarfRegAlias<W25>; 112 def X26 : AArch64Reg<26, "x26", [W26]>, DwarfRegAlias<W26>; 113 def X27 : AArch64Reg<27, "x27", [W27]>, DwarfRegAlias<W27>; 114 def X28 : AArch64Reg<28, "x28", [W28]>, DwarfRegAlias<W28>; 115 def FP : AArch64Reg<29, "x29", [W29]>, DwarfRegAlias<W29>; 116 def LR : AArch64Reg<30, "x30", [W30]>, DwarfRegAlias<W30>; 117 def SP : AArch64Reg<31, "sp", [WSP]>, DwarfRegAlias<WSP>; 118 def XZR : AArch64Reg<31, "xzr", [WZR]>, DwarfRegAlias<WSP>; 119 } 120 121 // Condition code register. 122 def NZCV : AArch64Reg<0, "nzcv">; 123 124 // GPR register classes with the intersections of GPR32/GPR32sp and 125 // GPR64/GPR64sp for use by the coalescer. 126 def GPR32common : RegisterClass<"AArch64", [i32], 32, (sequence "W%u", 0, 30)> { 127 let AltOrders = [(rotl GPR32common, 8)]; 128 let AltOrderSelect = [{ return 1; }]; 129 } 130 def GPR64common : RegisterClass<"AArch64", [i64], 64, 131 (add (sequence "X%u", 0, 28), FP, LR)> { 132 let AltOrders = [(rotl GPR64common, 8)]; 133 let AltOrderSelect = [{ return 1; }]; 134 } 135 // GPR register classes which exclude SP/WSP. 136 def GPR32 : RegisterClass<"AArch64", [i32], 32, (add GPR32common, WZR)> { 137 let AltOrders = [(rotl GPR32, 8)]; 138 let AltOrderSelect = [{ return 1; }]; 139 } 140 def GPR64 : RegisterClass<"AArch64", [i64], 64, (add GPR64common, XZR)> { 141 let AltOrders = [(rotl GPR64, 8)]; 142 let AltOrderSelect = [{ return 1; }]; 143 } 144 145 // GPR register classes which include SP/WSP. 146 def GPR32sp : RegisterClass<"AArch64", [i32], 32, (add GPR32common, WSP)> { 147 let AltOrders = [(rotl GPR32sp, 8)]; 148 let AltOrderSelect = [{ return 1; }]; 149 } 150 def GPR64sp : RegisterClass<"AArch64", [i64], 64, (add GPR64common, SP)> { 151 let AltOrders = [(rotl GPR64sp, 8)]; 152 let AltOrderSelect = [{ return 1; }]; 153 } 154 155 def GPR32sponly : RegisterClass<"AArch64", [i32], 32, (add WSP)>; 156 def GPR64sponly : RegisterClass<"AArch64", [i64], 64, (add SP)>; 157 158 def GPR64spPlus0Operand : AsmOperandClass { 159 let Name = "GPR64sp0"; 160 let RenderMethod = "addRegOperands"; 161 let ParserMethod = "tryParseGPR64sp0Operand"; 162 } 163 164 def GPR64sp0 : RegisterOperand<GPR64sp> { 165 let ParserMatchClass = GPR64spPlus0Operand; 166 } 167 168 // GPR register classes which include WZR/XZR AND SP/WSP. This is not a 169 // constraint used by any instructions, it is used as a common super-class. 170 def GPR32all : RegisterClass<"AArch64", [i32], 32, (add GPR32common, WZR, WSP)>; 171 def GPR64all : RegisterClass<"AArch64", [i64], 64, (add GPR64common, XZR, SP)>; 172 173 // For tail calls, we can't use callee-saved registers, as they are restored 174 // to the saved value before the tail call, which would clobber a call address. 175 // This is for indirect tail calls to store the address of the destination. 176 def tcGPR64 : RegisterClass<"AArch64", [i64], 64, (sub GPR64common, X19, X20, X21, 177 X22, X23, X24, X25, X26, 178 X27, X28, FP, LR)>; 179 180 // GPR register classes for post increment amount of vector load/store that 181 // has alternate printing when Rm=31 and prints a constant immediate value 182 // equal to the total number of bytes transferred. 183 184 // FIXME: TableGen *should* be able to do these itself now. There appears to be 185 // a bug in counting how many operands a Post-indexed MCInst should have which 186 // means the aliases don't trigger. 187 def GPR64pi1 : RegisterOperand<GPR64, "printPostIncOperand<1>">; 188 def GPR64pi2 : RegisterOperand<GPR64, "printPostIncOperand<2>">; 189 def GPR64pi3 : RegisterOperand<GPR64, "printPostIncOperand<3>">; 190 def GPR64pi4 : RegisterOperand<GPR64, "printPostIncOperand<4>">; 191 def GPR64pi6 : RegisterOperand<GPR64, "printPostIncOperand<6>">; 192 def GPR64pi8 : RegisterOperand<GPR64, "printPostIncOperand<8>">; 193 def GPR64pi12 : RegisterOperand<GPR64, "printPostIncOperand<12>">; 194 def GPR64pi16 : RegisterOperand<GPR64, "printPostIncOperand<16>">; 195 def GPR64pi24 : RegisterOperand<GPR64, "printPostIncOperand<24>">; 196 def GPR64pi32 : RegisterOperand<GPR64, "printPostIncOperand<32>">; 197 def GPR64pi48 : RegisterOperand<GPR64, "printPostIncOperand<48>">; 198 def GPR64pi64 : RegisterOperand<GPR64, "printPostIncOperand<64>">; 199 200 // Condition code regclass. 201 def CCR : RegisterClass<"AArch64", [i32], 32, (add NZCV)> { 202 let CopyCost = -1; // Don't allow copying of status registers. 203 204 // CCR is not allocatable. 205 let isAllocatable = 0; 206 } 207 208 //===----------------------------------------------------------------------===// 209 // Floating Point Scalar Registers 210 //===----------------------------------------------------------------------===// 211 212 def B0 : AArch64Reg<0, "b0">, DwarfRegNum<[64]>; 213 def B1 : AArch64Reg<1, "b1">, DwarfRegNum<[65]>; 214 def B2 : AArch64Reg<2, "b2">, DwarfRegNum<[66]>; 215 def B3 : AArch64Reg<3, "b3">, DwarfRegNum<[67]>; 216 def B4 : AArch64Reg<4, "b4">, DwarfRegNum<[68]>; 217 def B5 : AArch64Reg<5, "b5">, DwarfRegNum<[69]>; 218 def B6 : AArch64Reg<6, "b6">, DwarfRegNum<[70]>; 219 def B7 : AArch64Reg<7, "b7">, DwarfRegNum<[71]>; 220 def B8 : AArch64Reg<8, "b8">, DwarfRegNum<[72]>; 221 def B9 : AArch64Reg<9, "b9">, DwarfRegNum<[73]>; 222 def B10 : AArch64Reg<10, "b10">, DwarfRegNum<[74]>; 223 def B11 : AArch64Reg<11, "b11">, DwarfRegNum<[75]>; 224 def B12 : AArch64Reg<12, "b12">, DwarfRegNum<[76]>; 225 def B13 : AArch64Reg<13, "b13">, DwarfRegNum<[77]>; 226 def B14 : AArch64Reg<14, "b14">, DwarfRegNum<[78]>; 227 def B15 : AArch64Reg<15, "b15">, DwarfRegNum<[79]>; 228 def B16 : AArch64Reg<16, "b16">, DwarfRegNum<[80]>; 229 def B17 : AArch64Reg<17, "b17">, DwarfRegNum<[81]>; 230 def B18 : AArch64Reg<18, "b18">, DwarfRegNum<[82]>; 231 def B19 : AArch64Reg<19, "b19">, DwarfRegNum<[83]>; 232 def B20 : AArch64Reg<20, "b20">, DwarfRegNum<[84]>; 233 def B21 : AArch64Reg<21, "b21">, DwarfRegNum<[85]>; 234 def B22 : AArch64Reg<22, "b22">, DwarfRegNum<[86]>; 235 def B23 : AArch64Reg<23, "b23">, DwarfRegNum<[87]>; 236 def B24 : AArch64Reg<24, "b24">, DwarfRegNum<[88]>; 237 def B25 : AArch64Reg<25, "b25">, DwarfRegNum<[89]>; 238 def B26 : AArch64Reg<26, "b26">, DwarfRegNum<[90]>; 239 def B27 : AArch64Reg<27, "b27">, DwarfRegNum<[91]>; 240 def B28 : AArch64Reg<28, "b28">, DwarfRegNum<[92]>; 241 def B29 : AArch64Reg<29, "b29">, DwarfRegNum<[93]>; 242 def B30 : AArch64Reg<30, "b30">, DwarfRegNum<[94]>; 243 def B31 : AArch64Reg<31, "b31">, DwarfRegNum<[95]>; 244 245 let SubRegIndices = [bsub] in { 246 def H0 : AArch64Reg<0, "h0", [B0]>, DwarfRegAlias<B0>; 247 def H1 : AArch64Reg<1, "h1", [B1]>, DwarfRegAlias<B1>; 248 def H2 : AArch64Reg<2, "h2", [B2]>, DwarfRegAlias<B2>; 249 def H3 : AArch64Reg<3, "h3", [B3]>, DwarfRegAlias<B3>; 250 def H4 : AArch64Reg<4, "h4", [B4]>, DwarfRegAlias<B4>; 251 def H5 : AArch64Reg<5, "h5", [B5]>, DwarfRegAlias<B5>; 252 def H6 : AArch64Reg<6, "h6", [B6]>, DwarfRegAlias<B6>; 253 def H7 : AArch64Reg<7, "h7", [B7]>, DwarfRegAlias<B7>; 254 def H8 : AArch64Reg<8, "h8", [B8]>, DwarfRegAlias<B8>; 255 def H9 : AArch64Reg<9, "h9", [B9]>, DwarfRegAlias<B9>; 256 def H10 : AArch64Reg<10, "h10", [B10]>, DwarfRegAlias<B10>; 257 def H11 : AArch64Reg<11, "h11", [B11]>, DwarfRegAlias<B11>; 258 def H12 : AArch64Reg<12, "h12", [B12]>, DwarfRegAlias<B12>; 259 def H13 : AArch64Reg<13, "h13", [B13]>, DwarfRegAlias<B13>; 260 def H14 : AArch64Reg<14, "h14", [B14]>, DwarfRegAlias<B14>; 261 def H15 : AArch64Reg<15, "h15", [B15]>, DwarfRegAlias<B15>; 262 def H16 : AArch64Reg<16, "h16", [B16]>, DwarfRegAlias<B16>; 263 def H17 : AArch64Reg<17, "h17", [B17]>, DwarfRegAlias<B17>; 264 def H18 : AArch64Reg<18, "h18", [B18]>, DwarfRegAlias<B18>; 265 def H19 : AArch64Reg<19, "h19", [B19]>, DwarfRegAlias<B19>; 266 def H20 : AArch64Reg<20, "h20", [B20]>, DwarfRegAlias<B20>; 267 def H21 : AArch64Reg<21, "h21", [B21]>, DwarfRegAlias<B21>; 268 def H22 : AArch64Reg<22, "h22", [B22]>, DwarfRegAlias<B22>; 269 def H23 : AArch64Reg<23, "h23", [B23]>, DwarfRegAlias<B23>; 270 def H24 : AArch64Reg<24, "h24", [B24]>, DwarfRegAlias<B24>; 271 def H25 : AArch64Reg<25, "h25", [B25]>, DwarfRegAlias<B25>; 272 def H26 : AArch64Reg<26, "h26", [B26]>, DwarfRegAlias<B26>; 273 def H27 : AArch64Reg<27, "h27", [B27]>, DwarfRegAlias<B27>; 274 def H28 : AArch64Reg<28, "h28", [B28]>, DwarfRegAlias<B28>; 275 def H29 : AArch64Reg<29, "h29", [B29]>, DwarfRegAlias<B29>; 276 def H30 : AArch64Reg<30, "h30", [B30]>, DwarfRegAlias<B30>; 277 def H31 : AArch64Reg<31, "h31", [B31]>, DwarfRegAlias<B31>; 278 } 279 280 let SubRegIndices = [hsub] in { 281 def S0 : AArch64Reg<0, "s0", [H0]>, DwarfRegAlias<B0>; 282 def S1 : AArch64Reg<1, "s1", [H1]>, DwarfRegAlias<B1>; 283 def S2 : AArch64Reg<2, "s2", [H2]>, DwarfRegAlias<B2>; 284 def S3 : AArch64Reg<3, "s3", [H3]>, DwarfRegAlias<B3>; 285 def S4 : AArch64Reg<4, "s4", [H4]>, DwarfRegAlias<B4>; 286 def S5 : AArch64Reg<5, "s5", [H5]>, DwarfRegAlias<B5>; 287 def S6 : AArch64Reg<6, "s6", [H6]>, DwarfRegAlias<B6>; 288 def S7 : AArch64Reg<7, "s7", [H7]>, DwarfRegAlias<B7>; 289 def S8 : AArch64Reg<8, "s8", [H8]>, DwarfRegAlias<B8>; 290 def S9 : AArch64Reg<9, "s9", [H9]>, DwarfRegAlias<B9>; 291 def S10 : AArch64Reg<10, "s10", [H10]>, DwarfRegAlias<B10>; 292 def S11 : AArch64Reg<11, "s11", [H11]>, DwarfRegAlias<B11>; 293 def S12 : AArch64Reg<12, "s12", [H12]>, DwarfRegAlias<B12>; 294 def S13 : AArch64Reg<13, "s13", [H13]>, DwarfRegAlias<B13>; 295 def S14 : AArch64Reg<14, "s14", [H14]>, DwarfRegAlias<B14>; 296 def S15 : AArch64Reg<15, "s15", [H15]>, DwarfRegAlias<B15>; 297 def S16 : AArch64Reg<16, "s16", [H16]>, DwarfRegAlias<B16>; 298 def S17 : AArch64Reg<17, "s17", [H17]>, DwarfRegAlias<B17>; 299 def S18 : AArch64Reg<18, "s18", [H18]>, DwarfRegAlias<B18>; 300 def S19 : AArch64Reg<19, "s19", [H19]>, DwarfRegAlias<B19>; 301 def S20 : AArch64Reg<20, "s20", [H20]>, DwarfRegAlias<B20>; 302 def S21 : AArch64Reg<21, "s21", [H21]>, DwarfRegAlias<B21>; 303 def S22 : AArch64Reg<22, "s22", [H22]>, DwarfRegAlias<B22>; 304 def S23 : AArch64Reg<23, "s23", [H23]>, DwarfRegAlias<B23>; 305 def S24 : AArch64Reg<24, "s24", [H24]>, DwarfRegAlias<B24>; 306 def S25 : AArch64Reg<25, "s25", [H25]>, DwarfRegAlias<B25>; 307 def S26 : AArch64Reg<26, "s26", [H26]>, DwarfRegAlias<B26>; 308 def S27 : AArch64Reg<27, "s27", [H27]>, DwarfRegAlias<B27>; 309 def S28 : AArch64Reg<28, "s28", [H28]>, DwarfRegAlias<B28>; 310 def S29 : AArch64Reg<29, "s29", [H29]>, DwarfRegAlias<B29>; 311 def S30 : AArch64Reg<30, "s30", [H30]>, DwarfRegAlias<B30>; 312 def S31 : AArch64Reg<31, "s31", [H31]>, DwarfRegAlias<B31>; 313 } 314 315 let SubRegIndices = [ssub], RegAltNameIndices = [vreg, vlist1] in { 316 def D0 : AArch64Reg<0, "d0", [S0], ["v0", ""]>, DwarfRegAlias<B0>; 317 def D1 : AArch64Reg<1, "d1", [S1], ["v1", ""]>, DwarfRegAlias<B1>; 318 def D2 : AArch64Reg<2, "d2", [S2], ["v2", ""]>, DwarfRegAlias<B2>; 319 def D3 : AArch64Reg<3, "d3", [S3], ["v3", ""]>, DwarfRegAlias<B3>; 320 def D4 : AArch64Reg<4, "d4", [S4], ["v4", ""]>, DwarfRegAlias<B4>; 321 def D5 : AArch64Reg<5, "d5", [S5], ["v5", ""]>, DwarfRegAlias<B5>; 322 def D6 : AArch64Reg<6, "d6", [S6], ["v6", ""]>, DwarfRegAlias<B6>; 323 def D7 : AArch64Reg<7, "d7", [S7], ["v7", ""]>, DwarfRegAlias<B7>; 324 def D8 : AArch64Reg<8, "d8", [S8], ["v8", ""]>, DwarfRegAlias<B8>; 325 def D9 : AArch64Reg<9, "d9", [S9], ["v9", ""]>, DwarfRegAlias<B9>; 326 def D10 : AArch64Reg<10, "d10", [S10], ["v10", ""]>, DwarfRegAlias<B10>; 327 def D11 : AArch64Reg<11, "d11", [S11], ["v11", ""]>, DwarfRegAlias<B11>; 328 def D12 : AArch64Reg<12, "d12", [S12], ["v12", ""]>, DwarfRegAlias<B12>; 329 def D13 : AArch64Reg<13, "d13", [S13], ["v13", ""]>, DwarfRegAlias<B13>; 330 def D14 : AArch64Reg<14, "d14", [S14], ["v14", ""]>, DwarfRegAlias<B14>; 331 def D15 : AArch64Reg<15, "d15", [S15], ["v15", ""]>, DwarfRegAlias<B15>; 332 def D16 : AArch64Reg<16, "d16", [S16], ["v16", ""]>, DwarfRegAlias<B16>; 333 def D17 : AArch64Reg<17, "d17", [S17], ["v17", ""]>, DwarfRegAlias<B17>; 334 def D18 : AArch64Reg<18, "d18", [S18], ["v18", ""]>, DwarfRegAlias<B18>; 335 def D19 : AArch64Reg<19, "d19", [S19], ["v19", ""]>, DwarfRegAlias<B19>; 336 def D20 : AArch64Reg<20, "d20", [S20], ["v20", ""]>, DwarfRegAlias<B20>; 337 def D21 : AArch64Reg<21, "d21", [S21], ["v21", ""]>, DwarfRegAlias<B21>; 338 def D22 : AArch64Reg<22, "d22", [S22], ["v22", ""]>, DwarfRegAlias<B22>; 339 def D23 : AArch64Reg<23, "d23", [S23], ["v23", ""]>, DwarfRegAlias<B23>; 340 def D24 : AArch64Reg<24, "d24", [S24], ["v24", ""]>, DwarfRegAlias<B24>; 341 def D25 : AArch64Reg<25, "d25", [S25], ["v25", ""]>, DwarfRegAlias<B25>; 342 def D26 : AArch64Reg<26, "d26", [S26], ["v26", ""]>, DwarfRegAlias<B26>; 343 def D27 : AArch64Reg<27, "d27", [S27], ["v27", ""]>, DwarfRegAlias<B27>; 344 def D28 : AArch64Reg<28, "d28", [S28], ["v28", ""]>, DwarfRegAlias<B28>; 345 def D29 : AArch64Reg<29, "d29", [S29], ["v29", ""]>, DwarfRegAlias<B29>; 346 def D30 : AArch64Reg<30, "d30", [S30], ["v30", ""]>, DwarfRegAlias<B30>; 347 def D31 : AArch64Reg<31, "d31", [S31], ["v31", ""]>, DwarfRegAlias<B31>; 348 } 349 350 let SubRegIndices = [dsub], RegAltNameIndices = [vreg, vlist1] in { 351 def Q0 : AArch64Reg<0, "q0", [D0], ["v0", ""]>, DwarfRegAlias<B0>; 352 def Q1 : AArch64Reg<1, "q1", [D1], ["v1", ""]>, DwarfRegAlias<B1>; 353 def Q2 : AArch64Reg<2, "q2", [D2], ["v2", ""]>, DwarfRegAlias<B2>; 354 def Q3 : AArch64Reg<3, "q3", [D3], ["v3", ""]>, DwarfRegAlias<B3>; 355 def Q4 : AArch64Reg<4, "q4", [D4], ["v4", ""]>, DwarfRegAlias<B4>; 356 def Q5 : AArch64Reg<5, "q5", [D5], ["v5", ""]>, DwarfRegAlias<B5>; 357 def Q6 : AArch64Reg<6, "q6", [D6], ["v6", ""]>, DwarfRegAlias<B6>; 358 def Q7 : AArch64Reg<7, "q7", [D7], ["v7", ""]>, DwarfRegAlias<B7>; 359 def Q8 : AArch64Reg<8, "q8", [D8], ["v8", ""]>, DwarfRegAlias<B8>; 360 def Q9 : AArch64Reg<9, "q9", [D9], ["v9", ""]>, DwarfRegAlias<B9>; 361 def Q10 : AArch64Reg<10, "q10", [D10], ["v10", ""]>, DwarfRegAlias<B10>; 362 def Q11 : AArch64Reg<11, "q11", [D11], ["v11", ""]>, DwarfRegAlias<B11>; 363 def Q12 : AArch64Reg<12, "q12", [D12], ["v12", ""]>, DwarfRegAlias<B12>; 364 def Q13 : AArch64Reg<13, "q13", [D13], ["v13", ""]>, DwarfRegAlias<B13>; 365 def Q14 : AArch64Reg<14, "q14", [D14], ["v14", ""]>, DwarfRegAlias<B14>; 366 def Q15 : AArch64Reg<15, "q15", [D15], ["v15", ""]>, DwarfRegAlias<B15>; 367 def Q16 : AArch64Reg<16, "q16", [D16], ["v16", ""]>, DwarfRegAlias<B16>; 368 def Q17 : AArch64Reg<17, "q17", [D17], ["v17", ""]>, DwarfRegAlias<B17>; 369 def Q18 : AArch64Reg<18, "q18", [D18], ["v18", ""]>, DwarfRegAlias<B18>; 370 def Q19 : AArch64Reg<19, "q19", [D19], ["v19", ""]>, DwarfRegAlias<B19>; 371 def Q20 : AArch64Reg<20, "q20", [D20], ["v20", ""]>, DwarfRegAlias<B20>; 372 def Q21 : AArch64Reg<21, "q21", [D21], ["v21", ""]>, DwarfRegAlias<B21>; 373 def Q22 : AArch64Reg<22, "q22", [D22], ["v22", ""]>, DwarfRegAlias<B22>; 374 def Q23 : AArch64Reg<23, "q23", [D23], ["v23", ""]>, DwarfRegAlias<B23>; 375 def Q24 : AArch64Reg<24, "q24", [D24], ["v24", ""]>, DwarfRegAlias<B24>; 376 def Q25 : AArch64Reg<25, "q25", [D25], ["v25", ""]>, DwarfRegAlias<B25>; 377 def Q26 : AArch64Reg<26, "q26", [D26], ["v26", ""]>, DwarfRegAlias<B26>; 378 def Q27 : AArch64Reg<27, "q27", [D27], ["v27", ""]>, DwarfRegAlias<B27>; 379 def Q28 : AArch64Reg<28, "q28", [D28], ["v28", ""]>, DwarfRegAlias<B28>; 380 def Q29 : AArch64Reg<29, "q29", [D29], ["v29", ""]>, DwarfRegAlias<B29>; 381 def Q30 : AArch64Reg<30, "q30", [D30], ["v30", ""]>, DwarfRegAlias<B30>; 382 def Q31 : AArch64Reg<31, "q31", [D31], ["v31", ""]>, DwarfRegAlias<B31>; 383 } 384 385 def FPR8 : RegisterClass<"AArch64", [untyped], 8, (sequence "B%u", 0, 31)> { 386 let Size = 8; 387 } 388 def FPR16 : RegisterClass<"AArch64", [f16], 16, (sequence "H%u", 0, 31)> { 389 let Size = 16; 390 } 391 def FPR32 : RegisterClass<"AArch64", [f32, i32], 32,(sequence "S%u", 0, 31)>; 392 def FPR64 : RegisterClass<"AArch64", [f64, i64, v2f32, v1f64, v8i8, v4i16, v2i32, 393 v1i64], 394 64, (sequence "D%u", 0, 31)>; 395 // We don't (yet) have an f128 legal type, so don't use that here. We 396 // normalize 128-bit vectors to v2f64 for arg passing and such, so use 397 // that here. 398 def FPR128 : RegisterClass<"AArch64", 399 [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, f128], 400 128, (sequence "Q%u", 0, 31)>; 401 402 // The lower 16 vector registers. Some instructions can only take registers 403 // in this range. 404 def FPR128_lo : RegisterClass<"AArch64", 405 [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 406 128, (trunc FPR128, 16)>; 407 408 // Pairs, triples, and quads of 64-bit vector registers. 409 def DSeqPairs : RegisterTuples<[dsub0, dsub1], [(rotl FPR64, 0), (rotl FPR64, 1)]>; 410 def DSeqTriples : RegisterTuples<[dsub0, dsub1, dsub2], 411 [(rotl FPR64, 0), (rotl FPR64, 1), 412 (rotl FPR64, 2)]>; 413 def DSeqQuads : RegisterTuples<[dsub0, dsub1, dsub2, dsub3], 414 [(rotl FPR64, 0), (rotl FPR64, 1), 415 (rotl FPR64, 2), (rotl FPR64, 3)]>; 416 def DD : RegisterClass<"AArch64", [untyped], 64, (add DSeqPairs)> { 417 let Size = 128; 418 } 419 def DDD : RegisterClass<"AArch64", [untyped], 64, (add DSeqTriples)> { 420 let Size = 196; 421 } 422 def DDDD : RegisterClass<"AArch64", [untyped], 64, (add DSeqQuads)> { 423 let Size = 256; 424 } 425 426 // Pairs, triples, and quads of 128-bit vector registers. 427 def QSeqPairs : RegisterTuples<[qsub0, qsub1], [(rotl FPR128, 0), (rotl FPR128, 1)]>; 428 def QSeqTriples : RegisterTuples<[qsub0, qsub1, qsub2], 429 [(rotl FPR128, 0), (rotl FPR128, 1), 430 (rotl FPR128, 2)]>; 431 def QSeqQuads : RegisterTuples<[qsub0, qsub1, qsub2, qsub3], 432 [(rotl FPR128, 0), (rotl FPR128, 1), 433 (rotl FPR128, 2), (rotl FPR128, 3)]>; 434 def QQ : RegisterClass<"AArch64", [untyped], 128, (add QSeqPairs)> { 435 let Size = 256; 436 } 437 def QQQ : RegisterClass<"AArch64", [untyped], 128, (add QSeqTriples)> { 438 let Size = 384; 439 } 440 def QQQQ : RegisterClass<"AArch64", [untyped], 128, (add QSeqQuads)> { 441 let Size = 512; 442 } 443 444 445 // Vector operand versions of the FP registers. Alternate name printing and 446 // assmebler matching. 447 def VectorReg64AsmOperand : AsmOperandClass { 448 let Name = "VectorReg64"; 449 let PredicateMethod = "isVectorReg"; 450 } 451 def VectorReg128AsmOperand : AsmOperandClass { 452 let Name = "VectorReg128"; 453 let PredicateMethod = "isVectorReg"; 454 } 455 456 def V64 : RegisterOperand<FPR64, "printVRegOperand"> { 457 let ParserMatchClass = VectorReg64AsmOperand; 458 } 459 460 def V128 : RegisterOperand<FPR128, "printVRegOperand"> { 461 let ParserMatchClass = VectorReg128AsmOperand; 462 } 463 464 def VectorRegLoAsmOperand : AsmOperandClass { let Name = "VectorRegLo"; } 465 def V128_lo : RegisterOperand<FPR128_lo, "printVRegOperand"> { 466 let ParserMatchClass = VectorRegLoAsmOperand; 467 } 468 469 class TypedVecListAsmOperand<int count, int regsize, int lanes, string kind> 470 : AsmOperandClass { 471 let Name = "TypedVectorList" # count # "_" # lanes # kind; 472 473 let PredicateMethod 474 = "isTypedVectorList<" # count # ", " # lanes # ", '" # kind # "'>"; 475 let RenderMethod = "addVectorList" # regsize # "Operands<" # count # ">"; 476 } 477 478 class TypedVecListRegOperand<RegisterClass Reg, int lanes, string kind> 479 : RegisterOperand<Reg, "printTypedVectorList<" # lanes # ", '" 480 # kind # "'>">; 481 482 multiclass VectorList<int count, RegisterClass Reg64, RegisterClass Reg128> { 483 // With implicit types (probably on instruction instead). E.g. { v0, v1 } 484 def _64AsmOperand : AsmOperandClass { 485 let Name = NAME # "64"; 486 let PredicateMethod = "isImplicitlyTypedVectorList<" # count # ">"; 487 let RenderMethod = "addVectorList64Operands<" # count # ">"; 488 } 489 490 def "64" : RegisterOperand<Reg64, "printImplicitlyTypedVectorList"> { 491 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_64AsmOperand"); 492 } 493 494 def _128AsmOperand : AsmOperandClass { 495 let Name = NAME # "128"; 496 let PredicateMethod = "isImplicitlyTypedVectorList<" # count # ">"; 497 let RenderMethod = "addVectorList128Operands<" # count # ">"; 498 } 499 500 def "128" : RegisterOperand<Reg128, "printImplicitlyTypedVectorList"> { 501 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_128AsmOperand"); 502 } 503 504 // 64-bit register lists with explicit type. 505 506 // { v0.8b, v1.8b } 507 def _8bAsmOperand : TypedVecListAsmOperand<count, 64, 8, "b">; 508 def "8b" : TypedVecListRegOperand<Reg64, 8, "b"> { 509 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_8bAsmOperand"); 510 } 511 512 // { v0.4h, v1.4h } 513 def _4hAsmOperand : TypedVecListAsmOperand<count, 64, 4, "h">; 514 def "4h" : TypedVecListRegOperand<Reg64, 4, "h"> { 515 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_4hAsmOperand"); 516 } 517 518 // { v0.2s, v1.2s } 519 def _2sAsmOperand : TypedVecListAsmOperand<count, 64, 2, "s">; 520 def "2s" : TypedVecListRegOperand<Reg64, 2, "s"> { 521 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_2sAsmOperand"); 522 } 523 524 // { v0.1d, v1.1d } 525 def _1dAsmOperand : TypedVecListAsmOperand<count, 64, 1, "d">; 526 def "1d" : TypedVecListRegOperand<Reg64, 1, "d"> { 527 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_1dAsmOperand"); 528 } 529 530 // 128-bit register lists with explicit type 531 532 // { v0.16b, v1.16b } 533 def _16bAsmOperand : TypedVecListAsmOperand<count, 128, 16, "b">; 534 def "16b" : TypedVecListRegOperand<Reg128, 16, "b"> { 535 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_16bAsmOperand"); 536 } 537 538 // { v0.8h, v1.8h } 539 def _8hAsmOperand : TypedVecListAsmOperand<count, 128, 8, "h">; 540 def "8h" : TypedVecListRegOperand<Reg128, 8, "h"> { 541 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_8hAsmOperand"); 542 } 543 544 // { v0.4s, v1.4s } 545 def _4sAsmOperand : TypedVecListAsmOperand<count, 128, 4, "s">; 546 def "4s" : TypedVecListRegOperand<Reg128, 4, "s"> { 547 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_4sAsmOperand"); 548 } 549 550 // { v0.2d, v1.2d } 551 def _2dAsmOperand : TypedVecListAsmOperand<count, 128, 2, "d">; 552 def "2d" : TypedVecListRegOperand<Reg128, 2, "d"> { 553 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_2dAsmOperand"); 554 } 555 556 // { v0.b, v1.b } 557 def _bAsmOperand : TypedVecListAsmOperand<count, 128, 0, "b">; 558 def "b" : TypedVecListRegOperand<Reg128, 0, "b"> { 559 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_bAsmOperand"); 560 } 561 562 // { v0.h, v1.h } 563 def _hAsmOperand : TypedVecListAsmOperand<count, 128, 0, "h">; 564 def "h" : TypedVecListRegOperand<Reg128, 0, "h"> { 565 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_hAsmOperand"); 566 } 567 568 // { v0.s, v1.s } 569 def _sAsmOperand : TypedVecListAsmOperand<count, 128, 0, "s">; 570 def "s" : TypedVecListRegOperand<Reg128, 0, "s"> { 571 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_sAsmOperand"); 572 } 573 574 // { v0.d, v1.d } 575 def _dAsmOperand : TypedVecListAsmOperand<count, 128, 0, "d">; 576 def "d" : TypedVecListRegOperand<Reg128, 0, "d"> { 577 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_dAsmOperand"); 578 } 579 580 581 } 582 583 defm VecListOne : VectorList<1, FPR64, FPR128>; 584 defm VecListTwo : VectorList<2, DD, QQ>; 585 defm VecListThree : VectorList<3, DDD, QQQ>; 586 defm VecListFour : VectorList<4, DDDD, QQQQ>; 587 588 589 // Register operand versions of the scalar FP registers. 590 def FPR16Op : RegisterOperand<FPR16, "printOperand">; 591 def FPR32Op : RegisterOperand<FPR32, "printOperand">; 592 def FPR64Op : RegisterOperand<FPR64, "printOperand">; 593 def FPR128Op : RegisterOperand<FPR128, "printOperand">; 594
