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      1 //===-- PPCCodeEmitter.cpp - JIT Code Emitter for PowerPC -----------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file defines the PowerPC 32-bit CodeEmitter and associated machinery to
     11 // JIT-compile bitcode to native PowerPC.
     12 //
     13 //===----------------------------------------------------------------------===//
     14 
     15 #include "PPC.h"
     16 #include "PPCRelocations.h"
     17 #include "PPCTargetMachine.h"
     18 #include "llvm/CodeGen/JITCodeEmitter.h"
     19 #include "llvm/CodeGen/MachineFunctionPass.h"
     20 #include "llvm/CodeGen/MachineInstrBuilder.h"
     21 #include "llvm/CodeGen/MachineModuleInfo.h"
     22 #include "llvm/IR/Module.h"
     23 #include "llvm/PassManager.h"
     24 #include "llvm/Support/ErrorHandling.h"
     25 #include "llvm/Support/raw_ostream.h"
     26 #include "llvm/Target/TargetOptions.h"
     27 using namespace llvm;
     28 
     29 namespace {
     30   class PPCCodeEmitter : public MachineFunctionPass {
     31     TargetMachine &TM;
     32     JITCodeEmitter &MCE;
     33     MachineModuleInfo *MMI;
     34 
     35     void getAnalysisUsage(AnalysisUsage &AU) const override {
     36       AU.addRequired<MachineModuleInfo>();
     37       MachineFunctionPass::getAnalysisUsage(AU);
     38     }
     39 
     40     static char ID;
     41 
     42     /// MovePCtoLROffset - When/if we see a MovePCtoLR instruction, we record
     43     /// its address in the function into this pointer.
     44     void *MovePCtoLROffset;
     45   public:
     46 
     47     PPCCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
     48       : MachineFunctionPass(ID), TM(tm), MCE(mce) {}
     49 
     50     /// getBinaryCodeForInstr - This function, generated by the
     51     /// CodeEmitterGenerator using TableGen, produces the binary encoding for
     52     /// machine instructions.
     53     uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
     54 
     55 
     56     MachineRelocation GetRelocation(const MachineOperand &MO,
     57                                     unsigned RelocID) const;
     58 
     59     /// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr
     60     unsigned getMachineOpValue(const MachineInstr &MI,
     61                                const MachineOperand &MO) const;
     62 
     63     unsigned get_crbitm_encoding(const MachineInstr &MI, unsigned OpNo) const;
     64     unsigned getDirectBrEncoding(const MachineInstr &MI, unsigned OpNo) const;
     65     unsigned getCondBrEncoding(const MachineInstr &MI, unsigned OpNo) const;
     66     unsigned getAbsDirectBrEncoding(const MachineInstr &MI,
     67                                     unsigned OpNo) const;
     68     unsigned getAbsCondBrEncoding(const MachineInstr &MI, unsigned OpNo) const;
     69 
     70     unsigned getImm16Encoding(const MachineInstr &MI, unsigned OpNo) const;
     71     unsigned getMemRIEncoding(const MachineInstr &MI, unsigned OpNo) const;
     72     unsigned getMemRIXEncoding(const MachineInstr &MI, unsigned OpNo) const;
     73     unsigned getTLSRegEncoding(const MachineInstr &MI, unsigned OpNo) const;
     74     unsigned getTLSCallEncoding(const MachineInstr &MI, unsigned OpNo) const;
     75 
     76     const char *getPassName() const override {
     77       return "PowerPC Machine Code Emitter";
     78     }
     79 
     80     /// runOnMachineFunction - emits the given MachineFunction to memory
     81     ///
     82     bool runOnMachineFunction(MachineFunction &MF) override;
     83 
     84     /// emitBasicBlock - emits the given MachineBasicBlock to memory
     85     ///
     86     void emitBasicBlock(MachineBasicBlock &MBB);
     87   };
     88 }
     89 
     90 char PPCCodeEmitter::ID = 0;
     91 
     92 /// createPPCCodeEmitterPass - Return a pass that emits the collected PPC code
     93 /// to the specified MCE object.
     94 FunctionPass *llvm::createPPCJITCodeEmitterPass(PPCTargetMachine &TM,
     95                                                 JITCodeEmitter &JCE) {
     96   return new PPCCodeEmitter(TM, JCE);
     97 }
     98 
     99 bool PPCCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
    100   assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
    101           MF.getTarget().getRelocationModel() != Reloc::Static) &&
    102          "JIT relocation model must be set to static or default!");
    103 
    104   MMI = &getAnalysis<MachineModuleInfo>();
    105   MCE.setModuleInfo(MMI);
    106   do {
    107     MovePCtoLROffset = nullptr;
    108     MCE.startFunction(MF);
    109     for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB)
    110       emitBasicBlock(*BB);
    111   } while (MCE.finishFunction(MF));
    112 
    113   return false;
    114 }
    115 
    116 void PPCCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
    117   MCE.StartMachineBasicBlock(&MBB);
    118 
    119   for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){
    120     const MachineInstr &MI = *I;
    121     MCE.processDebugLoc(MI.getDebugLoc(), true);
    122     switch (MI.getOpcode()) {
    123     default:
    124       MCE.emitWordBE(getBinaryCodeForInstr(MI));
    125       break;
    126     case TargetOpcode::CFI_INSTRUCTION:
    127       break;
    128     case TargetOpcode::EH_LABEL:
    129       MCE.emitLabel(MI.getOperand(0).getMCSymbol());
    130       break;
    131     case TargetOpcode::IMPLICIT_DEF:
    132     case TargetOpcode::KILL:
    133       break; // pseudo opcode, no side effects
    134     case PPC::MovePCtoLR:
    135     case PPC::MovePCtoLR8:
    136       assert(TM.getRelocationModel() == Reloc::PIC_);
    137       MovePCtoLROffset = (void*)MCE.getCurrentPCValue();
    138       MCE.emitWordBE(0x48000005);   // bl 1
    139       break;
    140     }
    141     MCE.processDebugLoc(MI.getDebugLoc(), false);
    142   }
    143 }
    144 
    145 unsigned PPCCodeEmitter::get_crbitm_encoding(const MachineInstr &MI,
    146                                              unsigned OpNo) const {
    147   const MachineOperand &MO = MI.getOperand(OpNo);
    148   assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 ||
    149           MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) &&
    150          (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
    151   return 0x80 >> TM.getRegisterInfo()->getEncodingValue(MO.getReg());
    152 }
    153 
    154 MachineRelocation PPCCodeEmitter::GetRelocation(const MachineOperand &MO,
    155                                                 unsigned RelocID) const {
    156   // If in PIC mode, we need to encode the negated address of the
    157   // 'movepctolr' into the unrelocated field.  After relocation, we'll have
    158   // &gv-&movepctolr-4 in the imm field.  Once &movepctolr is added to the imm
    159   // field, we get &gv.  This doesn't happen for branch relocations, which are
    160   // always implicitly pc relative.
    161   intptr_t Cst = 0;
    162   if (TM.getRelocationModel() == Reloc::PIC_) {
    163     assert(MovePCtoLROffset && "MovePCtoLR not seen yet?");
    164     Cst = -(intptr_t)MovePCtoLROffset - 4;
    165   }
    166 
    167   if (MO.isGlobal())
    168     return MachineRelocation::getGV(MCE.getCurrentPCOffset(), RelocID,
    169                                     const_cast<GlobalValue *>(MO.getGlobal()),
    170                                     Cst, isa<Function>(MO.getGlobal()));
    171   if (MO.isSymbol())
    172     return MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
    173                                         RelocID, MO.getSymbolName(), Cst);
    174   if (MO.isCPI())
    175     return MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
    176                                            RelocID, MO.getIndex(), Cst);
    177 
    178   if (MO.isMBB())
    179     return MachineRelocation::getBB(MCE.getCurrentPCOffset(),
    180                                     RelocID, MO.getMBB());
    181 
    182   assert(MO.isJTI());
    183   return MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
    184                                          RelocID, MO.getIndex(), Cst);
    185 }
    186 
    187 unsigned PPCCodeEmitter::getDirectBrEncoding(const MachineInstr &MI,
    188                                              unsigned OpNo) const {
    189   const MachineOperand &MO = MI.getOperand(OpNo);
    190   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO);
    191 
    192   MCE.addRelocation(GetRelocation(MO, PPC::reloc_pcrel_bx));
    193   return 0;
    194 }
    195 
    196 unsigned PPCCodeEmitter::getCondBrEncoding(const MachineInstr &MI,
    197                                            unsigned OpNo) const {
    198   const MachineOperand &MO = MI.getOperand(OpNo);
    199   MCE.addRelocation(GetRelocation(MO, PPC::reloc_pcrel_bcx));
    200   return 0;
    201 }
    202 
    203 unsigned PPCCodeEmitter::getAbsDirectBrEncoding(const MachineInstr &MI,
    204                                                 unsigned OpNo) const {
    205   const MachineOperand &MO = MI.getOperand(OpNo);
    206   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO);
    207 
    208   llvm_unreachable("Absolute branch relocations unsupported on the old JIT.");
    209 }
    210 
    211 unsigned PPCCodeEmitter::getAbsCondBrEncoding(const MachineInstr &MI,
    212                                               unsigned OpNo) const {
    213   llvm_unreachable("Absolute branch relocations unsupported on the old JIT.");
    214 }
    215 
    216 unsigned PPCCodeEmitter::getImm16Encoding(const MachineInstr &MI,
    217                                           unsigned OpNo) const {
    218   const MachineOperand &MO = MI.getOperand(OpNo);
    219   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO);
    220 
    221   unsigned RelocID;
    222   switch (MO.getTargetFlags() & PPCII::MO_ACCESS_MASK) {
    223     default: llvm_unreachable("Unsupported target operand flags!");
    224     case PPCII::MO_LO: RelocID = PPC::reloc_absolute_low; break;
    225     case PPCII::MO_HA: RelocID = PPC::reloc_absolute_high; break;
    226   }
    227 
    228   MCE.addRelocation(GetRelocation(MO, RelocID));
    229   return 0;
    230 }
    231 
    232 unsigned PPCCodeEmitter::getMemRIEncoding(const MachineInstr &MI,
    233                                           unsigned OpNo) const {
    234   // Encode (imm, reg) as a memri, which has the low 16-bits as the
    235   // displacement and the next 5 bits as the register #.
    236   assert(MI.getOperand(OpNo+1).isReg());
    237   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1)) << 16;
    238 
    239   const MachineOperand &MO = MI.getOperand(OpNo);
    240   if (MO.isImm())
    241     return (getMachineOpValue(MI, MO) & 0xFFFF) | RegBits;
    242 
    243   // Add a fixup for the displacement field.
    244   MCE.addRelocation(GetRelocation(MO, PPC::reloc_absolute_low));
    245   return RegBits;
    246 }
    247 
    248 unsigned PPCCodeEmitter::getMemRIXEncoding(const MachineInstr &MI,
    249                                            unsigned OpNo) const {
    250   // Encode (imm, reg) as a memrix, which has the low 14-bits as the
    251   // displacement and the next 5 bits as the register #.
    252   assert(MI.getOperand(OpNo+1).isReg());
    253   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1)) << 14;
    254 
    255   const MachineOperand &MO = MI.getOperand(OpNo);
    256   if (MO.isImm())
    257     return ((getMachineOpValue(MI, MO) >> 2) & 0x3FFF) | RegBits;
    258 
    259   MCE.addRelocation(GetRelocation(MO, PPC::reloc_absolute_low_ix));
    260   return RegBits;
    261 }
    262 
    263 
    264 unsigned PPCCodeEmitter::getTLSRegEncoding(const MachineInstr &MI,
    265                                            unsigned OpNo) const {
    266   llvm_unreachable("TLS not supported on the old JIT.");
    267   return 0;
    268 }
    269 
    270 unsigned PPCCodeEmitter::getTLSCallEncoding(const MachineInstr &MI,
    271                                             unsigned OpNo) const {
    272   llvm_unreachable("TLS not supported on the old JIT.");
    273   return 0;
    274 }
    275 
    276 unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI,
    277                                            const MachineOperand &MO) const {
    278 
    279   if (MO.isReg()) {
    280     // MTOCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
    281     // The GPR operand should come through here though.
    282     assert((MI.getOpcode() != PPC::MTOCRF && MI.getOpcode() != PPC::MTOCRF8 &&
    283             MI.getOpcode() != PPC::MFOCRF && MI.getOpcode() != PPC::MFOCRF8) ||
    284            MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
    285     return TM.getRegisterInfo()->getEncodingValue(MO.getReg());
    286   }
    287 
    288   assert(MO.isImm() &&
    289          "Relocation required in an instruction that we cannot encode!");
    290   return MO.getImm();
    291 }
    292 
    293 #include "PPCGenCodeEmitter.inc"
    294