1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 /// \file 9 //===----------------------------------------------------------------------===// 10 11 #ifndef AMDGPU_H 12 #define AMDGPU_H 13 14 #include "llvm/Support/TargetRegistry.h" 15 #include "llvm/Target/TargetMachine.h" 16 17 namespace llvm { 18 19 class AMDGPUInstrPrinter; 20 class AMDGPUSubtarget; 21 class AMDGPUTargetMachine; 22 class FunctionPass; 23 class MCAsmInfo; 24 class raw_ostream; 25 class Target; 26 class TargetMachine; 27 28 // R600 Passes 29 FunctionPass *createR600VectorRegMerger(TargetMachine &tm); 30 FunctionPass *createR600TextureIntrinsicsReplacer(); 31 FunctionPass *createR600ExpandSpecialInstrsPass(TargetMachine &tm); 32 FunctionPass *createR600EmitClauseMarkers(); 33 FunctionPass *createR600ClauseMergePass(TargetMachine &tm); 34 FunctionPass *createR600Packetizer(TargetMachine &tm); 35 FunctionPass *createR600ControlFlowFinalizer(TargetMachine &tm); 36 FunctionPass *createAMDGPUCFGStructurizerPass(); 37 38 // SI Passes 39 FunctionPass *createSITypeRewriter(); 40 FunctionPass *createSIAnnotateControlFlowPass(); 41 FunctionPass *createSILowerI1CopiesPass(); 42 FunctionPass *createSILowerControlFlowPass(TargetMachine &tm); 43 FunctionPass *createSIFixSGPRCopiesPass(TargetMachine &tm); 44 FunctionPass *createSIFixSGPRLiveRangesPass(); 45 FunctionPass *createSICodeEmitterPass(formatted_raw_ostream &OS); 46 FunctionPass *createSIInsertWaits(TargetMachine &tm); 47 48 void initializeSILowerI1CopiesPass(PassRegistry &); 49 extern char &SILowerI1CopiesID; 50 51 // Passes common to R600 and SI 52 FunctionPass *createAMDGPUPromoteAlloca(const AMDGPUSubtarget &ST); 53 Pass *createAMDGPUStructurizeCFGPass(); 54 FunctionPass *createAMDGPUISelDag(TargetMachine &tm); 55 56 /// \brief Creates an AMDGPU-specific Target Transformation Info pass. 57 ImmutablePass * 58 createAMDGPUTargetTransformInfoPass(const AMDGPUTargetMachine *TM); 59 60 void initializeSIFixSGPRLiveRangesPass(PassRegistry&); 61 extern char &SIFixSGPRLiveRangesID; 62 63 64 extern Target TheAMDGPUTarget; 65 66 } // End namespace llvm 67 68 namespace ShaderType { 69 enum Type { 70 PIXEL = 0, 71 VERTEX = 1, 72 GEOMETRY = 2, 73 COMPUTE = 3 74 }; 75 } 76 77 /// OpenCL uses address spaces to differentiate between 78 /// various memory regions on the hardware. On the CPU 79 /// all of the address spaces point to the same memory, 80 /// however on the GPU, each address space points to 81 /// a separate piece of memory that is unique from other 82 /// memory locations. 83 namespace AMDGPUAS { 84 enum AddressSpaces { 85 PRIVATE_ADDRESS = 0, ///< Address space for private memory. 86 GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0). 87 CONSTANT_ADDRESS = 2, ///< Address space for constant memory 88 LOCAL_ADDRESS = 3, ///< Address space for local memory. 89 FLAT_ADDRESS = 4, ///< Address space for flat memory. 90 REGION_ADDRESS = 5, ///< Address space for region memory. 91 PARAM_D_ADDRESS = 6, ///< Address space for direct addressible parameter memory (CONST0) 92 PARAM_I_ADDRESS = 7, ///< Address space for indirect addressible parameter memory (VTX1) 93 94 // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on this 95 // order to be able to dynamically index a constant buffer, for example: 96 // 97 // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx 98 99 CONSTANT_BUFFER_0 = 8, 100 CONSTANT_BUFFER_1 = 9, 101 CONSTANT_BUFFER_2 = 10, 102 CONSTANT_BUFFER_3 = 11, 103 CONSTANT_BUFFER_4 = 12, 104 CONSTANT_BUFFER_5 = 13, 105 CONSTANT_BUFFER_6 = 14, 106 CONSTANT_BUFFER_7 = 15, 107 CONSTANT_BUFFER_8 = 16, 108 CONSTANT_BUFFER_9 = 17, 109 CONSTANT_BUFFER_10 = 18, 110 CONSTANT_BUFFER_11 = 19, 111 CONSTANT_BUFFER_12 = 20, 112 CONSTANT_BUFFER_13 = 21, 113 CONSTANT_BUFFER_14 = 22, 114 CONSTANT_BUFFER_15 = 23, 115 ADDRESS_NONE = 24, ///< Address space for unknown memory. 116 LAST_ADDRESS = ADDRESS_NONE 117 }; 118 119 } // namespace AMDGPUAS 120 121 #endif // AMDGPU_H 122
