1 //===-- R600Instructions.td - R600 Instruction defs -------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // TableGen definitions for instructions which are available on R600 family 11 // GPUs. 12 // 13 //===----------------------------------------------------------------------===// 14 15 include "R600Intrinsics.td" 16 include "R600InstrFormats.td" 17 18 class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> : 19 InstR600 <outs, ins, asm, pattern, NullALU> { 20 21 let Namespace = "AMDGPU"; 22 } 23 24 def MEMxi : Operand<iPTR> { 25 let MIOperandInfo = (ops R600_TReg32_X:$ptr, i32imm:$index); 26 let PrintMethod = "printMemOperand"; 27 } 28 29 def MEMrr : Operand<iPTR> { 30 let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index); 31 } 32 33 // Operands for non-registers 34 35 class InstFlag<string PM = "printOperand", int Default = 0> 36 : OperandWithDefaultOps <i32, (ops (i32 Default))> { 37 let PrintMethod = PM; 38 } 39 40 // src_sel for ALU src operands, see also ALU_CONST, ALU_PARAM registers 41 def SEL : OperandWithDefaultOps <i32, (ops (i32 -1))> { 42 let PrintMethod = "printSel"; 43 } 44 def BANK_SWIZZLE : OperandWithDefaultOps <i32, (ops (i32 0))> { 45 let PrintMethod = "printBankSwizzle"; 46 } 47 48 def LITERAL : InstFlag<"printLiteral">; 49 50 def WRITE : InstFlag <"printWrite", 1>; 51 def OMOD : InstFlag <"printOMOD">; 52 def REL : InstFlag <"printRel">; 53 def CLAMP : InstFlag <"printClamp">; 54 def NEG : InstFlag <"printNeg">; 55 def ABS : InstFlag <"printAbs">; 56 def UEM : InstFlag <"printUpdateExecMask">; 57 def UP : InstFlag <"printUpdatePred">; 58 59 // XXX: The r600g finalizer in Mesa expects last to be one in most cases. 60 // Once we start using the packetizer in this backend we should have this 61 // default to 0. 62 def LAST : InstFlag<"printLast", 1>; 63 def RSel : Operand<i32> { 64 let PrintMethod = "printRSel"; 65 } 66 def CT: Operand<i32> { 67 let PrintMethod = "printCT"; 68 } 69 70 def FRAMEri : Operand<iPTR> { 71 let MIOperandInfo = (ops R600_Reg32:$ptr, i32imm:$index); 72 } 73 74 def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>; 75 def ADDRDWord : ComplexPattern<i32, 1, "SelectADDRDWord", [], []>; 76 def ADDRVTX_READ : ComplexPattern<i32, 2, "SelectADDRVTX_READ", [], []>; 77 def ADDRGA_CONST_OFFSET : ComplexPattern<i32, 1, "SelectGlobalValueConstantOffset", [], []>; 78 def ADDRGA_VAR_OFFSET : ComplexPattern<i32, 2, "SelectGlobalValueVariableOffset", [], []>; 79 80 81 def R600_Pred : PredicateOperand<i32, (ops R600_Predicate), 82 (ops PRED_SEL_OFF)>; 83 84 85 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { 86 87 // Class for instructions with only one source register. 88 // If you add new ins to this instruction, make sure they are listed before 89 // $literal, because the backend currently assumes that the last operand is 90 // a literal. Also be sure to update the enum R600Op1OperandIndex::ROI in 91 // R600Defines.h, R600InstrInfo::buildDefaultInstruction(), 92 // and R600InstrInfo::getOperandIdx(). 93 class R600_1OP <bits<11> inst, string opName, list<dag> pattern, 94 InstrItinClass itin = AnyALU> : 95 InstR600 <(outs R600_Reg32:$dst), 96 (ins WRITE:$write, OMOD:$omod, REL:$dst_rel, CLAMP:$clamp, 97 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel, 98 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal, 99 BANK_SWIZZLE:$bank_swizzle), 100 !strconcat(" ", opName, 101 "$clamp $last $dst$write$dst_rel$omod, " 102 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, " 103 "$pred_sel $bank_swizzle"), 104 pattern, 105 itin>, 106 R600ALU_Word0, 107 R600ALU_Word1_OP2 <inst> { 108 109 let src1 = 0; 110 let src1_rel = 0; 111 let src1_neg = 0; 112 let src1_abs = 0; 113 let update_exec_mask = 0; 114 let update_pred = 0; 115 let HasNativeOperands = 1; 116 let Op1 = 1; 117 let ALUInst = 1; 118 let DisableEncoding = "$literal"; 119 let UseNamedOperandTable = 1; 120 121 let Inst{31-0} = Word0; 122 let Inst{63-32} = Word1; 123 } 124 125 class R600_1OP_Helper <bits<11> inst, string opName, SDPatternOperator node, 126 InstrItinClass itin = AnyALU> : 127 R600_1OP <inst, opName, 128 [(set R600_Reg32:$dst, (node R600_Reg32:$src0))], itin 129 >; 130 131 // If you add or change the operands for R600_2OP instructions, you must 132 // also update the R600Op2OperandIndex::ROI enum in R600Defines.h, 133 // R600InstrInfo::buildDefaultInstruction(), and R600InstrInfo::getOperandIdx(). 134 class R600_2OP <bits<11> inst, string opName, list<dag> pattern, 135 InstrItinClass itin = AnyALU> : 136 InstR600 <(outs R600_Reg32:$dst), 137 (ins UEM:$update_exec_mask, UP:$update_pred, WRITE:$write, 138 OMOD:$omod, REL:$dst_rel, CLAMP:$clamp, 139 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel, 140 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, ABS:$src1_abs, SEL:$src1_sel, 141 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal, 142 BANK_SWIZZLE:$bank_swizzle), 143 !strconcat(" ", opName, 144 "$clamp $last $update_exec_mask$update_pred$dst$write$dst_rel$omod, " 145 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, " 146 "$src1_neg$src1_abs$src1$src1_abs$src1_rel, " 147 "$pred_sel $bank_swizzle"), 148 pattern, 149 itin>, 150 R600ALU_Word0, 151 R600ALU_Word1_OP2 <inst> { 152 153 let HasNativeOperands = 1; 154 let Op2 = 1; 155 let ALUInst = 1; 156 let DisableEncoding = "$literal"; 157 let UseNamedOperandTable = 1; 158 159 let Inst{31-0} = Word0; 160 let Inst{63-32} = Word1; 161 } 162 163 class R600_2OP_Helper <bits<11> inst, string opName, SDPatternOperator node, 164 InstrItinClass itin = AnyALU> : 165 R600_2OP <inst, opName, 166 [(set R600_Reg32:$dst, (node R600_Reg32:$src0, 167 R600_Reg32:$src1))], itin 168 >; 169 170 // If you add our change the operands for R600_3OP instructions, you must 171 // also update the R600Op3OperandIndex::ROI enum in R600Defines.h, 172 // R600InstrInfo::buildDefaultInstruction(), and 173 // R600InstrInfo::getOperandIdx(). 174 class R600_3OP <bits<5> inst, string opName, list<dag> pattern, 175 InstrItinClass itin = AnyALU> : 176 InstR600 <(outs R600_Reg32:$dst), 177 (ins REL:$dst_rel, CLAMP:$clamp, 178 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, SEL:$src0_sel, 179 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, SEL:$src1_sel, 180 R600_Reg32:$src2, NEG:$src2_neg, REL:$src2_rel, SEL:$src2_sel, 181 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal, 182 BANK_SWIZZLE:$bank_swizzle), 183 !strconcat(" ", opName, "$clamp $last $dst$dst_rel, " 184 "$src0_neg$src0$src0_rel, " 185 "$src1_neg$src1$src1_rel, " 186 "$src2_neg$src2$src2_rel, " 187 "$pred_sel" 188 "$bank_swizzle"), 189 pattern, 190 itin>, 191 R600ALU_Word0, 192 R600ALU_Word1_OP3<inst>{ 193 194 let HasNativeOperands = 1; 195 let DisableEncoding = "$literal"; 196 let Op3 = 1; 197 let UseNamedOperandTable = 1; 198 let ALUInst = 1; 199 200 let Inst{31-0} = Word0; 201 let Inst{63-32} = Word1; 202 } 203 204 class R600_REDUCTION <bits<11> inst, dag ins, string asm, list<dag> pattern, 205 InstrItinClass itin = VecALU> : 206 InstR600 <(outs R600_Reg32:$dst), 207 ins, 208 asm, 209 pattern, 210 itin>; 211 212 213 214 } // End mayLoad = 1, mayStore = 0, hasSideEffects = 0 215 216 def TEX_SHADOW : PatLeaf< 217 (imm), 218 [{uint32_t TType = (uint32_t)N->getZExtValue(); 219 return (TType >= 6 && TType <= 8) || (TType >= 11 && TType <= 13); 220 }] 221 >; 222 223 def TEX_RECT : PatLeaf< 224 (imm), 225 [{uint32_t TType = (uint32_t)N->getZExtValue(); 226 return TType == 5; 227 }] 228 >; 229 230 def TEX_ARRAY : PatLeaf< 231 (imm), 232 [{uint32_t TType = (uint32_t)N->getZExtValue(); 233 return TType == 9 || TType == 10 || TType == 16; 234 }] 235 >; 236 237 def TEX_SHADOW_ARRAY : PatLeaf< 238 (imm), 239 [{uint32_t TType = (uint32_t)N->getZExtValue(); 240 return TType == 11 || TType == 12 || TType == 17; 241 }] 242 >; 243 244 def TEX_MSAA : PatLeaf< 245 (imm), 246 [{uint32_t TType = (uint32_t)N->getZExtValue(); 247 return TType == 14; 248 }] 249 >; 250 251 def TEX_ARRAY_MSAA : PatLeaf< 252 (imm), 253 [{uint32_t TType = (uint32_t)N->getZExtValue(); 254 return TType == 15; 255 }] 256 >; 257 258 class EG_CF_RAT <bits <8> cfinst, bits <6> ratinst, bits<4> ratid, bits<4> mask, 259 dag outs, dag ins, string asm, list<dag> pattern> : 260 InstR600ISA <outs, ins, asm, pattern>, 261 CF_ALLOC_EXPORT_WORD0_RAT, CF_ALLOC_EXPORT_WORD1_BUF { 262 263 let rat_id = ratid; 264 let rat_inst = ratinst; 265 let rim = 0; 266 // XXX: Have a separate instruction for non-indexed writes. 267 let type = 1; 268 let rw_rel = 0; 269 let elem_size = 0; 270 271 let array_size = 0; 272 let comp_mask = mask; 273 let burst_count = 0; 274 let vpm = 0; 275 let cf_inst = cfinst; 276 let mark = 0; 277 let barrier = 1; 278 279 let Inst{31-0} = Word0; 280 let Inst{63-32} = Word1; 281 let IsExport = 1; 282 283 } 284 285 class VTX_READ <string name, bits<8> buffer_id, dag outs, list<dag> pattern> 286 : InstR600ISA <outs, (ins MEMxi:$src_gpr), name, pattern>, 287 VTX_WORD1_GPR { 288 289 // Static fields 290 let DST_REL = 0; 291 // The docs say that if this bit is set, then DATA_FORMAT, NUM_FORMAT_ALL, 292 // FORMAT_COMP_ALL, SRF_MODE_ALL, and ENDIAN_SWAP fields will be ignored, 293 // however, based on my testing if USE_CONST_FIELDS is set, then all 294 // these fields need to be set to 0. 295 let USE_CONST_FIELDS = 0; 296 let NUM_FORMAT_ALL = 1; 297 let FORMAT_COMP_ALL = 0; 298 let SRF_MODE_ALL = 0; 299 300 let Inst{63-32} = Word1; 301 // LLVM can only encode 64-bit instructions, so these fields are manually 302 // encoded in R600CodeEmitter 303 // 304 // bits<16> OFFSET; 305 // bits<2> ENDIAN_SWAP = 0; 306 // bits<1> CONST_BUF_NO_STRIDE = 0; 307 // bits<1> MEGA_FETCH = 0; 308 // bits<1> ALT_CONST = 0; 309 // bits<2> BUFFER_INDEX_MODE = 0; 310 311 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding 312 // is done in R600CodeEmitter 313 // 314 // Inst{79-64} = OFFSET; 315 // Inst{81-80} = ENDIAN_SWAP; 316 // Inst{82} = CONST_BUF_NO_STRIDE; 317 // Inst{83} = MEGA_FETCH; 318 // Inst{84} = ALT_CONST; 319 // Inst{86-85} = BUFFER_INDEX_MODE; 320 // Inst{95-86} = 0; Reserved 321 322 // VTX_WORD3 (Padding) 323 // 324 // Inst{127-96} = 0; 325 326 let VTXInst = 1; 327 } 328 329 class LoadParamFrag <PatFrag load_type> : PatFrag < 330 (ops node:$ptr), (load_type node:$ptr), 331 [{ return isConstantLoad(dyn_cast<LoadSDNode>(N), 0); }] 332 >; 333 334 def load_param : LoadParamFrag<load>; 335 def load_param_exti8 : LoadParamFrag<az_extloadi8>; 336 def load_param_exti16 : LoadParamFrag<az_extloadi16>; 337 338 def isR600 : Predicate<"Subtarget.getGeneration() <= AMDGPUSubtarget::R700">; 339 340 def isR600toCayman : Predicate< 341 "Subtarget.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS">; 342 343 //===----------------------------------------------------------------------===// 344 // R600 SDNodes 345 //===----------------------------------------------------------------------===// 346 347 def INTERP_PAIR_XY : AMDGPUShaderInst < 348 (outs R600_TReg32_X:$dst0, R600_TReg32_Y:$dst1), 349 (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2), 350 "INTERP_PAIR_XY $src0 $src1 $src2 : $dst0 dst1", 351 []>; 352 353 def INTERP_PAIR_ZW : AMDGPUShaderInst < 354 (outs R600_TReg32_Z:$dst0, R600_TReg32_W:$dst1), 355 (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2), 356 "INTERP_PAIR_ZW $src0 $src1 $src2 : $dst0 dst1", 357 []>; 358 359 def CONST_ADDRESS: SDNode<"AMDGPUISD::CONST_ADDRESS", 360 SDTypeProfile<1, -1, [SDTCisInt<0>, SDTCisPtrTy<1>]>, 361 [SDNPVariadic] 362 >; 363 364 def DOT4 : SDNode<"AMDGPUISD::DOT4", 365 SDTypeProfile<1, 8, [SDTCisFP<0>, SDTCisVT<1, f32>, SDTCisVT<2, f32>, 366 SDTCisVT<3, f32>, SDTCisVT<4, f32>, SDTCisVT<5, f32>, 367 SDTCisVT<6, f32>, SDTCisVT<7, f32>, SDTCisVT<8, f32>]>, 368 [] 369 >; 370 371 def COS_HW : SDNode<"AMDGPUISD::COS_HW", 372 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]> 373 >; 374 375 def SIN_HW : SDNode<"AMDGPUISD::SIN_HW", 376 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]> 377 >; 378 379 def TEXTURE_FETCH_Type : SDTypeProfile<1, 19, [SDTCisFP<0>]>; 380 381 def TEXTURE_FETCH: SDNode<"AMDGPUISD::TEXTURE_FETCH", TEXTURE_FETCH_Type, []>; 382 383 multiclass TexPattern<bits<32> TextureOp, Instruction inst, ValueType vt = v4f32> { 384 def : Pat<(TEXTURE_FETCH (i32 TextureOp), vt:$SRC_GPR, 385 (i32 imm:$srcx), (i32 imm:$srcy), (i32 imm:$srcz), (i32 imm:$srcw), 386 (i32 imm:$offsetx), (i32 imm:$offsety), (i32 imm:$offsetz), 387 (i32 imm:$DST_SEL_X), (i32 imm:$DST_SEL_Y), (i32 imm:$DST_SEL_Z), 388 (i32 imm:$DST_SEL_W), 389 (i32 imm:$RESOURCE_ID), (i32 imm:$SAMPLER_ID), 390 (i32 imm:$COORD_TYPE_X), (i32 imm:$COORD_TYPE_Y), (i32 imm:$COORD_TYPE_Z), 391 (i32 imm:$COORD_TYPE_W)), 392 (inst R600_Reg128:$SRC_GPR, 393 imm:$srcx, imm:$srcy, imm:$srcz, imm:$srcw, 394 imm:$offsetx, imm:$offsety, imm:$offsetz, 395 imm:$DST_SEL_X, imm:$DST_SEL_Y, imm:$DST_SEL_Z, 396 imm:$DST_SEL_W, 397 imm:$RESOURCE_ID, imm:$SAMPLER_ID, 398 imm:$COORD_TYPE_X, imm:$COORD_TYPE_Y, imm:$COORD_TYPE_Z, 399 imm:$COORD_TYPE_W)>; 400 } 401 402 //===----------------------------------------------------------------------===// 403 // Interpolation Instructions 404 //===----------------------------------------------------------------------===// 405 406 def INTERP_VEC_LOAD : AMDGPUShaderInst < 407 (outs R600_Reg128:$dst), 408 (ins i32imm:$src0), 409 "INTERP_LOAD $src0 : $dst", 410 [(set R600_Reg128:$dst, (int_R600_interp_const imm:$src0))]>; 411 412 def INTERP_XY : R600_2OP <0xD6, "INTERP_XY", []> { 413 let bank_swizzle = 5; 414 } 415 416 def INTERP_ZW : R600_2OP <0xD7, "INTERP_ZW", []> { 417 let bank_swizzle = 5; 418 } 419 420 def INTERP_LOAD_P0 : R600_1OP <0xE0, "INTERP_LOAD_P0", []>; 421 422 //===----------------------------------------------------------------------===// 423 // Export Instructions 424 //===----------------------------------------------------------------------===// 425 426 def ExportType : SDTypeProfile<0, 7, [SDTCisFP<0>, SDTCisInt<1>]>; 427 428 def EXPORT: SDNode<"AMDGPUISD::EXPORT", ExportType, 429 [SDNPHasChain, SDNPSideEffect]>; 430 431 class ExportWord0 { 432 field bits<32> Word0; 433 434 bits<13> arraybase; 435 bits<2> type; 436 bits<7> gpr; 437 bits<2> elem_size; 438 439 let Word0{12-0} = arraybase; 440 let Word0{14-13} = type; 441 let Word0{21-15} = gpr; 442 let Word0{22} = 0; // RW_REL 443 let Word0{29-23} = 0; // INDEX_GPR 444 let Word0{31-30} = elem_size; 445 } 446 447 class ExportSwzWord1 { 448 field bits<32> Word1; 449 450 bits<3> sw_x; 451 bits<3> sw_y; 452 bits<3> sw_z; 453 bits<3> sw_w; 454 bits<1> eop; 455 bits<8> inst; 456 457 let Word1{2-0} = sw_x; 458 let Word1{5-3} = sw_y; 459 let Word1{8-6} = sw_z; 460 let Word1{11-9} = sw_w; 461 } 462 463 class ExportBufWord1 { 464 field bits<32> Word1; 465 466 bits<12> arraySize; 467 bits<4> compMask; 468 bits<1> eop; 469 bits<8> inst; 470 471 let Word1{11-0} = arraySize; 472 let Word1{15-12} = compMask; 473 } 474 475 multiclass ExportPattern<Instruction ExportInst, bits<8> cf_inst> { 476 def : Pat<(int_R600_store_pixel_depth R600_Reg32:$reg), 477 (ExportInst 478 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), R600_Reg32:$reg, sub0), 479 0, 61, 0, 7, 7, 7, cf_inst, 0) 480 >; 481 482 def : Pat<(int_R600_store_pixel_stencil R600_Reg32:$reg), 483 (ExportInst 484 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), R600_Reg32:$reg, sub0), 485 0, 61, 7, 0, 7, 7, cf_inst, 0) 486 >; 487 488 def : Pat<(int_R600_store_dummy (i32 imm:$type)), 489 (ExportInst 490 (v4f32 (IMPLICIT_DEF)), imm:$type, 0, 7, 7, 7, 7, cf_inst, 0) 491 >; 492 493 def : Pat<(int_R600_store_dummy 1), 494 (ExportInst 495 (v4f32 (IMPLICIT_DEF)), 1, 60, 7, 7, 7, 7, cf_inst, 0) 496 >; 497 498 def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 imm:$base), (i32 imm:$type), 499 (i32 imm:$swz_x), (i32 imm:$swz_y), (i32 imm:$swz_z), (i32 imm:$swz_w)), 500 (ExportInst R600_Reg128:$src, imm:$type, imm:$base, 501 imm:$swz_x, imm:$swz_y, imm:$swz_z, imm:$swz_w, cf_inst, 0) 502 >; 503 504 } 505 506 multiclass SteamOutputExportPattern<Instruction ExportInst, 507 bits<8> buf0inst, bits<8> buf1inst, bits<8> buf2inst, bits<8> buf3inst> { 508 // Stream0 509 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src), 510 (i32 imm:$arraybase), (i32 0), (i32 imm:$mask)), 511 (ExportInst R600_Reg128:$src, 0, imm:$arraybase, 512 4095, imm:$mask, buf0inst, 0)>; 513 // Stream1 514 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src), 515 (i32 imm:$arraybase), (i32 1), (i32 imm:$mask)), 516 (ExportInst R600_Reg128:$src, 0, imm:$arraybase, 517 4095, imm:$mask, buf1inst, 0)>; 518 // Stream2 519 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src), 520 (i32 imm:$arraybase), (i32 2), (i32 imm:$mask)), 521 (ExportInst R600_Reg128:$src, 0, imm:$arraybase, 522 4095, imm:$mask, buf2inst, 0)>; 523 // Stream3 524 def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src), 525 (i32 imm:$arraybase), (i32 3), (i32 imm:$mask)), 526 (ExportInst R600_Reg128:$src, 0, imm:$arraybase, 527 4095, imm:$mask, buf3inst, 0)>; 528 } 529 530 // Export Instructions should not be duplicated by TailDuplication pass 531 // (which assumes that duplicable instruction are affected by exec mask) 532 let usesCustomInserter = 1, isNotDuplicable = 1 in { 533 534 class ExportSwzInst : InstR600ISA<( 535 outs), 536 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase, 537 RSel:$sw_x, RSel:$sw_y, RSel:$sw_z, RSel:$sw_w, i32imm:$inst, 538 i32imm:$eop), 539 !strconcat("EXPORT", " $gpr.$sw_x$sw_y$sw_z$sw_w"), 540 []>, ExportWord0, ExportSwzWord1 { 541 let elem_size = 3; 542 let Inst{31-0} = Word0; 543 let Inst{63-32} = Word1; 544 let IsExport = 1; 545 } 546 547 } // End usesCustomInserter = 1 548 549 class ExportBufInst : InstR600ISA<( 550 outs), 551 (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase, 552 i32imm:$arraySize, i32imm:$compMask, i32imm:$inst, i32imm:$eop), 553 !strconcat("EXPORT", " $gpr"), 554 []>, ExportWord0, ExportBufWord1 { 555 let elem_size = 0; 556 let Inst{31-0} = Word0; 557 let Inst{63-32} = Word1; 558 let IsExport = 1; 559 } 560 561 //===----------------------------------------------------------------------===// 562 // Control Flow Instructions 563 //===----------------------------------------------------------------------===// 564 565 566 def KCACHE : InstFlag<"printKCache">; 567 568 class ALU_CLAUSE<bits<4> inst, string OpName> : AMDGPUInst <(outs), 569 (ins i32imm:$ADDR, i32imm:$KCACHE_BANK0, i32imm:$KCACHE_BANK1, 570 KCACHE:$KCACHE_MODE0, KCACHE:$KCACHE_MODE1, 571 i32imm:$KCACHE_ADDR0, i32imm:$KCACHE_ADDR1, 572 i32imm:$COUNT, i32imm:$Enabled), 573 !strconcat(OpName, " $COUNT, @$ADDR, " 574 "KC0[$KCACHE_MODE0], KC1[$KCACHE_MODE1]"), 575 [] >, CF_ALU_WORD0, CF_ALU_WORD1 { 576 field bits<64> Inst; 577 578 let CF_INST = inst; 579 let ALT_CONST = 0; 580 let WHOLE_QUAD_MODE = 0; 581 let BARRIER = 1; 582 let UseNamedOperandTable = 1; 583 584 let Inst{31-0} = Word0; 585 let Inst{63-32} = Word1; 586 } 587 588 class CF_WORD0_R600 { 589 field bits<32> Word0; 590 591 bits<32> ADDR; 592 593 let Word0 = ADDR; 594 } 595 596 class CF_CLAUSE_R600 <bits<7> inst, dag ins, string AsmPrint> : AMDGPUInst <(outs), 597 ins, AsmPrint, [] >, CF_WORD0_R600, CF_WORD1_R600 { 598 field bits<64> Inst; 599 bits<4> CNT; 600 601 let CF_INST = inst; 602 let BARRIER = 1; 603 let CF_CONST = 0; 604 let VALID_PIXEL_MODE = 0; 605 let COND = 0; 606 let COUNT = CNT{2-0}; 607 let CALL_COUNT = 0; 608 let COUNT_3 = CNT{3}; 609 let END_OF_PROGRAM = 0; 610 let WHOLE_QUAD_MODE = 0; 611 612 let Inst{31-0} = Word0; 613 let Inst{63-32} = Word1; 614 } 615 616 class CF_CLAUSE_EG <bits<8> inst, dag ins, string AsmPrint> : AMDGPUInst <(outs), 617 ins, AsmPrint, [] >, CF_WORD0_EG, CF_WORD1_EG { 618 field bits<64> Inst; 619 620 let CF_INST = inst; 621 let BARRIER = 1; 622 let JUMPTABLE_SEL = 0; 623 let CF_CONST = 0; 624 let VALID_PIXEL_MODE = 0; 625 let COND = 0; 626 let END_OF_PROGRAM = 0; 627 628 let Inst{31-0} = Word0; 629 let Inst{63-32} = Word1; 630 } 631 632 def CF_ALU : ALU_CLAUSE<8, "ALU">; 633 def CF_ALU_PUSH_BEFORE : ALU_CLAUSE<9, "ALU_PUSH_BEFORE">; 634 def CF_ALU_POP_AFTER : ALU_CLAUSE<10, "ALU_POP_AFTER">; 635 def CF_ALU_CONTINUE : ALU_CLAUSE<13, "ALU_CONTINUE">; 636 def CF_ALU_BREAK : ALU_CLAUSE<14, "ALU_BREAK">; 637 def CF_ALU_ELSE_AFTER : ALU_CLAUSE<15, "ALU_ELSE_AFTER">; 638 639 def FETCH_CLAUSE : AMDGPUInst <(outs), 640 (ins i32imm:$addr), "Fetch clause starting at $addr:", [] > { 641 field bits<8> Inst; 642 bits<8> num; 643 let Inst = num; 644 } 645 646 def ALU_CLAUSE : AMDGPUInst <(outs), 647 (ins i32imm:$addr), "ALU clause starting at $addr:", [] > { 648 field bits<8> Inst; 649 bits<8> num; 650 let Inst = num; 651 } 652 653 def LITERALS : AMDGPUInst <(outs), 654 (ins LITERAL:$literal1, LITERAL:$literal2), "$literal1, $literal2", [] > { 655 field bits<64> Inst; 656 bits<32> literal1; 657 bits<32> literal2; 658 659 let Inst{31-0} = literal1; 660 let Inst{63-32} = literal2; 661 } 662 663 def PAD : AMDGPUInst <(outs), (ins), "PAD", [] > { 664 field bits<64> Inst; 665 } 666 667 let Predicates = [isR600toCayman] in { 668 669 //===----------------------------------------------------------------------===// 670 // Common Instructions R600, R700, Evergreen, Cayman 671 //===----------------------------------------------------------------------===// 672 673 def ADD : R600_2OP_Helper <0x0, "ADD", fadd>; 674 // Non-IEEE MUL: 0 * anything = 0 675 def MUL : R600_2OP_Helper <0x1, "MUL NON-IEEE", int_AMDGPU_mul>; 676 def MUL_IEEE : R600_2OP_Helper <0x2, "MUL_IEEE", fmul>; 677 def MAX : R600_2OP_Helper <0x3, "MAX", AMDGPUfmax>; 678 def MIN : R600_2OP_Helper <0x4, "MIN", AMDGPUfmin>; 679 680 // For the SET* instructions there is a naming conflict in TargetSelectionDAG.td, 681 // so some of the instruction names don't match the asm string. 682 // XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics. 683 def SETE : R600_2OP < 684 0x08, "SETE", 685 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_OEQ))] 686 >; 687 688 def SGT : R600_2OP < 689 0x09, "SETGT", 690 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_OGT))] 691 >; 692 693 def SGE : R600_2OP < 694 0xA, "SETGE", 695 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_OGE))] 696 >; 697 698 def SNE : R600_2OP < 699 0xB, "SETNE", 700 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_UNE))] 701 >; 702 703 def SETE_DX10 : R600_2OP < 704 0xC, "SETE_DX10", 705 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_OEQ))] 706 >; 707 708 def SETGT_DX10 : R600_2OP < 709 0xD, "SETGT_DX10", 710 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_OGT))] 711 >; 712 713 def SETGE_DX10 : R600_2OP < 714 0xE, "SETGE_DX10", 715 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_OGE))] 716 >; 717 718 def SETNE_DX10 : R600_2OP < 719 0xF, "SETNE_DX10", 720 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_UNE))] 721 >; 722 723 def FRACT : R600_1OP_Helper <0x10, "FRACT", AMDGPUfract>; 724 def TRUNC : R600_1OP_Helper <0x11, "TRUNC", ftrunc>; 725 def CEIL : R600_1OP_Helper <0x12, "CEIL", fceil>; 726 def RNDNE : R600_1OP_Helper <0x13, "RNDNE", frint>; 727 def FLOOR : R600_1OP_Helper <0x14, "FLOOR", ffloor>; 728 729 def MOV : R600_1OP <0x19, "MOV", []>; 730 731 let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1 in { 732 733 class MOV_IMM <ValueType vt, Operand immType> : AMDGPUInst < 734 (outs R600_Reg32:$dst), 735 (ins immType:$imm), 736 "", 737 [] 738 >; 739 740 } // end let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1 741 742 def MOV_IMM_I32 : MOV_IMM<i32, i32imm>; 743 def : Pat < 744 (imm:$val), 745 (MOV_IMM_I32 imm:$val) 746 >; 747 748 def MOV_IMM_F32 : MOV_IMM<f32, f32imm>; 749 def : Pat < 750 (fpimm:$val), 751 (MOV_IMM_F32 fpimm:$val) 752 >; 753 754 def PRED_SETE : R600_2OP <0x20, "PRED_SETE", []>; 755 def PRED_SETGT : R600_2OP <0x21, "PRED_SETGT", []>; 756 def PRED_SETGE : R600_2OP <0x22, "PRED_SETGE", []>; 757 def PRED_SETNE : R600_2OP <0x23, "PRED_SETNE", []>; 758 759 let hasSideEffects = 1 in { 760 761 def KILLGT : R600_2OP <0x2D, "KILLGT", []>; 762 763 } // end hasSideEffects 764 765 def AND_INT : R600_2OP_Helper <0x30, "AND_INT", and>; 766 def OR_INT : R600_2OP_Helper <0x31, "OR_INT", or>; 767 def XOR_INT : R600_2OP_Helper <0x32, "XOR_INT", xor>; 768 def NOT_INT : R600_1OP_Helper <0x33, "NOT_INT", not>; 769 def ADD_INT : R600_2OP_Helper <0x34, "ADD_INT", add>; 770 def SUB_INT : R600_2OP_Helper <0x35, "SUB_INT", sub>; 771 def MAX_INT : R600_2OP_Helper <0x36, "MAX_INT", AMDGPUsmax>; 772 def MIN_INT : R600_2OP_Helper <0x37, "MIN_INT", AMDGPUsmin>; 773 def MAX_UINT : R600_2OP_Helper <0x38, "MAX_UINT", AMDGPUumax>; 774 def MIN_UINT : R600_2OP_Helper <0x39, "MIN_UINT", AMDGPUumin>; 775 776 def SETE_INT : R600_2OP < 777 0x3A, "SETE_INT", 778 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETEQ))] 779 >; 780 781 def SETGT_INT : R600_2OP < 782 0x3B, "SETGT_INT", 783 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGT))] 784 >; 785 786 def SETGE_INT : R600_2OP < 787 0x3C, "SETGE_INT", 788 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGE))] 789 >; 790 791 def SETNE_INT : R600_2OP < 792 0x3D, "SETNE_INT", 793 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETNE))] 794 >; 795 796 def SETGT_UINT : R600_2OP < 797 0x3E, "SETGT_UINT", 798 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETUGT))] 799 >; 800 801 def SETGE_UINT : R600_2OP < 802 0x3F, "SETGE_UINT", 803 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETUGE))] 804 >; 805 806 def PRED_SETE_INT : R600_2OP <0x42, "PRED_SETE_INT", []>; 807 def PRED_SETGT_INT : R600_2OP <0x43, "PRED_SETGE_INT", []>; 808 def PRED_SETGE_INT : R600_2OP <0x44, "PRED_SETGE_INT", []>; 809 def PRED_SETNE_INT : R600_2OP <0x45, "PRED_SETNE_INT", []>; 810 811 def CNDE_INT : R600_3OP < 812 0x1C, "CNDE_INT", 813 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_EQ))] 814 >; 815 816 def CNDGE_INT : R600_3OP < 817 0x1E, "CNDGE_INT", 818 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_SGE))] 819 >; 820 821 def CNDGT_INT : R600_3OP < 822 0x1D, "CNDGT_INT", 823 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_SGT))] 824 >; 825 826 //===----------------------------------------------------------------------===// 827 // Texture instructions 828 //===----------------------------------------------------------------------===// 829 830 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { 831 832 class R600_TEX <bits<11> inst, string opName> : 833 InstR600 <(outs R600_Reg128:$DST_GPR), 834 (ins R600_Reg128:$SRC_GPR, 835 RSel:$srcx, RSel:$srcy, RSel:$srcz, RSel:$srcw, 836 i32imm:$offsetx, i32imm:$offsety, i32imm:$offsetz, 837 RSel:$DST_SEL_X, RSel:$DST_SEL_Y, RSel:$DST_SEL_Z, RSel:$DST_SEL_W, 838 i32imm:$RESOURCE_ID, i32imm:$SAMPLER_ID, 839 CT:$COORD_TYPE_X, CT:$COORD_TYPE_Y, CT:$COORD_TYPE_Z, 840 CT:$COORD_TYPE_W), 841 !strconcat(opName, 842 " $DST_GPR.$DST_SEL_X$DST_SEL_Y$DST_SEL_Z$DST_SEL_W, " 843 "$SRC_GPR.$srcx$srcy$srcz$srcw " 844 "RID:$RESOURCE_ID SID:$SAMPLER_ID " 845 "CT:$COORD_TYPE_X$COORD_TYPE_Y$COORD_TYPE_Z$COORD_TYPE_W"), 846 [], 847 NullALU>, TEX_WORD0, TEX_WORD1, TEX_WORD2 { 848 let Inst{31-0} = Word0; 849 let Inst{63-32} = Word1; 850 851 let TEX_INST = inst{4-0}; 852 let SRC_REL = 0; 853 let DST_REL = 0; 854 let LOD_BIAS = 0; 855 856 let INST_MOD = 0; 857 let FETCH_WHOLE_QUAD = 0; 858 let ALT_CONST = 0; 859 let SAMPLER_INDEX_MODE = 0; 860 let RESOURCE_INDEX_MODE = 0; 861 862 let TEXInst = 1; 863 } 864 865 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 0 866 867 868 869 def TEX_SAMPLE : R600_TEX <0x10, "TEX_SAMPLE">; 870 def TEX_SAMPLE_C : R600_TEX <0x18, "TEX_SAMPLE_C">; 871 def TEX_SAMPLE_L : R600_TEX <0x11, "TEX_SAMPLE_L">; 872 def TEX_SAMPLE_C_L : R600_TEX <0x19, "TEX_SAMPLE_C_L">; 873 def TEX_SAMPLE_LB : R600_TEX <0x12, "TEX_SAMPLE_LB">; 874 def TEX_SAMPLE_C_LB : R600_TEX <0x1A, "TEX_SAMPLE_C_LB">; 875 def TEX_LD : R600_TEX <0x03, "TEX_LD">; 876 def TEX_LDPTR : R600_TEX <0x03, "TEX_LDPTR"> { 877 let INST_MOD = 1; 878 } 879 def TEX_GET_TEXTURE_RESINFO : R600_TEX <0x04, "TEX_GET_TEXTURE_RESINFO">; 880 def TEX_GET_GRADIENTS_H : R600_TEX <0x07, "TEX_GET_GRADIENTS_H">; 881 def TEX_GET_GRADIENTS_V : R600_TEX <0x08, "TEX_GET_GRADIENTS_V">; 882 def TEX_SET_GRADIENTS_H : R600_TEX <0x0B, "TEX_SET_GRADIENTS_H">; 883 def TEX_SET_GRADIENTS_V : R600_TEX <0x0C, "TEX_SET_GRADIENTS_V">; 884 def TEX_SAMPLE_G : R600_TEX <0x14, "TEX_SAMPLE_G">; 885 def TEX_SAMPLE_C_G : R600_TEX <0x1C, "TEX_SAMPLE_C_G">; 886 887 defm : TexPattern<0, TEX_SAMPLE>; 888 defm : TexPattern<1, TEX_SAMPLE_C>; 889 defm : TexPattern<2, TEX_SAMPLE_L>; 890 defm : TexPattern<3, TEX_SAMPLE_C_L>; 891 defm : TexPattern<4, TEX_SAMPLE_LB>; 892 defm : TexPattern<5, TEX_SAMPLE_C_LB>; 893 defm : TexPattern<6, TEX_LD, v4i32>; 894 defm : TexPattern<7, TEX_GET_TEXTURE_RESINFO, v4i32>; 895 defm : TexPattern<8, TEX_GET_GRADIENTS_H>; 896 defm : TexPattern<9, TEX_GET_GRADIENTS_V>; 897 defm : TexPattern<10, TEX_LDPTR, v4i32>; 898 899 //===----------------------------------------------------------------------===// 900 // Helper classes for common instructions 901 //===----------------------------------------------------------------------===// 902 903 class MUL_LIT_Common <bits<5> inst> : R600_3OP < 904 inst, "MUL_LIT", 905 [] 906 >; 907 908 class MULADD_Common <bits<5> inst> : R600_3OP < 909 inst, "MULADD", 910 [] 911 >; 912 913 class MULADD_IEEE_Common <bits<5> inst> : R600_3OP < 914 inst, "MULADD_IEEE", 915 [(set f32:$dst, (fadd (fmul f32:$src0, f32:$src1), f32:$src2))] 916 >; 917 918 class CNDE_Common <bits<5> inst> : R600_3OP < 919 inst, "CNDE", 920 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_OEQ))] 921 >; 922 923 class CNDGT_Common <bits<5> inst> : R600_3OP < 924 inst, "CNDGT", 925 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_OGT))] 926 > { 927 let Itinerary = VecALU; 928 } 929 930 class CNDGE_Common <bits<5> inst> : R600_3OP < 931 inst, "CNDGE", 932 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_OGE))] 933 > { 934 let Itinerary = VecALU; 935 } 936 937 938 let isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU" in { 939 class R600_VEC2OP<list<dag> pattern> : InstR600 <(outs R600_Reg32:$dst), (ins 940 // Slot X 941 UEM:$update_exec_mask_X, UP:$update_pred_X, WRITE:$write_X, 942 OMOD:$omod_X, REL:$dst_rel_X, CLAMP:$clamp_X, 943 R600_TReg32_X:$src0_X, NEG:$src0_neg_X, REL:$src0_rel_X, ABS:$src0_abs_X, SEL:$src0_sel_X, 944 R600_TReg32_X:$src1_X, NEG:$src1_neg_X, REL:$src1_rel_X, ABS:$src1_abs_X, SEL:$src1_sel_X, 945 R600_Pred:$pred_sel_X, 946 // Slot Y 947 UEM:$update_exec_mask_Y, UP:$update_pred_Y, WRITE:$write_Y, 948 OMOD:$omod_Y, REL:$dst_rel_Y, CLAMP:$clamp_Y, 949 R600_TReg32_Y:$src0_Y, NEG:$src0_neg_Y, REL:$src0_rel_Y, ABS:$src0_abs_Y, SEL:$src0_sel_Y, 950 R600_TReg32_Y:$src1_Y, NEG:$src1_neg_Y, REL:$src1_rel_Y, ABS:$src1_abs_Y, SEL:$src1_sel_Y, 951 R600_Pred:$pred_sel_Y, 952 // Slot Z 953 UEM:$update_exec_mask_Z, UP:$update_pred_Z, WRITE:$write_Z, 954 OMOD:$omod_Z, REL:$dst_rel_Z, CLAMP:$clamp_Z, 955 R600_TReg32_Z:$src0_Z, NEG:$src0_neg_Z, REL:$src0_rel_Z, ABS:$src0_abs_Z, SEL:$src0_sel_Z, 956 R600_TReg32_Z:$src1_Z, NEG:$src1_neg_Z, REL:$src1_rel_Z, ABS:$src1_abs_Z, SEL:$src1_sel_Z, 957 R600_Pred:$pred_sel_Z, 958 // Slot W 959 UEM:$update_exec_mask_W, UP:$update_pred_W, WRITE:$write_W, 960 OMOD:$omod_W, REL:$dst_rel_W, CLAMP:$clamp_W, 961 R600_TReg32_W:$src0_W, NEG:$src0_neg_W, REL:$src0_rel_W, ABS:$src0_abs_W, SEL:$src0_sel_W, 962 R600_TReg32_W:$src1_W, NEG:$src1_neg_W, REL:$src1_rel_W, ABS:$src1_abs_W, SEL:$src1_sel_W, 963 R600_Pred:$pred_sel_W, 964 LITERAL:$literal0, LITERAL:$literal1), 965 "", 966 pattern, 967 AnyALU> { 968 969 let UseNamedOperandTable = 1; 970 971 } 972 } 973 974 def DOT_4 : R600_VEC2OP<[(set R600_Reg32:$dst, (DOT4 975 R600_TReg32_X:$src0_X, R600_TReg32_X:$src1_X, 976 R600_TReg32_Y:$src0_Y, R600_TReg32_Y:$src1_Y, 977 R600_TReg32_Z:$src0_Z, R600_TReg32_Z:$src1_Z, 978 R600_TReg32_W:$src0_W, R600_TReg32_W:$src1_W))]>; 979 980 981 class DOT4_Common <bits<11> inst> : R600_2OP <inst, "DOT4", []>; 982 983 984 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { 985 multiclass CUBE_Common <bits<11> inst> { 986 987 def _pseudo : InstR600 < 988 (outs R600_Reg128:$dst), 989 (ins R600_Reg128:$src0), 990 "CUBE $dst $src0", 991 [(set v4f32:$dst, (int_AMDGPU_cube v4f32:$src0))], 992 VecALU 993 > { 994 let isPseudo = 1; 995 let UseNamedOperandTable = 1; 996 } 997 998 def _real : R600_2OP <inst, "CUBE", []>; 999 } 1000 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 0 1001 1002 class EXP_IEEE_Common <bits<11> inst> : R600_1OP_Helper < 1003 inst, "EXP_IEEE", fexp2 1004 > { 1005 let Itinerary = TransALU; 1006 } 1007 1008 class FLT_TO_INT_Common <bits<11> inst> : R600_1OP_Helper < 1009 inst, "FLT_TO_INT", fp_to_sint 1010 > { 1011 let Itinerary = TransALU; 1012 } 1013 1014 class INT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper < 1015 inst, "INT_TO_FLT", sint_to_fp 1016 > { 1017 let Itinerary = TransALU; 1018 } 1019 1020 class FLT_TO_UINT_Common <bits<11> inst> : R600_1OP_Helper < 1021 inst, "FLT_TO_UINT", fp_to_uint 1022 > { 1023 let Itinerary = TransALU; 1024 } 1025 1026 class UINT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper < 1027 inst, "UINT_TO_FLT", uint_to_fp 1028 > { 1029 let Itinerary = TransALU; 1030 } 1031 1032 class LOG_CLAMPED_Common <bits<11> inst> : R600_1OP < 1033 inst, "LOG_CLAMPED", [] 1034 >; 1035 1036 class LOG_IEEE_Common <bits<11> inst> : R600_1OP_Helper < 1037 inst, "LOG_IEEE", flog2 1038 > { 1039 let Itinerary = TransALU; 1040 } 1041 1042 class LSHL_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHL", shl>; 1043 class LSHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHR", srl>; 1044 class ASHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "ASHR", sra>; 1045 class MULHI_INT_Common <bits<11> inst> : R600_2OP_Helper < 1046 inst, "MULHI_INT", mulhs 1047 > { 1048 let Itinerary = TransALU; 1049 } 1050 class MULHI_UINT_Common <bits<11> inst> : R600_2OP_Helper < 1051 inst, "MULHI", mulhu 1052 > { 1053 let Itinerary = TransALU; 1054 } 1055 class MULLO_INT_Common <bits<11> inst> : R600_2OP_Helper < 1056 inst, "MULLO_INT", mul 1057 > { 1058 let Itinerary = TransALU; 1059 } 1060 class MULLO_UINT_Common <bits<11> inst> : R600_2OP <inst, "MULLO_UINT", []> { 1061 let Itinerary = TransALU; 1062 } 1063 1064 class RECIP_CLAMPED_Common <bits<11> inst> : R600_1OP < 1065 inst, "RECIP_CLAMPED", [] 1066 > { 1067 let Itinerary = TransALU; 1068 } 1069 1070 class RECIP_IEEE_Common <bits<11> inst> : R600_1OP < 1071 inst, "RECIP_IEEE", [(set f32:$dst, (fdiv FP_ONE, f32:$src0))] 1072 > { 1073 let Itinerary = TransALU; 1074 } 1075 1076 class RECIP_UINT_Common <bits<11> inst> : R600_1OP_Helper < 1077 inst, "RECIP_UINT", AMDGPUurecip 1078 > { 1079 let Itinerary = TransALU; 1080 } 1081 1082 // Clamped to maximum. 1083 class RECIPSQRT_CLAMPED_Common <bits<11> inst> : R600_1OP_Helper < 1084 inst, "RECIPSQRT_CLAMPED", AMDGPUrsq_clamped 1085 > { 1086 let Itinerary = TransALU; 1087 } 1088 1089 class RECIPSQRT_IEEE_Common <bits<11> inst> : R600_1OP_Helper < 1090 inst, "RECIPSQRT_IEEE", AMDGPUrsq_legacy 1091 > { 1092 let Itinerary = TransALU; 1093 } 1094 1095 // TODO: There is also RECIPSQRT_FF which clamps to zero. 1096 1097 class SIN_Common <bits<11> inst> : R600_1OP < 1098 inst, "SIN", [(set f32:$dst, (SIN_HW f32:$src0))]>{ 1099 let Trig = 1; 1100 let Itinerary = TransALU; 1101 } 1102 1103 class COS_Common <bits<11> inst> : R600_1OP < 1104 inst, "COS", [(set f32:$dst, (COS_HW f32:$src0))]> { 1105 let Trig = 1; 1106 let Itinerary = TransALU; 1107 } 1108 1109 def CLAMP_R600 : CLAMP <R600_Reg32>; 1110 def FABS_R600 : FABS<R600_Reg32>; 1111 def FNEG_R600 : FNEG<R600_Reg32>; 1112 1113 //===----------------------------------------------------------------------===// 1114 // Helper patterns for complex intrinsics 1115 //===----------------------------------------------------------------------===// 1116 1117 multiclass DIV_Common <InstR600 recip_ieee> { 1118 def : Pat< 1119 (int_AMDGPU_div f32:$src0, f32:$src1), 1120 (MUL_IEEE $src0, (recip_ieee $src1)) 1121 >; 1122 1123 def : Pat< 1124 (fdiv f32:$src0, f32:$src1), 1125 (MUL_IEEE $src0, (recip_ieee $src1)) 1126 >; 1127 } 1128 1129 class TGSI_LIT_Z_Common <InstR600 mul_lit, InstR600 log_clamped, InstR600 exp_ieee> 1130 : Pat < 1131 (int_TGSI_lit_z f32:$src_x, f32:$src_y, f32:$src_w), 1132 (exp_ieee (mul_lit (log_clamped (MAX $src_y, (f32 ZERO))), $src_w, $src_x)) 1133 >; 1134 1135 // FROUND pattern 1136 class FROUNDPat<Instruction CNDGE> : Pat < 1137 (AMDGPUround f32:$x), 1138 (CNDGE (ADD (FNEG_R600 (f32 HALF)), (FRACT $x)), (CEIL $x), (FLOOR $x)) 1139 >; 1140 1141 1142 //===----------------------------------------------------------------------===// 1143 // R600 / R700 Instructions 1144 //===----------------------------------------------------------------------===// 1145 1146 let Predicates = [isR600] in { 1147 1148 def MUL_LIT_r600 : MUL_LIT_Common<0x0C>; 1149 def MULADD_r600 : MULADD_Common<0x10>; 1150 def MULADD_IEEE_r600 : MULADD_IEEE_Common<0x14>; 1151 def CNDE_r600 : CNDE_Common<0x18>; 1152 def CNDGT_r600 : CNDGT_Common<0x19>; 1153 def CNDGE_r600 : CNDGE_Common<0x1A>; 1154 def DOT4_r600 : DOT4_Common<0x50>; 1155 defm CUBE_r600 : CUBE_Common<0x52>; 1156 def EXP_IEEE_r600 : EXP_IEEE_Common<0x61>; 1157 def LOG_CLAMPED_r600 : LOG_CLAMPED_Common<0x62>; 1158 def LOG_IEEE_r600 : LOG_IEEE_Common<0x63>; 1159 def RECIP_CLAMPED_r600 : RECIP_CLAMPED_Common<0x64>; 1160 def RECIP_IEEE_r600 : RECIP_IEEE_Common<0x66>; 1161 def RECIPSQRT_CLAMPED_r600 : RECIPSQRT_CLAMPED_Common<0x67>; 1162 def RECIPSQRT_IEEE_r600 : RECIPSQRT_IEEE_Common<0x69>; 1163 def FLT_TO_INT_r600 : FLT_TO_INT_Common<0x6b>; 1164 def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>; 1165 def FLT_TO_UINT_r600 : FLT_TO_UINT_Common<0x79>; 1166 def UINT_TO_FLT_r600 : UINT_TO_FLT_Common<0x6d>; 1167 def SIN_r600 : SIN_Common<0x6E>; 1168 def COS_r600 : COS_Common<0x6F>; 1169 def ASHR_r600 : ASHR_Common<0x70>; 1170 def LSHR_r600 : LSHR_Common<0x71>; 1171 def LSHL_r600 : LSHL_Common<0x72>; 1172 def MULLO_INT_r600 : MULLO_INT_Common<0x73>; 1173 def MULHI_INT_r600 : MULHI_INT_Common<0x74>; 1174 def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>; 1175 def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>; 1176 def RECIP_UINT_r600 : RECIP_UINT_Common <0x78>; 1177 1178 defm DIV_r600 : DIV_Common<RECIP_IEEE_r600>; 1179 def : POW_Common <LOG_IEEE_r600, EXP_IEEE_r600, MUL>; 1180 def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common<MUL_LIT_r600, LOG_CLAMPED_r600, EXP_IEEE_r600>; 1181 1182 def : Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_r600 $src))>; 1183 def : FROUNDPat <CNDGE_r600>; 1184 1185 def R600_ExportSwz : ExportSwzInst { 1186 let Word1{20-17} = 0; // BURST_COUNT 1187 let Word1{21} = eop; 1188 let Word1{22} = 0; // VALID_PIXEL_MODE 1189 let Word1{30-23} = inst; 1190 let Word1{31} = 1; // BARRIER 1191 } 1192 defm : ExportPattern<R600_ExportSwz, 39>; 1193 1194 def R600_ExportBuf : ExportBufInst { 1195 let Word1{20-17} = 0; // BURST_COUNT 1196 let Word1{21} = eop; 1197 let Word1{22} = 0; // VALID_PIXEL_MODE 1198 let Word1{30-23} = inst; 1199 let Word1{31} = 1; // BARRIER 1200 } 1201 defm : SteamOutputExportPattern<R600_ExportBuf, 0x20, 0x21, 0x22, 0x23>; 1202 1203 def CF_TC_R600 : CF_CLAUSE_R600<1, (ins i32imm:$ADDR, i32imm:$CNT), 1204 "TEX $CNT @$ADDR"> { 1205 let POP_COUNT = 0; 1206 } 1207 def CF_VC_R600 : CF_CLAUSE_R600<2, (ins i32imm:$ADDR, i32imm:$CNT), 1208 "VTX $CNT @$ADDR"> { 1209 let POP_COUNT = 0; 1210 } 1211 def WHILE_LOOP_R600 : CF_CLAUSE_R600<6, (ins i32imm:$ADDR), 1212 "LOOP_START_DX10 @$ADDR"> { 1213 let POP_COUNT = 0; 1214 let CNT = 0; 1215 } 1216 def END_LOOP_R600 : CF_CLAUSE_R600<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> { 1217 let POP_COUNT = 0; 1218 let CNT = 0; 1219 } 1220 def LOOP_BREAK_R600 : CF_CLAUSE_R600<9, (ins i32imm:$ADDR), 1221 "LOOP_BREAK @$ADDR"> { 1222 let POP_COUNT = 0; 1223 let CNT = 0; 1224 } 1225 def CF_CONTINUE_R600 : CF_CLAUSE_R600<8, (ins i32imm:$ADDR), 1226 "CONTINUE @$ADDR"> { 1227 let POP_COUNT = 0; 1228 let CNT = 0; 1229 } 1230 def CF_JUMP_R600 : CF_CLAUSE_R600<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 1231 "JUMP @$ADDR POP:$POP_COUNT"> { 1232 let CNT = 0; 1233 } 1234 def CF_PUSH_ELSE_R600 : CF_CLAUSE_R600<12, (ins i32imm:$ADDR), 1235 "PUSH_ELSE @$ADDR"> { 1236 let CNT = 0; 1237 } 1238 def CF_ELSE_R600 : CF_CLAUSE_R600<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 1239 "ELSE @$ADDR POP:$POP_COUNT"> { 1240 let CNT = 0; 1241 } 1242 def CF_CALL_FS_R600 : CF_CLAUSE_R600<19, (ins), "CALL_FS"> { 1243 let ADDR = 0; 1244 let CNT = 0; 1245 let POP_COUNT = 0; 1246 } 1247 def POP_R600 : CF_CLAUSE_R600<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 1248 "POP @$ADDR POP:$POP_COUNT"> { 1249 let CNT = 0; 1250 } 1251 def CF_END_R600 : CF_CLAUSE_R600<0, (ins), "CF_END"> { 1252 let CNT = 0; 1253 let POP_COUNT = 0; 1254 let ADDR = 0; 1255 let END_OF_PROGRAM = 1; 1256 } 1257 1258 } 1259 1260 1261 //===----------------------------------------------------------------------===// 1262 // Regist loads and stores - for indirect addressing 1263 //===----------------------------------------------------------------------===// 1264 1265 defm R600_ : RegisterLoadStore <R600_Reg32, FRAMEri, ADDRIndirect>; 1266 1267 1268 //===----------------------------------------------------------------------===// 1269 // Pseudo instructions 1270 //===----------------------------------------------------------------------===// 1271 1272 let isPseudo = 1 in { 1273 1274 def PRED_X : InstR600 < 1275 (outs R600_Predicate_Bit:$dst), 1276 (ins R600_Reg32:$src0, i32imm:$src1, i32imm:$flags), 1277 "", [], NullALU> { 1278 let FlagOperandIdx = 3; 1279 } 1280 1281 let isTerminator = 1, isBranch = 1 in { 1282 def JUMP_COND : InstR600 < 1283 (outs), 1284 (ins brtarget:$target, R600_Predicate_Bit:$p), 1285 "JUMP $target ($p)", 1286 [], AnyALU 1287 >; 1288 1289 def JUMP : InstR600 < 1290 (outs), 1291 (ins brtarget:$target), 1292 "JUMP $target", 1293 [], AnyALU 1294 > 1295 { 1296 let isPredicable = 1; 1297 let isBarrier = 1; 1298 } 1299 1300 } // End isTerminator = 1, isBranch = 1 1301 1302 let usesCustomInserter = 1 in { 1303 1304 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in { 1305 1306 def MASK_WRITE : AMDGPUShaderInst < 1307 (outs), 1308 (ins R600_Reg32:$src), 1309 "MASK_WRITE $src", 1310 [] 1311 >; 1312 1313 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 1 1314 1315 1316 def TXD: InstR600 < 1317 (outs R600_Reg128:$dst), 1318 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, 1319 i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget), 1320 "TXD $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget", 1321 [(set v4f32:$dst, (int_AMDGPU_txd v4f32:$src0, v4f32:$src1, v4f32:$src2, 1322 imm:$resourceId, imm:$samplerId, imm:$textureTarget))], 1323 NullALU > { 1324 let TEXInst = 1; 1325 } 1326 1327 def TXD_SHADOW: InstR600 < 1328 (outs R600_Reg128:$dst), 1329 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, 1330 i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget), 1331 "TXD_SHADOW $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget", 1332 [(set v4f32:$dst, (int_AMDGPU_txd v4f32:$src0, v4f32:$src1, v4f32:$src2, 1333 imm:$resourceId, imm:$samplerId, TEX_SHADOW:$textureTarget))], 1334 NullALU 1335 > { 1336 let TEXInst = 1; 1337 } 1338 } // End isPseudo = 1 1339 } // End usesCustomInserter = 1 1340 1341 1342 //===----------------------------------------------------------------------===// 1343 // Constant Buffer Addressing Support 1344 //===----------------------------------------------------------------------===// 1345 1346 let usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU" in { 1347 def CONST_COPY : Instruction { 1348 let OutOperandList = (outs R600_Reg32:$dst); 1349 let InOperandList = (ins i32imm:$src); 1350 let Pattern = 1351 [(set R600_Reg32:$dst, (CONST_ADDRESS ADDRGA_CONST_OFFSET:$src))]; 1352 let AsmString = "CONST_COPY"; 1353 let neverHasSideEffects = 1; 1354 let isAsCheapAsAMove = 1; 1355 let Itinerary = NullALU; 1356 } 1357 } // end usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU" 1358 1359 def TEX_VTX_CONSTBUF : 1360 InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), "VTX_READ_eg $dst, $ptr", 1361 [(set v4i32:$dst, (CONST_ADDRESS ADDRGA_VAR_OFFSET:$ptr, (i32 imm:$BUFFER_ID)))]>, 1362 VTX_WORD1_GPR, VTX_WORD0_eg { 1363 1364 let VC_INST = 0; 1365 let FETCH_TYPE = 2; 1366 let FETCH_WHOLE_QUAD = 0; 1367 let SRC_REL = 0; 1368 let SRC_SEL_X = 0; 1369 let DST_REL = 0; 1370 let USE_CONST_FIELDS = 0; 1371 let NUM_FORMAT_ALL = 2; 1372 let FORMAT_COMP_ALL = 1; 1373 let SRF_MODE_ALL = 1; 1374 let MEGA_FETCH_COUNT = 16; 1375 let DST_SEL_X = 0; 1376 let DST_SEL_Y = 1; 1377 let DST_SEL_Z = 2; 1378 let DST_SEL_W = 3; 1379 let DATA_FORMAT = 35; 1380 1381 let Inst{31-0} = Word0; 1382 let Inst{63-32} = Word1; 1383 1384 // LLVM can only encode 64-bit instructions, so these fields are manually 1385 // encoded in R600CodeEmitter 1386 // 1387 // bits<16> OFFSET; 1388 // bits<2> ENDIAN_SWAP = 0; 1389 // bits<1> CONST_BUF_NO_STRIDE = 0; 1390 // bits<1> MEGA_FETCH = 0; 1391 // bits<1> ALT_CONST = 0; 1392 // bits<2> BUFFER_INDEX_MODE = 0; 1393 1394 1395 1396 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding 1397 // is done in R600CodeEmitter 1398 // 1399 // Inst{79-64} = OFFSET; 1400 // Inst{81-80} = ENDIAN_SWAP; 1401 // Inst{82} = CONST_BUF_NO_STRIDE; 1402 // Inst{83} = MEGA_FETCH; 1403 // Inst{84} = ALT_CONST; 1404 // Inst{86-85} = BUFFER_INDEX_MODE; 1405 // Inst{95-86} = 0; Reserved 1406 1407 // VTX_WORD3 (Padding) 1408 // 1409 // Inst{127-96} = 0; 1410 let VTXInst = 1; 1411 } 1412 1413 def TEX_VTX_TEXBUF: 1414 InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), "TEX_VTX_EXPLICIT_READ $dst, $ptr", 1415 [(set v4f32:$dst, (int_R600_load_texbuf ADDRGA_VAR_OFFSET:$ptr, imm:$BUFFER_ID))]>, 1416 VTX_WORD1_GPR, VTX_WORD0_eg { 1417 1418 let VC_INST = 0; 1419 let FETCH_TYPE = 2; 1420 let FETCH_WHOLE_QUAD = 0; 1421 let SRC_REL = 0; 1422 let SRC_SEL_X = 0; 1423 let DST_REL = 0; 1424 let USE_CONST_FIELDS = 1; 1425 let NUM_FORMAT_ALL = 0; 1426 let FORMAT_COMP_ALL = 0; 1427 let SRF_MODE_ALL = 1; 1428 let MEGA_FETCH_COUNT = 16; 1429 let DST_SEL_X = 0; 1430 let DST_SEL_Y = 1; 1431 let DST_SEL_Z = 2; 1432 let DST_SEL_W = 3; 1433 let DATA_FORMAT = 0; 1434 1435 let Inst{31-0} = Word0; 1436 let Inst{63-32} = Word1; 1437 1438 // LLVM can only encode 64-bit instructions, so these fields are manually 1439 // encoded in R600CodeEmitter 1440 // 1441 // bits<16> OFFSET; 1442 // bits<2> ENDIAN_SWAP = 0; 1443 // bits<1> CONST_BUF_NO_STRIDE = 0; 1444 // bits<1> MEGA_FETCH = 0; 1445 // bits<1> ALT_CONST = 0; 1446 // bits<2> BUFFER_INDEX_MODE = 0; 1447 1448 1449 1450 // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding 1451 // is done in R600CodeEmitter 1452 // 1453 // Inst{79-64} = OFFSET; 1454 // Inst{81-80} = ENDIAN_SWAP; 1455 // Inst{82} = CONST_BUF_NO_STRIDE; 1456 // Inst{83} = MEGA_FETCH; 1457 // Inst{84} = ALT_CONST; 1458 // Inst{86-85} = BUFFER_INDEX_MODE; 1459 // Inst{95-86} = 0; Reserved 1460 1461 // VTX_WORD3 (Padding) 1462 // 1463 // Inst{127-96} = 0; 1464 let VTXInst = 1; 1465 } 1466 1467 //===---------------------------------------------------------------------===// 1468 // Flow and Program control Instructions 1469 //===---------------------------------------------------------------------===// 1470 class ILFormat<dag outs, dag ins, string asmstr, list<dag> pattern> 1471 : Instruction { 1472 1473 let Namespace = "AMDGPU"; 1474 dag OutOperandList = outs; 1475 dag InOperandList = ins; 1476 let Pattern = pattern; 1477 let AsmString = !strconcat(asmstr, "\n"); 1478 let isPseudo = 1; 1479 let Itinerary = NullALU; 1480 bit hasIEEEFlag = 0; 1481 bit hasZeroOpFlag = 0; 1482 let mayLoad = 0; 1483 let mayStore = 0; 1484 let hasSideEffects = 0; 1485 } 1486 1487 multiclass BranchConditional<SDNode Op, RegisterClass rci, RegisterClass rcf> { 1488 def _i32 : ILFormat<(outs), 1489 (ins brtarget:$target, rci:$src0), 1490 "; i32 Pseudo branch instruction", 1491 [(Op bb:$target, (i32 rci:$src0))]>; 1492 def _f32 : ILFormat<(outs), 1493 (ins brtarget:$target, rcf:$src0), 1494 "; f32 Pseudo branch instruction", 1495 [(Op bb:$target, (f32 rcf:$src0))]>; 1496 } 1497 1498 // Only scalar types should generate flow control 1499 multiclass BranchInstr<string name> { 1500 def _i32 : ILFormat<(outs), (ins R600_Reg32:$src), 1501 !strconcat(name, " $src"), []>; 1502 def _f32 : ILFormat<(outs), (ins R600_Reg32:$src), 1503 !strconcat(name, " $src"), []>; 1504 } 1505 // Only scalar types should generate flow control 1506 multiclass BranchInstr2<string name> { 1507 def _i32 : ILFormat<(outs), (ins R600_Reg32:$src0, R600_Reg32:$src1), 1508 !strconcat(name, " $src0, $src1"), []>; 1509 def _f32 : ILFormat<(outs), (ins R600_Reg32:$src0, R600_Reg32:$src1), 1510 !strconcat(name, " $src0, $src1"), []>; 1511 } 1512 1513 //===---------------------------------------------------------------------===// 1514 // Custom Inserter for Branches and returns, this eventually will be a 1515 // separate pass 1516 //===---------------------------------------------------------------------===// 1517 let isTerminator = 1, usesCustomInserter = 1, isBranch = 1, isBarrier = 1 in { 1518 def BRANCH : ILFormat<(outs), (ins brtarget:$target), 1519 "; Pseudo unconditional branch instruction", 1520 [(br bb:$target)]>; 1521 defm BRANCH_COND : BranchConditional<IL_brcond, R600_Reg32, R600_Reg32>; 1522 } 1523 1524 //===---------------------------------------------------------------------===// 1525 // Return instruction 1526 //===---------------------------------------------------------------------===// 1527 let isTerminator = 1, isReturn = 1, hasCtrlDep = 1, 1528 usesCustomInserter = 1 in { 1529 def RETURN : ILFormat<(outs), (ins variable_ops), 1530 "RETURN", [(IL_retflag)]>; 1531 } 1532 1533 //===----------------------------------------------------------------------===// 1534 // Branch Instructions 1535 //===----------------------------------------------------------------------===// 1536 1537 def IF_PREDICATE_SET : ILFormat<(outs), (ins R600_Reg32:$src), 1538 "IF_PREDICATE_SET $src", []>; 1539 1540 let isTerminator=1 in { 1541 def BREAK : ILFormat< (outs), (ins), 1542 "BREAK", []>; 1543 def CONTINUE : ILFormat< (outs), (ins), 1544 "CONTINUE", []>; 1545 def DEFAULT : ILFormat< (outs), (ins), 1546 "DEFAULT", []>; 1547 def ELSE : ILFormat< (outs), (ins), 1548 "ELSE", []>; 1549 def ENDSWITCH : ILFormat< (outs), (ins), 1550 "ENDSWITCH", []>; 1551 def ENDMAIN : ILFormat< (outs), (ins), 1552 "ENDMAIN", []>; 1553 def END : ILFormat< (outs), (ins), 1554 "END", []>; 1555 def ENDFUNC : ILFormat< (outs), (ins), 1556 "ENDFUNC", []>; 1557 def ENDIF : ILFormat< (outs), (ins), 1558 "ENDIF", []>; 1559 def WHILELOOP : ILFormat< (outs), (ins), 1560 "WHILE", []>; 1561 def ENDLOOP : ILFormat< (outs), (ins), 1562 "ENDLOOP", []>; 1563 def FUNC : ILFormat< (outs), (ins), 1564 "FUNC", []>; 1565 def RETDYN : ILFormat< (outs), (ins), 1566 "RET_DYN", []>; 1567 // This opcode has custom swizzle pattern encoded in Swizzle Encoder 1568 defm IF_LOGICALNZ : BranchInstr<"IF_LOGICALNZ">; 1569 // This opcode has custom swizzle pattern encoded in Swizzle Encoder 1570 defm IF_LOGICALZ : BranchInstr<"IF_LOGICALZ">; 1571 // This opcode has custom swizzle pattern encoded in Swizzle Encoder 1572 defm BREAK_LOGICALNZ : BranchInstr<"BREAK_LOGICALNZ">; 1573 // This opcode has custom swizzle pattern encoded in Swizzle Encoder 1574 defm BREAK_LOGICALZ : BranchInstr<"BREAK_LOGICALZ">; 1575 // This opcode has custom swizzle pattern encoded in Swizzle Encoder 1576 defm CONTINUE_LOGICALNZ : BranchInstr<"CONTINUE_LOGICALNZ">; 1577 // This opcode has custom swizzle pattern encoded in Swizzle Encoder 1578 defm CONTINUE_LOGICALZ : BranchInstr<"CONTINUE_LOGICALZ">; 1579 defm IFC : BranchInstr2<"IFC">; 1580 defm BREAKC : BranchInstr2<"BREAKC">; 1581 defm CONTINUEC : BranchInstr2<"CONTINUEC">; 1582 } 1583 1584 //===----------------------------------------------------------------------===// 1585 // Indirect addressing pseudo instructions 1586 //===----------------------------------------------------------------------===// 1587 1588 let isPseudo = 1 in { 1589 1590 class ExtractVertical <RegisterClass vec_rc> : InstR600 < 1591 (outs R600_Reg32:$dst), 1592 (ins vec_rc:$vec, R600_Reg32:$index), "", 1593 [], 1594 AnyALU 1595 >; 1596 1597 let Constraints = "$dst = $vec" in { 1598 1599 class InsertVertical <RegisterClass vec_rc> : InstR600 < 1600 (outs vec_rc:$dst), 1601 (ins vec_rc:$vec, R600_Reg32:$value, R600_Reg32:$index), "", 1602 [], 1603 AnyALU 1604 >; 1605 1606 } // End Constraints = "$dst = $vec" 1607 1608 } // End isPseudo = 1 1609 1610 def R600_EXTRACT_ELT_V2 : ExtractVertical <R600_Reg64Vertical>; 1611 def R600_EXTRACT_ELT_V4 : ExtractVertical <R600_Reg128Vertical>; 1612 1613 def R600_INSERT_ELT_V2 : InsertVertical <R600_Reg64Vertical>; 1614 def R600_INSERT_ELT_V4 : InsertVertical <R600_Reg128Vertical>; 1615 1616 class ExtractVerticalPat <Instruction inst, ValueType vec_ty, 1617 ValueType scalar_ty> : Pat < 1618 (scalar_ty (extractelt vec_ty:$vec, i32:$index)), 1619 (inst $vec, $index) 1620 >; 1621 1622 def : ExtractVerticalPat <R600_EXTRACT_ELT_V2, v2i32, i32>; 1623 def : ExtractVerticalPat <R600_EXTRACT_ELT_V2, v2f32, f32>; 1624 def : ExtractVerticalPat <R600_EXTRACT_ELT_V4, v4i32, i32>; 1625 def : ExtractVerticalPat <R600_EXTRACT_ELT_V4, v4f32, f32>; 1626 1627 class InsertVerticalPat <Instruction inst, ValueType vec_ty, 1628 ValueType scalar_ty> : Pat < 1629 (vec_ty (insertelt vec_ty:$vec, scalar_ty:$value, i32:$index)), 1630 (inst $vec, $value, $index) 1631 >; 1632 1633 def : InsertVerticalPat <R600_INSERT_ELT_V2, v2i32, i32>; 1634 def : InsertVerticalPat <R600_INSERT_ELT_V2, v2f32, f32>; 1635 def : InsertVerticalPat <R600_INSERT_ELT_V4, v4i32, i32>; 1636 def : InsertVerticalPat <R600_INSERT_ELT_V4, v4f32, f32>; 1637 1638 //===----------------------------------------------------------------------===// 1639 // ISel Patterns 1640 //===----------------------------------------------------------------------===// 1641 1642 // CND*_INT Pattterns for f32 True / False values 1643 1644 class CND_INT_f32 <InstR600 cnd, CondCode cc> : Pat < 1645 (selectcc i32:$src0, 0, f32:$src1, f32:$src2, cc), 1646 (cnd $src0, $src1, $src2) 1647 >; 1648 1649 def : CND_INT_f32 <CNDE_INT, SETEQ>; 1650 def : CND_INT_f32 <CNDGT_INT, SETGT>; 1651 def : CND_INT_f32 <CNDGE_INT, SETGE>; 1652 1653 //CNDGE_INT extra pattern 1654 def : Pat < 1655 (selectcc i32:$src0, -1, i32:$src1, i32:$src2, COND_SGT), 1656 (CNDGE_INT $src0, $src1, $src2) 1657 >; 1658 1659 // KIL Patterns 1660 def KILP : Pat < 1661 (int_AMDGPU_kilp), 1662 (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO))) 1663 >; 1664 1665 def KIL : Pat < 1666 (int_AMDGPU_kill f32:$src0), 1667 (MASK_WRITE (KILLGT (f32 ZERO), $src0)) 1668 >; 1669 1670 def : Extract_Element <f32, v4f32, 0, sub0>; 1671 def : Extract_Element <f32, v4f32, 1, sub1>; 1672 def : Extract_Element <f32, v4f32, 2, sub2>; 1673 def : Extract_Element <f32, v4f32, 3, sub3>; 1674 1675 def : Insert_Element <f32, v4f32, 0, sub0>; 1676 def : Insert_Element <f32, v4f32, 1, sub1>; 1677 def : Insert_Element <f32, v4f32, 2, sub2>; 1678 def : Insert_Element <f32, v4f32, 3, sub3>; 1679 1680 def : Extract_Element <i32, v4i32, 0, sub0>; 1681 def : Extract_Element <i32, v4i32, 1, sub1>; 1682 def : Extract_Element <i32, v4i32, 2, sub2>; 1683 def : Extract_Element <i32, v4i32, 3, sub3>; 1684 1685 def : Insert_Element <i32, v4i32, 0, sub0>; 1686 def : Insert_Element <i32, v4i32, 1, sub1>; 1687 def : Insert_Element <i32, v4i32, 2, sub2>; 1688 def : Insert_Element <i32, v4i32, 3, sub3>; 1689 1690 def : Extract_Element <f32, v2f32, 0, sub0>; 1691 def : Extract_Element <f32, v2f32, 1, sub1>; 1692 1693 def : Insert_Element <f32, v2f32, 0, sub0>; 1694 def : Insert_Element <f32, v2f32, 1, sub1>; 1695 1696 def : Extract_Element <i32, v2i32, 0, sub0>; 1697 def : Extract_Element <i32, v2i32, 1, sub1>; 1698 1699 def : Insert_Element <i32, v2i32, 0, sub0>; 1700 def : Insert_Element <i32, v2i32, 1, sub1>; 1701 1702 // bitconvert patterns 1703 1704 def : BitConvert <i32, f32, R600_Reg32>; 1705 def : BitConvert <f32, i32, R600_Reg32>; 1706 def : BitConvert <v2f32, v2i32, R600_Reg64>; 1707 def : BitConvert <v2i32, v2f32, R600_Reg64>; 1708 def : BitConvert <v4f32, v4i32, R600_Reg128>; 1709 def : BitConvert <v4i32, v4f32, R600_Reg128>; 1710 1711 // DWORDADDR pattern 1712 def : DwordAddrPat <i32, R600_Reg32>; 1713 1714 } // End isR600toCayman Predicate 1715 1716 let Predicates = [isR600] in { 1717 // Intrinsic patterns 1718 defm : Expand24IBitOps<MULLO_INT_r600, ADD_INT>; 1719 defm : Expand24UBitOps<MULLO_UINT_r600, ADD_INT>; 1720 } // End isR600 1721 1722 def getLDSNoRetOp : InstrMapping { 1723 let FilterClass = "R600_LDS_1A1D"; 1724 let RowFields = ["BaseOp"]; 1725 let ColFields = ["DisableEncoding"]; 1726 let KeyCol = ["$dst"]; 1727 let ValueCols = [[""""]]; 1728 } 1729
