1 //===-- Sparc.td - Describe the Sparc Target Machine -------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // 11 //===----------------------------------------------------------------------===// 12 13 //===----------------------------------------------------------------------===// 14 // Target-independent interfaces which we are implementing 15 //===----------------------------------------------------------------------===// 16 17 include "llvm/Target/Target.td" 18 19 //===----------------------------------------------------------------------===// 20 // SPARC Subtarget features. 21 // 22 23 def FeatureV9 24 : SubtargetFeature<"v9", "IsV9", "true", 25 "Enable SPARC-V9 instructions">; 26 def FeatureV8Deprecated 27 : SubtargetFeature<"deprecated-v8", "V8DeprecatedInsts", "true", 28 "Enable deprecated V8 instructions in V9 mode">; 29 def FeatureVIS 30 : SubtargetFeature<"vis", "IsVIS", "true", 31 "Enable UltraSPARC Visual Instruction Set extensions">; 32 def FeatureVIS2 33 : SubtargetFeature<"vis2", "IsVIS2", "true", 34 "Enable Visual Instruction Set extensions II">; 35 def FeatureVIS3 36 : SubtargetFeature<"vis3", "IsVIS3", "true", 37 "Enable Visual Instruction Set extensions III">; 38 39 def FeatureHardQuad 40 : SubtargetFeature<"hard-quad-float", "HasHardQuad", "true", 41 "Enable quad-word floating point instructions">; 42 43 def UsePopc : SubtargetFeature<"popc", "UsePopc", "true", 44 "Use the popc (population count) instruction">; 45 46 //===----------------------------------------------------------------------===// 47 // Register File, Calling Conv, Instruction Descriptions 48 //===----------------------------------------------------------------------===// 49 50 include "SparcRegisterInfo.td" 51 include "SparcCallingConv.td" 52 include "SparcInstrInfo.td" 53 54 def SparcInstrInfo : InstrInfo; 55 56 def SparcAsmParser : AsmParser { 57 bit ShouldEmitMatchRegisterName = 0; 58 } 59 60 //===----------------------------------------------------------------------===// 61 // SPARC processors supported. 62 //===----------------------------------------------------------------------===// 63 64 class Proc<string Name, list<SubtargetFeature> Features> 65 : Processor<Name, NoItineraries, Features>; 66 67 def : Proc<"generic", []>; 68 def : Proc<"v7", []>; 69 def : Proc<"v8", []>; 70 def : Proc<"supersparc", []>; 71 def : Proc<"sparclite", []>; 72 def : Proc<"f934", []>; 73 def : Proc<"hypersparc", []>; 74 def : Proc<"sparclite86x", []>; 75 def : Proc<"sparclet", []>; 76 def : Proc<"tsc701", []>; 77 def : Proc<"v9", [FeatureV9]>; 78 def : Proc<"ultrasparc", [FeatureV9, FeatureV8Deprecated, FeatureVIS]>; 79 def : Proc<"ultrasparc3", [FeatureV9, FeatureV8Deprecated, FeatureVIS, 80 FeatureVIS2]>; 81 def : Proc<"niagara", [FeatureV9, FeatureV8Deprecated, FeatureVIS, 82 FeatureVIS2]>; 83 def : Proc<"niagara2", [FeatureV9, FeatureV8Deprecated, UsePopc, 84 FeatureVIS, FeatureVIS2]>; 85 def : Proc<"niagara3", [FeatureV9, FeatureV8Deprecated, UsePopc, 86 FeatureVIS, FeatureVIS2]>; 87 def : Proc<"niagara4", [FeatureV9, FeatureV8Deprecated, UsePopc, 88 FeatureVIS, FeatureVIS2, FeatureVIS3]>; 89 90 91 //===----------------------------------------------------------------------===// 92 // Declare the target which we are implementing 93 //===----------------------------------------------------------------------===// 94 95 def Sparc : Target { 96 // Pull in Instruction Info: 97 let InstructionSet = SparcInstrInfo; 98 let AssemblyParsers = [SparcAsmParser]; 99 } 100
