1 //===-- SparcRegisterInfo.td - Sparc Register defs ---------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 //===----------------------------------------------------------------------===// 11 // Declarations that describe the Sparc register file 12 //===----------------------------------------------------------------------===// 13 14 class SparcReg<bits<16> Enc, string n> : Register<n> { 15 let HWEncoding = Enc; 16 let Namespace = "SP"; 17 } 18 19 class SparcCtrlReg<bits<16> Enc, string n>: Register<n> { 20 let HWEncoding = Enc; 21 let Namespace = "SP"; 22 } 23 24 let Namespace = "SP" in { 25 def sub_even : SubRegIndex<32>; 26 def sub_odd : SubRegIndex<32, 32>; 27 def sub_even64 : SubRegIndex<64>; 28 def sub_odd64 : SubRegIndex<64, 64>; 29 } 30 31 // Registers are identified with 5-bit ID numbers. 32 // Ri - 32-bit integer registers 33 class Ri<bits<16> Enc, string n> : SparcReg<Enc, n>; 34 35 // Rf - 32-bit floating-point registers 36 class Rf<bits<16> Enc, string n> : SparcReg<Enc, n>; 37 38 // Rd - Slots in the FP register file for 64-bit floating-point values. 39 class Rd<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> { 40 let SubRegs = subregs; 41 let SubRegIndices = [sub_even, sub_odd]; 42 let CoveredBySubRegs = 1; 43 } 44 45 // Rq - Slots in the FP register file for 128-bit floating-point values. 46 class Rq<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> { 47 let SubRegs = subregs; 48 let SubRegIndices = [sub_even64, sub_odd64]; 49 let CoveredBySubRegs = 1; 50 } 51 52 // Control Registers 53 def ICC : SparcCtrlReg<0, "ICC">; // This represents icc and xcc in 64-bit code. 54 foreach I = 0-3 in 55 def FCC#I : SparcCtrlReg<I, "FCC"#I>; 56 57 // Y register 58 def Y : SparcCtrlReg<0, "Y">, DwarfRegNum<[64]>; 59 60 // Integer registers 61 def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>; 62 def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>; 63 def G2 : Ri< 2, "G2">, DwarfRegNum<[2]>; 64 def G3 : Ri< 3, "G3">, DwarfRegNum<[3]>; 65 def G4 : Ri< 4, "G4">, DwarfRegNum<[4]>; 66 def G5 : Ri< 5, "G5">, DwarfRegNum<[5]>; 67 def G6 : Ri< 6, "G6">, DwarfRegNum<[6]>; 68 def G7 : Ri< 7, "G7">, DwarfRegNum<[7]>; 69 def O0 : Ri< 8, "O0">, DwarfRegNum<[8]>; 70 def O1 : Ri< 9, "O1">, DwarfRegNum<[9]>; 71 def O2 : Ri<10, "O2">, DwarfRegNum<[10]>; 72 def O3 : Ri<11, "O3">, DwarfRegNum<[11]>; 73 def O4 : Ri<12, "O4">, DwarfRegNum<[12]>; 74 def O5 : Ri<13, "O5">, DwarfRegNum<[13]>; 75 def O6 : Ri<14, "SP">, DwarfRegNum<[14]>; 76 def O7 : Ri<15, "O7">, DwarfRegNum<[15]>; 77 def L0 : Ri<16, "L0">, DwarfRegNum<[16]>; 78 def L1 : Ri<17, "L1">, DwarfRegNum<[17]>; 79 def L2 : Ri<18, "L2">, DwarfRegNum<[18]>; 80 def L3 : Ri<19, "L3">, DwarfRegNum<[19]>; 81 def L4 : Ri<20, "L4">, DwarfRegNum<[20]>; 82 def L5 : Ri<21, "L5">, DwarfRegNum<[21]>; 83 def L6 : Ri<22, "L6">, DwarfRegNum<[22]>; 84 def L7 : Ri<23, "L7">, DwarfRegNum<[23]>; 85 def I0 : Ri<24, "I0">, DwarfRegNum<[24]>; 86 def I1 : Ri<25, "I1">, DwarfRegNum<[25]>; 87 def I2 : Ri<26, "I2">, DwarfRegNum<[26]>; 88 def I3 : Ri<27, "I3">, DwarfRegNum<[27]>; 89 def I4 : Ri<28, "I4">, DwarfRegNum<[28]>; 90 def I5 : Ri<29, "I5">, DwarfRegNum<[29]>; 91 def I6 : Ri<30, "FP">, DwarfRegNum<[30]>; 92 def I7 : Ri<31, "I7">, DwarfRegNum<[31]>; 93 94 // Floating-point registers 95 def F0 : Rf< 0, "F0">, DwarfRegNum<[32]>; 96 def F1 : Rf< 1, "F1">, DwarfRegNum<[33]>; 97 def F2 : Rf< 2, "F2">, DwarfRegNum<[34]>; 98 def F3 : Rf< 3, "F3">, DwarfRegNum<[35]>; 99 def F4 : Rf< 4, "F4">, DwarfRegNum<[36]>; 100 def F5 : Rf< 5, "F5">, DwarfRegNum<[37]>; 101 def F6 : Rf< 6, "F6">, DwarfRegNum<[38]>; 102 def F7 : Rf< 7, "F7">, DwarfRegNum<[39]>; 103 def F8 : Rf< 8, "F8">, DwarfRegNum<[40]>; 104 def F9 : Rf< 9, "F9">, DwarfRegNum<[41]>; 105 def F10 : Rf<10, "F10">, DwarfRegNum<[42]>; 106 def F11 : Rf<11, "F11">, DwarfRegNum<[43]>; 107 def F12 : Rf<12, "F12">, DwarfRegNum<[44]>; 108 def F13 : Rf<13, "F13">, DwarfRegNum<[45]>; 109 def F14 : Rf<14, "F14">, DwarfRegNum<[46]>; 110 def F15 : Rf<15, "F15">, DwarfRegNum<[47]>; 111 def F16 : Rf<16, "F16">, DwarfRegNum<[48]>; 112 def F17 : Rf<17, "F17">, DwarfRegNum<[49]>; 113 def F18 : Rf<18, "F18">, DwarfRegNum<[50]>; 114 def F19 : Rf<19, "F19">, DwarfRegNum<[51]>; 115 def F20 : Rf<20, "F20">, DwarfRegNum<[52]>; 116 def F21 : Rf<21, "F21">, DwarfRegNum<[53]>; 117 def F22 : Rf<22, "F22">, DwarfRegNum<[54]>; 118 def F23 : Rf<23, "F23">, DwarfRegNum<[55]>; 119 def F24 : Rf<24, "F24">, DwarfRegNum<[56]>; 120 def F25 : Rf<25, "F25">, DwarfRegNum<[57]>; 121 def F26 : Rf<26, "F26">, DwarfRegNum<[58]>; 122 def F27 : Rf<27, "F27">, DwarfRegNum<[59]>; 123 def F28 : Rf<28, "F28">, DwarfRegNum<[60]>; 124 def F29 : Rf<29, "F29">, DwarfRegNum<[61]>; 125 def F30 : Rf<30, "F30">, DwarfRegNum<[62]>; 126 def F31 : Rf<31, "F31">, DwarfRegNum<[63]>; 127 128 // Aliases of the F* registers used to hold 64-bit fp values (doubles) 129 def D0 : Rd< 0, "F0", [F0, F1]>, DwarfRegNum<[72]>; 130 def D1 : Rd< 2, "F2", [F2, F3]>, DwarfRegNum<[73]>; 131 def D2 : Rd< 4, "F4", [F4, F5]>, DwarfRegNum<[74]>; 132 def D3 : Rd< 6, "F6", [F6, F7]>, DwarfRegNum<[75]>; 133 def D4 : Rd< 8, "F8", [F8, F9]>, DwarfRegNum<[76]>; 134 def D5 : Rd<10, "F10", [F10, F11]>, DwarfRegNum<[77]>; 135 def D6 : Rd<12, "F12", [F12, F13]>, DwarfRegNum<[78]>; 136 def D7 : Rd<14, "F14", [F14, F15]>, DwarfRegNum<[79]>; 137 def D8 : Rd<16, "F16", [F16, F17]>, DwarfRegNum<[80]>; 138 def D9 : Rd<18, "F18", [F18, F19]>, DwarfRegNum<[81]>; 139 def D10 : Rd<20, "F20", [F20, F21]>, DwarfRegNum<[82]>; 140 def D11 : Rd<22, "F22", [F22, F23]>, DwarfRegNum<[83]>; 141 def D12 : Rd<24, "F24", [F24, F25]>, DwarfRegNum<[84]>; 142 def D13 : Rd<26, "F26", [F26, F27]>, DwarfRegNum<[85]>; 143 def D14 : Rd<28, "F28", [F28, F29]>, DwarfRegNum<[86]>; 144 def D15 : Rd<30, "F30", [F30, F31]>, DwarfRegNum<[87]>; 145 146 // Unaliased double precision floating point registers. 147 // FIXME: Define DwarfRegNum for these registers. 148 def D16 : SparcReg< 1, "F32">; 149 def D17 : SparcReg< 3, "F34">; 150 def D18 : SparcReg< 5, "F36">; 151 def D19 : SparcReg< 7, "F38">; 152 def D20 : SparcReg< 9, "F40">; 153 def D21 : SparcReg<11, "F42">; 154 def D22 : SparcReg<13, "F44">; 155 def D23 : SparcReg<15, "F46">; 156 def D24 : SparcReg<17, "F48">; 157 def D25 : SparcReg<19, "F50">; 158 def D26 : SparcReg<21, "F52">; 159 def D27 : SparcReg<23, "F54">; 160 def D28 : SparcReg<25, "F56">; 161 def D29 : SparcReg<27, "F58">; 162 def D30 : SparcReg<29, "F60">; 163 def D31 : SparcReg<31, "F62">; 164 165 // Aliases of the F* registers used to hold 128-bit for values (long doubles). 166 def Q0 : Rq< 0, "F0", [D0, D1]>; 167 def Q1 : Rq< 4, "F4", [D2, D3]>; 168 def Q2 : Rq< 8, "F8", [D4, D5]>; 169 def Q3 : Rq<12, "F12", [D6, D7]>; 170 def Q4 : Rq<16, "F16", [D8, D9]>; 171 def Q5 : Rq<20, "F20", [D10, D11]>; 172 def Q6 : Rq<24, "F24", [D12, D13]>; 173 def Q7 : Rq<28, "F28", [D14, D15]>; 174 def Q8 : Rq< 1, "F32", [D16, D17]>; 175 def Q9 : Rq< 5, "F36", [D18, D19]>; 176 def Q10 : Rq< 9, "F40", [D20, D21]>; 177 def Q11 : Rq<13, "F44", [D22, D23]>; 178 def Q12 : Rq<17, "F48", [D24, D25]>; 179 def Q13 : Rq<21, "F52", [D26, D27]>; 180 def Q14 : Rq<25, "F56", [D28, D29]>; 181 def Q15 : Rq<29, "F60", [D30, D31]>; 182 183 // Register classes. 184 // 185 // FIXME: the register order should be defined in terms of the preferred 186 // allocation order... 187 // 188 // This register class should not be used to hold i64 values, use the I64Regs 189 // register class for that. The i64 type is included here to allow i64 patterns 190 // using the integer instructions. 191 def IntRegs : RegisterClass<"SP", [i32, i64], 32, 192 (add (sequence "I%u", 0, 7), 193 (sequence "G%u", 0, 7), 194 (sequence "L%u", 0, 7), 195 (sequence "O%u", 0, 7))>; 196 197 // Register class for 64-bit mode, with a 64-bit spill slot size. 198 // These are the same as the 32-bit registers, so TableGen will consider this 199 // to be a sub-class of IntRegs. That works out because requiring a 64-bit 200 // spill slot is a stricter constraint than only requiring a 32-bit spill slot. 201 def I64Regs : RegisterClass<"SP", [i64], 64, (add IntRegs)>; 202 203 // Floating point register classes. 204 def FPRegs : RegisterClass<"SP", [f32], 32, (sequence "F%u", 0, 31)>; 205 206 def DFPRegs : RegisterClass<"SP", [f64], 64, (sequence "D%u", 0, 31)>; 207 208 def QFPRegs : RegisterClass<"SP", [f128], 128, (sequence "Q%u", 0, 15)>; 209 210 // Floating point control register classes. 211 def FCCRegs : RegisterClass<"SP", [i1], 1, (sequence "FCC%u", 0, 3)>; 212
