1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the X86 implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "X86InstrInfo.h" 15 #include "X86.h" 16 #include "X86InstrBuilder.h" 17 #include "X86MachineFunctionInfo.h" 18 #include "X86Subtarget.h" 19 #include "X86TargetMachine.h" 20 #include "llvm/ADT/STLExtras.h" 21 #include "llvm/CodeGen/LiveVariables.h" 22 #include "llvm/CodeGen/MachineConstantPool.h" 23 #include "llvm/CodeGen/MachineDominators.h" 24 #include "llvm/CodeGen/MachineFrameInfo.h" 25 #include "llvm/CodeGen/MachineInstrBuilder.h" 26 #include "llvm/CodeGen/MachineRegisterInfo.h" 27 #include "llvm/CodeGen/StackMaps.h" 28 #include "llvm/IR/DerivedTypes.h" 29 #include "llvm/IR/LLVMContext.h" 30 #include "llvm/MC/MCAsmInfo.h" 31 #include "llvm/MC/MCExpr.h" 32 #include "llvm/MC/MCInst.h" 33 #include "llvm/Support/CommandLine.h" 34 #include "llvm/Support/Debug.h" 35 #include "llvm/Support/ErrorHandling.h" 36 #include "llvm/Support/raw_ostream.h" 37 #include "llvm/Target/TargetOptions.h" 38 #include <limits> 39 40 using namespace llvm; 41 42 #define DEBUG_TYPE "x86-instr-info" 43 44 #define GET_INSTRINFO_CTOR_DTOR 45 #include "X86GenInstrInfo.inc" 46 47 static cl::opt<bool> 48 NoFusing("disable-spill-fusing", 49 cl::desc("Disable fusing of spill code into instructions")); 50 static cl::opt<bool> 51 PrintFailedFusing("print-failed-fuse-candidates", 52 cl::desc("Print instructions that the allocator wants to" 53 " fuse, but the X86 backend currently can't"), 54 cl::Hidden); 55 static cl::opt<bool> 56 ReMatPICStubLoad("remat-pic-stub-load", 57 cl::desc("Re-materialize load from stub in PIC mode"), 58 cl::init(false), cl::Hidden); 59 60 enum { 61 // Select which memory operand is being unfolded. 62 // (stored in bits 0 - 3) 63 TB_INDEX_0 = 0, 64 TB_INDEX_1 = 1, 65 TB_INDEX_2 = 2, 66 TB_INDEX_3 = 3, 67 TB_INDEX_MASK = 0xf, 68 69 // Do not insert the reverse map (MemOp -> RegOp) into the table. 70 // This may be needed because there is a many -> one mapping. 71 TB_NO_REVERSE = 1 << 4, 72 73 // Do not insert the forward map (RegOp -> MemOp) into the table. 74 // This is needed for Native Client, which prohibits branch 75 // instructions from using a memory operand. 76 TB_NO_FORWARD = 1 << 5, 77 78 TB_FOLDED_LOAD = 1 << 6, 79 TB_FOLDED_STORE = 1 << 7, 80 81 // Minimum alignment required for load/store. 82 // Used for RegOp->MemOp conversion. 83 // (stored in bits 8 - 15) 84 TB_ALIGN_SHIFT = 8, 85 TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT, 86 TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT, 87 TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT, 88 TB_ALIGN_64 = 64 << TB_ALIGN_SHIFT, 89 TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT 90 }; 91 92 struct X86OpTblEntry { 93 uint16_t RegOp; 94 uint16_t MemOp; 95 uint16_t Flags; 96 }; 97 98 // Pin the vtable to this file. 99 void X86InstrInfo::anchor() {} 100 101 X86InstrInfo::X86InstrInfo(X86Subtarget &STI) 102 : X86GenInstrInfo( 103 (STI.is64Bit() ? X86::ADJCALLSTACKDOWN64 : X86::ADJCALLSTACKDOWN32), 104 (STI.is64Bit() ? X86::ADJCALLSTACKUP64 : X86::ADJCALLSTACKUP32)), 105 Subtarget(STI), RI(STI) { 106 107 static const X86OpTblEntry OpTbl2Addr[] = { 108 { X86::ADC32ri, X86::ADC32mi, 0 }, 109 { X86::ADC32ri8, X86::ADC32mi8, 0 }, 110 { X86::ADC32rr, X86::ADC32mr, 0 }, 111 { X86::ADC64ri32, X86::ADC64mi32, 0 }, 112 { X86::ADC64ri8, X86::ADC64mi8, 0 }, 113 { X86::ADC64rr, X86::ADC64mr, 0 }, 114 { X86::ADD16ri, X86::ADD16mi, 0 }, 115 { X86::ADD16ri8, X86::ADD16mi8, 0 }, 116 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE }, 117 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE }, 118 { X86::ADD16rr, X86::ADD16mr, 0 }, 119 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE }, 120 { X86::ADD32ri, X86::ADD32mi, 0 }, 121 { X86::ADD32ri8, X86::ADD32mi8, 0 }, 122 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE }, 123 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE }, 124 { X86::ADD32rr, X86::ADD32mr, 0 }, 125 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE }, 126 { X86::ADD64ri32, X86::ADD64mi32, 0 }, 127 { X86::ADD64ri8, X86::ADD64mi8, 0 }, 128 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE }, 129 { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE }, 130 { X86::ADD64rr, X86::ADD64mr, 0 }, 131 { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE }, 132 { X86::ADD8ri, X86::ADD8mi, 0 }, 133 { X86::ADD8rr, X86::ADD8mr, 0 }, 134 { X86::AND16ri, X86::AND16mi, 0 }, 135 { X86::AND16ri8, X86::AND16mi8, 0 }, 136 { X86::AND16rr, X86::AND16mr, 0 }, 137 { X86::AND32ri, X86::AND32mi, 0 }, 138 { X86::AND32ri8, X86::AND32mi8, 0 }, 139 { X86::AND32rr, X86::AND32mr, 0 }, 140 { X86::AND64ri32, X86::AND64mi32, 0 }, 141 { X86::AND64ri8, X86::AND64mi8, 0 }, 142 { X86::AND64rr, X86::AND64mr, 0 }, 143 { X86::AND8ri, X86::AND8mi, 0 }, 144 { X86::AND8rr, X86::AND8mr, 0 }, 145 { X86::DEC16r, X86::DEC16m, 0 }, 146 { X86::DEC32r, X86::DEC32m, 0 }, 147 { X86::DEC64_16r, X86::DEC64_16m, 0 }, 148 { X86::DEC64_32r, X86::DEC64_32m, 0 }, 149 { X86::DEC64r, X86::DEC64m, 0 }, 150 { X86::DEC8r, X86::DEC8m, 0 }, 151 { X86::INC16r, X86::INC16m, 0 }, 152 { X86::INC32r, X86::INC32m, 0 }, 153 { X86::INC64_16r, X86::INC64_16m, 0 }, 154 { X86::INC64_32r, X86::INC64_32m, 0 }, 155 { X86::INC64r, X86::INC64m, 0 }, 156 { X86::INC8r, X86::INC8m, 0 }, 157 { X86::NEG16r, X86::NEG16m, 0 }, 158 { X86::NEG32r, X86::NEG32m, 0 }, 159 { X86::NEG64r, X86::NEG64m, 0 }, 160 { X86::NEG8r, X86::NEG8m, 0 }, 161 { X86::NOT16r, X86::NOT16m, 0 }, 162 { X86::NOT32r, X86::NOT32m, 0 }, 163 { X86::NOT64r, X86::NOT64m, 0 }, 164 { X86::NOT8r, X86::NOT8m, 0 }, 165 { X86::OR16ri, X86::OR16mi, 0 }, 166 { X86::OR16ri8, X86::OR16mi8, 0 }, 167 { X86::OR16rr, X86::OR16mr, 0 }, 168 { X86::OR32ri, X86::OR32mi, 0 }, 169 { X86::OR32ri8, X86::OR32mi8, 0 }, 170 { X86::OR32rr, X86::OR32mr, 0 }, 171 { X86::OR64ri32, X86::OR64mi32, 0 }, 172 { X86::OR64ri8, X86::OR64mi8, 0 }, 173 { X86::OR64rr, X86::OR64mr, 0 }, 174 { X86::OR8ri, X86::OR8mi, 0 }, 175 { X86::OR8rr, X86::OR8mr, 0 }, 176 { X86::ROL16r1, X86::ROL16m1, 0 }, 177 { X86::ROL16rCL, X86::ROL16mCL, 0 }, 178 { X86::ROL16ri, X86::ROL16mi, 0 }, 179 { X86::ROL32r1, X86::ROL32m1, 0 }, 180 { X86::ROL32rCL, X86::ROL32mCL, 0 }, 181 { X86::ROL32ri, X86::ROL32mi, 0 }, 182 { X86::ROL64r1, X86::ROL64m1, 0 }, 183 { X86::ROL64rCL, X86::ROL64mCL, 0 }, 184 { X86::ROL64ri, X86::ROL64mi, 0 }, 185 { X86::ROL8r1, X86::ROL8m1, 0 }, 186 { X86::ROL8rCL, X86::ROL8mCL, 0 }, 187 { X86::ROL8ri, X86::ROL8mi, 0 }, 188 { X86::ROR16r1, X86::ROR16m1, 0 }, 189 { X86::ROR16rCL, X86::ROR16mCL, 0 }, 190 { X86::ROR16ri, X86::ROR16mi, 0 }, 191 { X86::ROR32r1, X86::ROR32m1, 0 }, 192 { X86::ROR32rCL, X86::ROR32mCL, 0 }, 193 { X86::ROR32ri, X86::ROR32mi, 0 }, 194 { X86::ROR64r1, X86::ROR64m1, 0 }, 195 { X86::ROR64rCL, X86::ROR64mCL, 0 }, 196 { X86::ROR64ri, X86::ROR64mi, 0 }, 197 { X86::ROR8r1, X86::ROR8m1, 0 }, 198 { X86::ROR8rCL, X86::ROR8mCL, 0 }, 199 { X86::ROR8ri, X86::ROR8mi, 0 }, 200 { X86::SAR16r1, X86::SAR16m1, 0 }, 201 { X86::SAR16rCL, X86::SAR16mCL, 0 }, 202 { X86::SAR16ri, X86::SAR16mi, 0 }, 203 { X86::SAR32r1, X86::SAR32m1, 0 }, 204 { X86::SAR32rCL, X86::SAR32mCL, 0 }, 205 { X86::SAR32ri, X86::SAR32mi, 0 }, 206 { X86::SAR64r1, X86::SAR64m1, 0 }, 207 { X86::SAR64rCL, X86::SAR64mCL, 0 }, 208 { X86::SAR64ri, X86::SAR64mi, 0 }, 209 { X86::SAR8r1, X86::SAR8m1, 0 }, 210 { X86::SAR8rCL, X86::SAR8mCL, 0 }, 211 { X86::SAR8ri, X86::SAR8mi, 0 }, 212 { X86::SBB32ri, X86::SBB32mi, 0 }, 213 { X86::SBB32ri8, X86::SBB32mi8, 0 }, 214 { X86::SBB32rr, X86::SBB32mr, 0 }, 215 { X86::SBB64ri32, X86::SBB64mi32, 0 }, 216 { X86::SBB64ri8, X86::SBB64mi8, 0 }, 217 { X86::SBB64rr, X86::SBB64mr, 0 }, 218 { X86::SHL16rCL, X86::SHL16mCL, 0 }, 219 { X86::SHL16ri, X86::SHL16mi, 0 }, 220 { X86::SHL32rCL, X86::SHL32mCL, 0 }, 221 { X86::SHL32ri, X86::SHL32mi, 0 }, 222 { X86::SHL64rCL, X86::SHL64mCL, 0 }, 223 { X86::SHL64ri, X86::SHL64mi, 0 }, 224 { X86::SHL8rCL, X86::SHL8mCL, 0 }, 225 { X86::SHL8ri, X86::SHL8mi, 0 }, 226 { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 }, 227 { X86::SHLD16rri8, X86::SHLD16mri8, 0 }, 228 { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 }, 229 { X86::SHLD32rri8, X86::SHLD32mri8, 0 }, 230 { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 }, 231 { X86::SHLD64rri8, X86::SHLD64mri8, 0 }, 232 { X86::SHR16r1, X86::SHR16m1, 0 }, 233 { X86::SHR16rCL, X86::SHR16mCL, 0 }, 234 { X86::SHR16ri, X86::SHR16mi, 0 }, 235 { X86::SHR32r1, X86::SHR32m1, 0 }, 236 { X86::SHR32rCL, X86::SHR32mCL, 0 }, 237 { X86::SHR32ri, X86::SHR32mi, 0 }, 238 { X86::SHR64r1, X86::SHR64m1, 0 }, 239 { X86::SHR64rCL, X86::SHR64mCL, 0 }, 240 { X86::SHR64ri, X86::SHR64mi, 0 }, 241 { X86::SHR8r1, X86::SHR8m1, 0 }, 242 { X86::SHR8rCL, X86::SHR8mCL, 0 }, 243 { X86::SHR8ri, X86::SHR8mi, 0 }, 244 { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 }, 245 { X86::SHRD16rri8, X86::SHRD16mri8, 0 }, 246 { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 }, 247 { X86::SHRD32rri8, X86::SHRD32mri8, 0 }, 248 { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 }, 249 { X86::SHRD64rri8, X86::SHRD64mri8, 0 }, 250 { X86::SUB16ri, X86::SUB16mi, 0 }, 251 { X86::SUB16ri8, X86::SUB16mi8, 0 }, 252 { X86::SUB16rr, X86::SUB16mr, 0 }, 253 { X86::SUB32ri, X86::SUB32mi, 0 }, 254 { X86::SUB32ri8, X86::SUB32mi8, 0 }, 255 { X86::SUB32rr, X86::SUB32mr, 0 }, 256 { X86::SUB64ri32, X86::SUB64mi32, 0 }, 257 { X86::SUB64ri8, X86::SUB64mi8, 0 }, 258 { X86::SUB64rr, X86::SUB64mr, 0 }, 259 { X86::SUB8ri, X86::SUB8mi, 0 }, 260 { X86::SUB8rr, X86::SUB8mr, 0 }, 261 { X86::XOR16ri, X86::XOR16mi, 0 }, 262 { X86::XOR16ri8, X86::XOR16mi8, 0 }, 263 { X86::XOR16rr, X86::XOR16mr, 0 }, 264 { X86::XOR32ri, X86::XOR32mi, 0 }, 265 { X86::XOR32ri8, X86::XOR32mi8, 0 }, 266 { X86::XOR32rr, X86::XOR32mr, 0 }, 267 { X86::XOR64ri32, X86::XOR64mi32, 0 }, 268 { X86::XOR64ri8, X86::XOR64mi8, 0 }, 269 { X86::XOR64rr, X86::XOR64mr, 0 }, 270 { X86::XOR8ri, X86::XOR8mi, 0 }, 271 { X86::XOR8rr, X86::XOR8mr, 0 } 272 }; 273 274 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) { 275 unsigned RegOp = OpTbl2Addr[i].RegOp; 276 unsigned MemOp = OpTbl2Addr[i].MemOp; 277 unsigned Flags = OpTbl2Addr[i].Flags; 278 AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable, 279 RegOp, MemOp, 280 // Index 0, folded load and store, no alignment requirement. 281 Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE); 282 } 283 284 static const X86OpTblEntry OpTbl0[] = { 285 { X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD }, 286 { X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD }, 287 { X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD }, 288 { X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD }, 289 { X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD }, 290 { X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD }, 291 { X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD }, 292 { X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD }, 293 { X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD }, 294 { X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD }, 295 { X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD }, 296 { X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD }, 297 { X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD }, 298 { X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD }, 299 { X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD }, 300 { X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD }, 301 { X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD }, 302 { X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD }, 303 { X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD }, 304 { X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD }, 305 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE }, 306 { X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD }, 307 { X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD }, 308 { X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD }, 309 { X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD }, 310 { X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD }, 311 { X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD }, 312 { X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD }, 313 { X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD }, 314 { X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD }, 315 { X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD }, 316 { X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE }, 317 { X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE }, 318 { X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE }, 319 { X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE }, 320 { X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE }, 321 { X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE }, 322 { X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE }, 323 { X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE }, 324 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE }, 325 { X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 326 { X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 327 { X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 328 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE }, 329 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE }, 330 { X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE }, 331 { X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE }, 332 { X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE }, 333 { X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE }, 334 { X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD }, 335 { X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD }, 336 { X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD }, 337 { X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD }, 338 { X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE }, 339 { X86::SETAr, X86::SETAm, TB_FOLDED_STORE }, 340 { X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE }, 341 { X86::SETBr, X86::SETBm, TB_FOLDED_STORE }, 342 { X86::SETEr, X86::SETEm, TB_FOLDED_STORE }, 343 { X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE }, 344 { X86::SETGr, X86::SETGm, TB_FOLDED_STORE }, 345 { X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE }, 346 { X86::SETLr, X86::SETLm, TB_FOLDED_STORE }, 347 { X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE }, 348 { X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE }, 349 { X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE }, 350 { X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE }, 351 { X86::SETOr, X86::SETOm, TB_FOLDED_STORE }, 352 { X86::SETPr, X86::SETPm, TB_FOLDED_STORE }, 353 { X86::SETSr, X86::SETSm, TB_FOLDED_STORE }, 354 { X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD }, 355 { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD }, 356 { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD }, 357 { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD }, 358 { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD }, 359 { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD }, 360 // AVX 128-bit versions of foldable instructions 361 { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE }, 362 { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 }, 363 { X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 364 { X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 365 { X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 366 { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr, TB_FOLDED_STORE }, 367 { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE }, 368 { X86::VMOVSDto64rr,X86::VMOVSDto64mr, TB_FOLDED_STORE }, 369 { X86::VMOVSS2DIrr, X86::VMOVSS2DImr, TB_FOLDED_STORE }, 370 { X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE }, 371 { X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE }, 372 // AVX 256-bit foldable instructions 373 { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 }, 374 { X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE | TB_ALIGN_32 }, 375 { X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE | TB_ALIGN_32 }, 376 { X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE | TB_ALIGN_32 }, 377 { X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE }, 378 { X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE }, 379 // AVX-512 foldable instructions 380 { X86::VMOVPDI2DIZrr,X86::VMOVPDI2DIZmr, TB_FOLDED_STORE } 381 }; 382 383 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) { 384 unsigned RegOp = OpTbl0[i].RegOp; 385 unsigned MemOp = OpTbl0[i].MemOp; 386 unsigned Flags = OpTbl0[i].Flags; 387 AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable, 388 RegOp, MemOp, TB_INDEX_0 | Flags); 389 } 390 391 static const X86OpTblEntry OpTbl1[] = { 392 { X86::CMP16rr, X86::CMP16rm, 0 }, 393 { X86::CMP32rr, X86::CMP32rm, 0 }, 394 { X86::CMP64rr, X86::CMP64rm, 0 }, 395 { X86::CMP8rr, X86::CMP8rm, 0 }, 396 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 }, 397 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 }, 398 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 }, 399 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 }, 400 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 }, 401 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 }, 402 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 }, 403 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 }, 404 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 }, 405 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 }, 406 { X86::IMUL16rri, X86::IMUL16rmi, 0 }, 407 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 }, 408 { X86::IMUL32rri, X86::IMUL32rmi, 0 }, 409 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 }, 410 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 }, 411 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 }, 412 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 }, 413 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 }, 414 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 }, 415 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 }, 416 { X86::CVTSS2SI64rr, X86::CVTSS2SI64rm, 0 }, 417 { X86::CVTSS2SIrr, X86::CVTSS2SIrm, 0 }, 418 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 }, 419 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 }, 420 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 }, 421 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 }, 422 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 }, 423 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 }, 424 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 }, 425 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 }, 426 { X86::MOV16rr, X86::MOV16rm, 0 }, 427 { X86::MOV32rr, X86::MOV32rm, 0 }, 428 { X86::MOV64rr, X86::MOV64rm, 0 }, 429 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 }, 430 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 }, 431 { X86::MOV8rr, X86::MOV8rm, 0 }, 432 { X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 }, 433 { X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 }, 434 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 }, 435 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 }, 436 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 }, 437 { X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 }, 438 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 }, 439 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 }, 440 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 }, 441 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 }, 442 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 }, 443 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 }, 444 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 }, 445 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 }, 446 { X86::MOVUPDrr, X86::MOVUPDrm, TB_ALIGN_16 }, 447 { X86::MOVUPSrr, X86::MOVUPSrm, 0 }, 448 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 }, 449 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, TB_ALIGN_16 }, 450 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 }, 451 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 }, 452 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 }, 453 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 }, 454 { X86::PABSBrr128, X86::PABSBrm128, TB_ALIGN_16 }, 455 { X86::PABSDrr128, X86::PABSDrm128, TB_ALIGN_16 }, 456 { X86::PABSWrr128, X86::PABSWrm128, TB_ALIGN_16 }, 457 { X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 }, 458 { X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 }, 459 { X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 }, 460 { X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 }, 461 { X86::RCPPSr_Int, X86::RCPPSm_Int, TB_ALIGN_16 }, 462 { X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 }, 463 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, TB_ALIGN_16 }, 464 { X86::RSQRTSSr, X86::RSQRTSSm, 0 }, 465 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 }, 466 { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 }, 467 { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 }, 468 { X86::SQRTSDr, X86::SQRTSDm, 0 }, 469 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 }, 470 { X86::SQRTSSr, X86::SQRTSSm, 0 }, 471 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 }, 472 { X86::TEST16rr, X86::TEST16rm, 0 }, 473 { X86::TEST32rr, X86::TEST32rm, 0 }, 474 { X86::TEST64rr, X86::TEST64rm, 0 }, 475 { X86::TEST8rr, X86::TEST8rm, 0 }, 476 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0 477 { X86::UCOMISDrr, X86::UCOMISDrm, 0 }, 478 { X86::UCOMISSrr, X86::UCOMISSrm, 0 }, 479 // AVX 128-bit versions of foldable instructions 480 { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, 0 }, 481 { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, 0 }, 482 { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 }, 483 { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 }, 484 { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 }, 485 { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 }, 486 { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 }, 487 { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm, 0 }, 488 { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 }, 489 { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 }, 490 { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 }, 491 { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm, 0 }, 492 { X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, 0 }, 493 { X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, 0 }, 494 { X86::VCVTSS2SI64rr, X86::VCVTSS2SI64rm, 0 }, 495 { X86::VCVTSS2SIrr, X86::VCVTSS2SIrm, 0 }, 496 { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 }, 497 { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 }, 498 { X86::VMOVAPDrr, X86::VMOVAPDrm, TB_ALIGN_16 }, 499 { X86::VMOVAPSrr, X86::VMOVAPSrm, TB_ALIGN_16 }, 500 { X86::VMOVDDUPrr, X86::VMOVDDUPrm, 0 }, 501 { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 }, 502 { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 }, 503 { X86::VMOVDQArr, X86::VMOVDQArm, TB_ALIGN_16 }, 504 { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, TB_ALIGN_16 }, 505 { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, TB_ALIGN_16 }, 506 { X86::VMOVUPDrr, X86::VMOVUPDrm, 0 }, 507 { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 }, 508 { X86::VMOVZQI2PQIrr, X86::VMOVZQI2PQIrm, 0 }, 509 { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm, TB_ALIGN_16 }, 510 { X86::VPABSBrr128, X86::VPABSBrm128, 0 }, 511 { X86::VPABSDrr128, X86::VPABSDrm128, 0 }, 512 { X86::VPABSWrr128, X86::VPABSWrm128, 0 }, 513 { X86::VPERMILPDri, X86::VPERMILPDmi, 0 }, 514 { X86::VPERMILPSri, X86::VPERMILPSmi, 0 }, 515 { X86::VPSHUFDri, X86::VPSHUFDmi, 0 }, 516 { X86::VPSHUFHWri, X86::VPSHUFHWmi, 0 }, 517 { X86::VPSHUFLWri, X86::VPSHUFLWmi, 0 }, 518 { X86::VRCPPSr, X86::VRCPPSm, 0 }, 519 { X86::VRCPPSr_Int, X86::VRCPPSm_Int, 0 }, 520 { X86::VRSQRTPSr, X86::VRSQRTPSm, 0 }, 521 { X86::VRSQRTPSr_Int, X86::VRSQRTPSm_Int, 0 }, 522 { X86::VSQRTPDr, X86::VSQRTPDm, 0 }, 523 { X86::VSQRTPSr, X86::VSQRTPSm, 0 }, 524 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 }, 525 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 }, 526 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrm, TB_NO_REVERSE }, 527 528 // AVX 256-bit foldable instructions 529 { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 }, 530 { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 }, 531 { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_32 }, 532 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 }, 533 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 }, 534 { X86::VPERMILPDYri, X86::VPERMILPDYmi, 0 }, 535 { X86::VPERMILPSYri, X86::VPERMILPSYmi, 0 }, 536 537 // AVX2 foldable instructions 538 { X86::VPABSBrr256, X86::VPABSBrm256, 0 }, 539 { X86::VPABSDrr256, X86::VPABSDrm256, 0 }, 540 { X86::VPABSWrr256, X86::VPABSWrm256, 0 }, 541 { X86::VPSHUFDYri, X86::VPSHUFDYmi, 0 }, 542 { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, 0 }, 543 { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, 0 }, 544 { X86::VRCPPSYr, X86::VRCPPSYm, 0 }, 545 { X86::VRCPPSYr_Int, X86::VRCPPSYm_Int, 0 }, 546 { X86::VRSQRTPSYr, X86::VRSQRTPSYm, 0 }, 547 { X86::VSQRTPDYr, X86::VSQRTPDYm, 0 }, 548 { X86::VSQRTPSYr, X86::VSQRTPSYm, 0 }, 549 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm, TB_NO_REVERSE }, 550 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm, TB_NO_REVERSE }, 551 552 // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions 553 { X86::BEXTR32rr, X86::BEXTR32rm, 0 }, 554 { X86::BEXTR64rr, X86::BEXTR64rm, 0 }, 555 { X86::BEXTRI32ri, X86::BEXTRI32mi, 0 }, 556 { X86::BEXTRI64ri, X86::BEXTRI64mi, 0 }, 557 { X86::BLCFILL32rr, X86::BLCFILL32rm, 0 }, 558 { X86::BLCFILL64rr, X86::BLCFILL64rm, 0 }, 559 { X86::BLCI32rr, X86::BLCI32rm, 0 }, 560 { X86::BLCI64rr, X86::BLCI64rm, 0 }, 561 { X86::BLCIC32rr, X86::BLCIC32rm, 0 }, 562 { X86::BLCIC64rr, X86::BLCIC64rm, 0 }, 563 { X86::BLCMSK32rr, X86::BLCMSK32rm, 0 }, 564 { X86::BLCMSK64rr, X86::BLCMSK64rm, 0 }, 565 { X86::BLCS32rr, X86::BLCS32rm, 0 }, 566 { X86::BLCS64rr, X86::BLCS64rm, 0 }, 567 { X86::BLSFILL32rr, X86::BLSFILL32rm, 0 }, 568 { X86::BLSFILL64rr, X86::BLSFILL64rm, 0 }, 569 { X86::BLSI32rr, X86::BLSI32rm, 0 }, 570 { X86::BLSI64rr, X86::BLSI64rm, 0 }, 571 { X86::BLSIC32rr, X86::BLSIC32rm, 0 }, 572 { X86::BLSIC64rr, X86::BLSIC64rm, 0 }, 573 { X86::BLSMSK32rr, X86::BLSMSK32rm, 0 }, 574 { X86::BLSMSK64rr, X86::BLSMSK64rm, 0 }, 575 { X86::BLSR32rr, X86::BLSR32rm, 0 }, 576 { X86::BLSR64rr, X86::BLSR64rm, 0 }, 577 { X86::BZHI32rr, X86::BZHI32rm, 0 }, 578 { X86::BZHI64rr, X86::BZHI64rm, 0 }, 579 { X86::LZCNT16rr, X86::LZCNT16rm, 0 }, 580 { X86::LZCNT32rr, X86::LZCNT32rm, 0 }, 581 { X86::LZCNT64rr, X86::LZCNT64rm, 0 }, 582 { X86::POPCNT16rr, X86::POPCNT16rm, 0 }, 583 { X86::POPCNT32rr, X86::POPCNT32rm, 0 }, 584 { X86::POPCNT64rr, X86::POPCNT64rm, 0 }, 585 { X86::RORX32ri, X86::RORX32mi, 0 }, 586 { X86::RORX64ri, X86::RORX64mi, 0 }, 587 { X86::SARX32rr, X86::SARX32rm, 0 }, 588 { X86::SARX64rr, X86::SARX64rm, 0 }, 589 { X86::SHRX32rr, X86::SHRX32rm, 0 }, 590 { X86::SHRX64rr, X86::SHRX64rm, 0 }, 591 { X86::SHLX32rr, X86::SHLX32rm, 0 }, 592 { X86::SHLX64rr, X86::SHLX64rm, 0 }, 593 { X86::T1MSKC32rr, X86::T1MSKC32rm, 0 }, 594 { X86::T1MSKC64rr, X86::T1MSKC64rm, 0 }, 595 { X86::TZCNT16rr, X86::TZCNT16rm, 0 }, 596 { X86::TZCNT32rr, X86::TZCNT32rm, 0 }, 597 { X86::TZCNT64rr, X86::TZCNT64rm, 0 }, 598 { X86::TZMSK32rr, X86::TZMSK32rm, 0 }, 599 { X86::TZMSK64rr, X86::TZMSK64rm, 0 }, 600 601 // AVX-512 foldable instructions 602 { X86::VMOV64toPQIZrr, X86::VMOVQI2PQIZrm, 0 }, 603 { X86::VMOVDI2SSZrr, X86::VMOVDI2SSZrm, 0 }, 604 { X86::VMOVDQA32rr, X86::VMOVDQA32rm, TB_ALIGN_64 }, 605 { X86::VMOVDQA64rr, X86::VMOVDQA64rm, TB_ALIGN_64 }, 606 { X86::VMOVDQU32rr, X86::VMOVDQU32rm, 0 }, 607 { X86::VMOVDQU64rr, X86::VMOVDQU64rm, 0 }, 608 { X86::VPABSDZrr, X86::VPABSDZrm, 0 }, 609 { X86::VPABSQZrr, X86::VPABSQZrm, 0 }, 610 611 // AES foldable instructions 612 { X86::AESIMCrr, X86::AESIMCrm, TB_ALIGN_16 }, 613 { X86::AESKEYGENASSIST128rr, X86::AESKEYGENASSIST128rm, TB_ALIGN_16 }, 614 { X86::VAESIMCrr, X86::VAESIMCrm, TB_ALIGN_16 }, 615 { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, TB_ALIGN_16 }, 616 }; 617 618 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) { 619 unsigned RegOp = OpTbl1[i].RegOp; 620 unsigned MemOp = OpTbl1[i].MemOp; 621 unsigned Flags = OpTbl1[i].Flags; 622 AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable, 623 RegOp, MemOp, 624 // Index 1, folded load 625 Flags | TB_INDEX_1 | TB_FOLDED_LOAD); 626 } 627 628 static const X86OpTblEntry OpTbl2[] = { 629 { X86::ADC32rr, X86::ADC32rm, 0 }, 630 { X86::ADC64rr, X86::ADC64rm, 0 }, 631 { X86::ADD16rr, X86::ADD16rm, 0 }, 632 { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE }, 633 { X86::ADD32rr, X86::ADD32rm, 0 }, 634 { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE }, 635 { X86::ADD64rr, X86::ADD64rm, 0 }, 636 { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE }, 637 { X86::ADD8rr, X86::ADD8rm, 0 }, 638 { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 }, 639 { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 }, 640 { X86::ADDSDrr, X86::ADDSDrm, 0 }, 641 { X86::ADDSSrr, X86::ADDSSrm, 0 }, 642 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 }, 643 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 }, 644 { X86::AND16rr, X86::AND16rm, 0 }, 645 { X86::AND32rr, X86::AND32rm, 0 }, 646 { X86::AND64rr, X86::AND64rm, 0 }, 647 { X86::AND8rr, X86::AND8rm, 0 }, 648 { X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 }, 649 { X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 }, 650 { X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 }, 651 { X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 }, 652 { X86::BLENDPDrri, X86::BLENDPDrmi, TB_ALIGN_16 }, 653 { X86::BLENDPSrri, X86::BLENDPSrmi, TB_ALIGN_16 }, 654 { X86::BLENDVPDrr0, X86::BLENDVPDrm0, TB_ALIGN_16 }, 655 { X86::BLENDVPSrr0, X86::BLENDVPSrm0, TB_ALIGN_16 }, 656 { X86::CMOVA16rr, X86::CMOVA16rm, 0 }, 657 { X86::CMOVA32rr, X86::CMOVA32rm, 0 }, 658 { X86::CMOVA64rr, X86::CMOVA64rm, 0 }, 659 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 }, 660 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 }, 661 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 }, 662 { X86::CMOVB16rr, X86::CMOVB16rm, 0 }, 663 { X86::CMOVB32rr, X86::CMOVB32rm, 0 }, 664 { X86::CMOVB64rr, X86::CMOVB64rm, 0 }, 665 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 }, 666 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 }, 667 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 }, 668 { X86::CMOVE16rr, X86::CMOVE16rm, 0 }, 669 { X86::CMOVE32rr, X86::CMOVE32rm, 0 }, 670 { X86::CMOVE64rr, X86::CMOVE64rm, 0 }, 671 { X86::CMOVG16rr, X86::CMOVG16rm, 0 }, 672 { X86::CMOVG32rr, X86::CMOVG32rm, 0 }, 673 { X86::CMOVG64rr, X86::CMOVG64rm, 0 }, 674 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 }, 675 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 }, 676 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 }, 677 { X86::CMOVL16rr, X86::CMOVL16rm, 0 }, 678 { X86::CMOVL32rr, X86::CMOVL32rm, 0 }, 679 { X86::CMOVL64rr, X86::CMOVL64rm, 0 }, 680 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 }, 681 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 }, 682 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 }, 683 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 }, 684 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 }, 685 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 }, 686 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 }, 687 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 }, 688 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 }, 689 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 }, 690 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 }, 691 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 }, 692 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 }, 693 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 }, 694 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 }, 695 { X86::CMOVO16rr, X86::CMOVO16rm, 0 }, 696 { X86::CMOVO32rr, X86::CMOVO32rm, 0 }, 697 { X86::CMOVO64rr, X86::CMOVO64rm, 0 }, 698 { X86::CMOVP16rr, X86::CMOVP16rm, 0 }, 699 { X86::CMOVP32rr, X86::CMOVP32rm, 0 }, 700 { X86::CMOVP64rr, X86::CMOVP64rm, 0 }, 701 { X86::CMOVS16rr, X86::CMOVS16rm, 0 }, 702 { X86::CMOVS32rr, X86::CMOVS32rm, 0 }, 703 { X86::CMOVS64rr, X86::CMOVS64rm, 0 }, 704 { X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 }, 705 { X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 }, 706 { X86::CMPSDrr, X86::CMPSDrm, 0 }, 707 { X86::CMPSSrr, X86::CMPSSrm, 0 }, 708 { X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 }, 709 { X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 }, 710 { X86::DIVSDrr, X86::DIVSDrm, 0 }, 711 { X86::DIVSSrr, X86::DIVSSrm, 0 }, 712 { X86::FsANDNPDrr, X86::FsANDNPDrm, TB_ALIGN_16 }, 713 { X86::FsANDNPSrr, X86::FsANDNPSrm, TB_ALIGN_16 }, 714 { X86::FsANDPDrr, X86::FsANDPDrm, TB_ALIGN_16 }, 715 { X86::FsANDPSrr, X86::FsANDPSrm, TB_ALIGN_16 }, 716 { X86::FsORPDrr, X86::FsORPDrm, TB_ALIGN_16 }, 717 { X86::FsORPSrr, X86::FsORPSrm, TB_ALIGN_16 }, 718 { X86::FsXORPDrr, X86::FsXORPDrm, TB_ALIGN_16 }, 719 { X86::FsXORPSrr, X86::FsXORPSrm, TB_ALIGN_16 }, 720 { X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 }, 721 { X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 }, 722 { X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 }, 723 { X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 }, 724 { X86::IMUL16rr, X86::IMUL16rm, 0 }, 725 { X86::IMUL32rr, X86::IMUL32rm, 0 }, 726 { X86::IMUL64rr, X86::IMUL64rm, 0 }, 727 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 }, 728 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 }, 729 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 }, 730 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 }, 731 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 }, 732 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 }, 733 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 }, 734 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 }, 735 { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 }, 736 { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 }, 737 { X86::MAXSDrr, X86::MAXSDrm, 0 }, 738 { X86::MAXSSrr, X86::MAXSSrm, 0 }, 739 { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 }, 740 { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 }, 741 { X86::MINSDrr, X86::MINSDrm, 0 }, 742 { X86::MINSSrr, X86::MINSSrm, 0 }, 743 { X86::MPSADBWrri, X86::MPSADBWrmi, TB_ALIGN_16 }, 744 { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 }, 745 { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 }, 746 { X86::MULSDrr, X86::MULSDrm, 0 }, 747 { X86::MULSSrr, X86::MULSSrm, 0 }, 748 { X86::OR16rr, X86::OR16rm, 0 }, 749 { X86::OR32rr, X86::OR32rm, 0 }, 750 { X86::OR64rr, X86::OR64rm, 0 }, 751 { X86::OR8rr, X86::OR8rm, 0 }, 752 { X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 }, 753 { X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 }, 754 { X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 }, 755 { X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 }, 756 { X86::PACKUSDWrr, X86::PACKUSDWrm, TB_ALIGN_16 }, 757 { X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 }, 758 { X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 }, 759 { X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 }, 760 { X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 }, 761 { X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 }, 762 { X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 }, 763 { X86::PADDUSBrr, X86::PADDUSBrm, TB_ALIGN_16 }, 764 { X86::PADDUSWrr, X86::PADDUSWrm, TB_ALIGN_16 }, 765 { X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 }, 766 { X86::PALIGNR128rr, X86::PALIGNR128rm, TB_ALIGN_16 }, 767 { X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 }, 768 { X86::PANDrr, X86::PANDrm, TB_ALIGN_16 }, 769 { X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 }, 770 { X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 }, 771 { X86::PBLENDWrri, X86::PBLENDWrmi, TB_ALIGN_16 }, 772 { X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 }, 773 { X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 }, 774 { X86::PCMPEQQrr, X86::PCMPEQQrm, TB_ALIGN_16 }, 775 { X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 }, 776 { X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 }, 777 { X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 }, 778 { X86::PCMPGTQrr, X86::PCMPGTQrm, TB_ALIGN_16 }, 779 { X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 }, 780 { X86::PHADDDrr, X86::PHADDDrm, TB_ALIGN_16 }, 781 { X86::PHADDWrr, X86::PHADDWrm, TB_ALIGN_16 }, 782 { X86::PHADDSWrr128, X86::PHADDSWrm128, TB_ALIGN_16 }, 783 { X86::PHSUBDrr, X86::PHSUBDrm, TB_ALIGN_16 }, 784 { X86::PHSUBSWrr128, X86::PHSUBSWrm128, TB_ALIGN_16 }, 785 { X86::PHSUBWrr, X86::PHSUBWrm, TB_ALIGN_16 }, 786 { X86::PINSRWrri, X86::PINSRWrmi, TB_ALIGN_16 }, 787 { X86::PMADDUBSWrr128, X86::PMADDUBSWrm128, TB_ALIGN_16 }, 788 { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 }, 789 { X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 }, 790 { X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 }, 791 { X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 }, 792 { X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 }, 793 { X86::PMINSBrr, X86::PMINSBrm, TB_ALIGN_16 }, 794 { X86::PMINSDrr, X86::PMINSDrm, TB_ALIGN_16 }, 795 { X86::PMINUDrr, X86::PMINUDrm, TB_ALIGN_16 }, 796 { X86::PMINUWrr, X86::PMINUWrm, TB_ALIGN_16 }, 797 { X86::PMAXSBrr, X86::PMAXSBrm, TB_ALIGN_16 }, 798 { X86::PMAXSDrr, X86::PMAXSDrm, TB_ALIGN_16 }, 799 { X86::PMAXUDrr, X86::PMAXUDrm, TB_ALIGN_16 }, 800 { X86::PMAXUWrr, X86::PMAXUWrm, TB_ALIGN_16 }, 801 { X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 }, 802 { X86::PMULHRSWrr128, X86::PMULHRSWrm128, TB_ALIGN_16 }, 803 { X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 }, 804 { X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 }, 805 { X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 }, 806 { X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 }, 807 { X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 }, 808 { X86::PORrr, X86::PORrm, TB_ALIGN_16 }, 809 { X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 }, 810 { X86::PSHUFBrr, X86::PSHUFBrm, TB_ALIGN_16 }, 811 { X86::PSIGNBrr, X86::PSIGNBrm, TB_ALIGN_16 }, 812 { X86::PSIGNWrr, X86::PSIGNWrm, TB_ALIGN_16 }, 813 { X86::PSIGNDrr, X86::PSIGNDrm, TB_ALIGN_16 }, 814 { X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 }, 815 { X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 }, 816 { X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 }, 817 { X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 }, 818 { X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 }, 819 { X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 }, 820 { X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 }, 821 { X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 }, 822 { X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 }, 823 { X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 }, 824 { X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 }, 825 { X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 }, 826 { X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 }, 827 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 }, 828 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 }, 829 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 }, 830 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 }, 831 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 }, 832 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 }, 833 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 }, 834 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 }, 835 { X86::PXORrr, X86::PXORrm, TB_ALIGN_16 }, 836 { X86::SBB32rr, X86::SBB32rm, 0 }, 837 { X86::SBB64rr, X86::SBB64rm, 0 }, 838 { X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 }, 839 { X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 }, 840 { X86::SUB16rr, X86::SUB16rm, 0 }, 841 { X86::SUB32rr, X86::SUB32rm, 0 }, 842 { X86::SUB64rr, X86::SUB64rm, 0 }, 843 { X86::SUB8rr, X86::SUB8rm, 0 }, 844 { X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 }, 845 { X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 }, 846 { X86::SUBSDrr, X86::SUBSDrm, 0 }, 847 { X86::SUBSSrr, X86::SUBSSrm, 0 }, 848 // FIXME: TEST*rr -> swapped operand of TEST*mr. 849 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 }, 850 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 }, 851 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 }, 852 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 }, 853 { X86::XOR16rr, X86::XOR16rm, 0 }, 854 { X86::XOR32rr, X86::XOR32rm, 0 }, 855 { X86::XOR64rr, X86::XOR64rm, 0 }, 856 { X86::XOR8rr, X86::XOR8rm, 0 }, 857 { X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 }, 858 { X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 }, 859 // AVX 128-bit versions of foldable instructions 860 { X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 }, 861 { X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm, 0 }, 862 { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 }, 863 { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 }, 864 { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 }, 865 { X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 }, 866 { X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 }, 867 { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 }, 868 { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 }, 869 { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 }, 870 { X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 }, 871 { X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm, 0 }, 872 { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQXrm, 0 }, 873 { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, 0 }, 874 { X86::VRSQRTSSr, X86::VRSQRTSSm, 0 }, 875 { X86::VSQRTSDr, X86::VSQRTSDm, 0 }, 876 { X86::VSQRTSSr, X86::VSQRTSSm, 0 }, 877 { X86::VADDPDrr, X86::VADDPDrm, 0 }, 878 { X86::VADDPSrr, X86::VADDPSrm, 0 }, 879 { X86::VADDSDrr, X86::VADDSDrm, 0 }, 880 { X86::VADDSSrr, X86::VADDSSrm, 0 }, 881 { X86::VADDSUBPDrr, X86::VADDSUBPDrm, 0 }, 882 { X86::VADDSUBPSrr, X86::VADDSUBPSrm, 0 }, 883 { X86::VANDNPDrr, X86::VANDNPDrm, 0 }, 884 { X86::VANDNPSrr, X86::VANDNPSrm, 0 }, 885 { X86::VANDPDrr, X86::VANDPDrm, 0 }, 886 { X86::VANDPSrr, X86::VANDPSrm, 0 }, 887 { X86::VBLENDPDrri, X86::VBLENDPDrmi, 0 }, 888 { X86::VBLENDPSrri, X86::VBLENDPSrmi, 0 }, 889 { X86::VBLENDVPDrr, X86::VBLENDVPDrm, 0 }, 890 { X86::VBLENDVPSrr, X86::VBLENDVPSrm, 0 }, 891 { X86::VCMPPDrri, X86::VCMPPDrmi, 0 }, 892 { X86::VCMPPSrri, X86::VCMPPSrmi, 0 }, 893 { X86::VCMPSDrr, X86::VCMPSDrm, 0 }, 894 { X86::VCMPSSrr, X86::VCMPSSrm, 0 }, 895 { X86::VDIVPDrr, X86::VDIVPDrm, 0 }, 896 { X86::VDIVPSrr, X86::VDIVPSrm, 0 }, 897 { X86::VDIVSDrr, X86::VDIVSDrm, 0 }, 898 { X86::VDIVSSrr, X86::VDIVSSrm, 0 }, 899 { X86::VFsANDNPDrr, X86::VFsANDNPDrm, TB_ALIGN_16 }, 900 { X86::VFsANDNPSrr, X86::VFsANDNPSrm, TB_ALIGN_16 }, 901 { X86::VFsANDPDrr, X86::VFsANDPDrm, TB_ALIGN_16 }, 902 { X86::VFsANDPSrr, X86::VFsANDPSrm, TB_ALIGN_16 }, 903 { X86::VFsORPDrr, X86::VFsORPDrm, TB_ALIGN_16 }, 904 { X86::VFsORPSrr, X86::VFsORPSrm, TB_ALIGN_16 }, 905 { X86::VFsXORPDrr, X86::VFsXORPDrm, TB_ALIGN_16 }, 906 { X86::VFsXORPSrr, X86::VFsXORPSrm, TB_ALIGN_16 }, 907 { X86::VHADDPDrr, X86::VHADDPDrm, 0 }, 908 { X86::VHADDPSrr, X86::VHADDPSrm, 0 }, 909 { X86::VHSUBPDrr, X86::VHSUBPDrm, 0 }, 910 { X86::VHSUBPSrr, X86::VHSUBPSrm, 0 }, 911 { X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, 0 }, 912 { X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, 0 }, 913 { X86::VMAXPDrr, X86::VMAXPDrm, 0 }, 914 { X86::VMAXPSrr, X86::VMAXPSrm, 0 }, 915 { X86::VMAXSDrr, X86::VMAXSDrm, 0 }, 916 { X86::VMAXSSrr, X86::VMAXSSrm, 0 }, 917 { X86::VMINPDrr, X86::VMINPDrm, 0 }, 918 { X86::VMINPSrr, X86::VMINPSrm, 0 }, 919 { X86::VMINSDrr, X86::VMINSDrm, 0 }, 920 { X86::VMINSSrr, X86::VMINSSrm, 0 }, 921 { X86::VMPSADBWrri, X86::VMPSADBWrmi, 0 }, 922 { X86::VMULPDrr, X86::VMULPDrm, 0 }, 923 { X86::VMULPSrr, X86::VMULPSrm, 0 }, 924 { X86::VMULSDrr, X86::VMULSDrm, 0 }, 925 { X86::VMULSSrr, X86::VMULSSrm, 0 }, 926 { X86::VORPDrr, X86::VORPDrm, 0 }, 927 { X86::VORPSrr, X86::VORPSrm, 0 }, 928 { X86::VPACKSSDWrr, X86::VPACKSSDWrm, 0 }, 929 { X86::VPACKSSWBrr, X86::VPACKSSWBrm, 0 }, 930 { X86::VPACKUSDWrr, X86::VPACKUSDWrm, 0 }, 931 { X86::VPACKUSWBrr, X86::VPACKUSWBrm, 0 }, 932 { X86::VPADDBrr, X86::VPADDBrm, 0 }, 933 { X86::VPADDDrr, X86::VPADDDrm, 0 }, 934 { X86::VPADDQrr, X86::VPADDQrm, 0 }, 935 { X86::VPADDSBrr, X86::VPADDSBrm, 0 }, 936 { X86::VPADDSWrr, X86::VPADDSWrm, 0 }, 937 { X86::VPADDUSBrr, X86::VPADDUSBrm, 0 }, 938 { X86::VPADDUSWrr, X86::VPADDUSWrm, 0 }, 939 { X86::VPADDWrr, X86::VPADDWrm, 0 }, 940 { X86::VPALIGNR128rr, X86::VPALIGNR128rm, 0 }, 941 { X86::VPANDNrr, X86::VPANDNrm, 0 }, 942 { X86::VPANDrr, X86::VPANDrm, 0 }, 943 { X86::VPAVGBrr, X86::VPAVGBrm, 0 }, 944 { X86::VPAVGWrr, X86::VPAVGWrm, 0 }, 945 { X86::VPBLENDWrri, X86::VPBLENDWrmi, 0 }, 946 { X86::VPCMPEQBrr, X86::VPCMPEQBrm, 0 }, 947 { X86::VPCMPEQDrr, X86::VPCMPEQDrm, 0 }, 948 { X86::VPCMPEQQrr, X86::VPCMPEQQrm, 0 }, 949 { X86::VPCMPEQWrr, X86::VPCMPEQWrm, 0 }, 950 { X86::VPCMPGTBrr, X86::VPCMPGTBrm, 0 }, 951 { X86::VPCMPGTDrr, X86::VPCMPGTDrm, 0 }, 952 { X86::VPCMPGTQrr, X86::VPCMPGTQrm, 0 }, 953 { X86::VPCMPGTWrr, X86::VPCMPGTWrm, 0 }, 954 { X86::VPHADDDrr, X86::VPHADDDrm, 0 }, 955 { X86::VPHADDSWrr128, X86::VPHADDSWrm128, 0 }, 956 { X86::VPHADDWrr, X86::VPHADDWrm, 0 }, 957 { X86::VPHSUBDrr, X86::VPHSUBDrm, 0 }, 958 { X86::VPHSUBSWrr128, X86::VPHSUBSWrm128, 0 }, 959 { X86::VPHSUBWrr, X86::VPHSUBWrm, 0 }, 960 { X86::VPERMILPDrr, X86::VPERMILPDrm, 0 }, 961 { X86::VPERMILPSrr, X86::VPERMILPSrm, 0 }, 962 { X86::VPINSRWrri, X86::VPINSRWrmi, 0 }, 963 { X86::VPMADDUBSWrr128, X86::VPMADDUBSWrm128, 0 }, 964 { X86::VPMADDWDrr, X86::VPMADDWDrm, 0 }, 965 { X86::VPMAXSWrr, X86::VPMAXSWrm, 0 }, 966 { X86::VPMAXUBrr, X86::VPMAXUBrm, 0 }, 967 { X86::VPMINSWrr, X86::VPMINSWrm, 0 }, 968 { X86::VPMINUBrr, X86::VPMINUBrm, 0 }, 969 { X86::VPMINSBrr, X86::VPMINSBrm, 0 }, 970 { X86::VPMINSDrr, X86::VPMINSDrm, 0 }, 971 { X86::VPMINUDrr, X86::VPMINUDrm, 0 }, 972 { X86::VPMINUWrr, X86::VPMINUWrm, 0 }, 973 { X86::VPMAXSBrr, X86::VPMAXSBrm, 0 }, 974 { X86::VPMAXSDrr, X86::VPMAXSDrm, 0 }, 975 { X86::VPMAXUDrr, X86::VPMAXUDrm, 0 }, 976 { X86::VPMAXUWrr, X86::VPMAXUWrm, 0 }, 977 { X86::VPMULDQrr, X86::VPMULDQrm, 0 }, 978 { X86::VPMULHRSWrr128, X86::VPMULHRSWrm128, 0 }, 979 { X86::VPMULHUWrr, X86::VPMULHUWrm, 0 }, 980 { X86::VPMULHWrr, X86::VPMULHWrm, 0 }, 981 { X86::VPMULLDrr, X86::VPMULLDrm, 0 }, 982 { X86::VPMULLWrr, X86::VPMULLWrm, 0 }, 983 { X86::VPMULUDQrr, X86::VPMULUDQrm, 0 }, 984 { X86::VPORrr, X86::VPORrm, 0 }, 985 { X86::VPSADBWrr, X86::VPSADBWrm, 0 }, 986 { X86::VPSHUFBrr, X86::VPSHUFBrm, 0 }, 987 { X86::VPSIGNBrr, X86::VPSIGNBrm, 0 }, 988 { X86::VPSIGNWrr, X86::VPSIGNWrm, 0 }, 989 { X86::VPSIGNDrr, X86::VPSIGNDrm, 0 }, 990 { X86::VPSLLDrr, X86::VPSLLDrm, 0 }, 991 { X86::VPSLLQrr, X86::VPSLLQrm, 0 }, 992 { X86::VPSLLWrr, X86::VPSLLWrm, 0 }, 993 { X86::VPSRADrr, X86::VPSRADrm, 0 }, 994 { X86::VPSRAWrr, X86::VPSRAWrm, 0 }, 995 { X86::VPSRLDrr, X86::VPSRLDrm, 0 }, 996 { X86::VPSRLQrr, X86::VPSRLQrm, 0 }, 997 { X86::VPSRLWrr, X86::VPSRLWrm, 0 }, 998 { X86::VPSUBBrr, X86::VPSUBBrm, 0 }, 999 { X86::VPSUBDrr, X86::VPSUBDrm, 0 }, 1000 { X86::VPSUBSBrr, X86::VPSUBSBrm, 0 }, 1001 { X86::VPSUBSWrr, X86::VPSUBSWrm, 0 }, 1002 { X86::VPSUBWrr, X86::VPSUBWrm, 0 }, 1003 { X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, 0 }, 1004 { X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, 0 }, 1005 { X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, 0 }, 1006 { X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, 0 }, 1007 { X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, 0 }, 1008 { X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, 0 }, 1009 { X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, 0 }, 1010 { X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, 0 }, 1011 { X86::VPXORrr, X86::VPXORrm, 0 }, 1012 { X86::VSHUFPDrri, X86::VSHUFPDrmi, 0 }, 1013 { X86::VSHUFPSrri, X86::VSHUFPSrmi, 0 }, 1014 { X86::VSUBPDrr, X86::VSUBPDrm, 0 }, 1015 { X86::VSUBPSrr, X86::VSUBPSrm, 0 }, 1016 { X86::VSUBSDrr, X86::VSUBSDrm, 0 }, 1017 { X86::VSUBSSrr, X86::VSUBSSrm, 0 }, 1018 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, 0 }, 1019 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, 0 }, 1020 { X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, 0 }, 1021 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, 0 }, 1022 { X86::VXORPDrr, X86::VXORPDrm, 0 }, 1023 { X86::VXORPSrr, X86::VXORPSrm, 0 }, 1024 // AVX 256-bit foldable instructions 1025 { X86::VADDPDYrr, X86::VADDPDYrm, 0 }, 1026 { X86::VADDPSYrr, X86::VADDPSYrm, 0 }, 1027 { X86::VADDSUBPDYrr, X86::VADDSUBPDYrm, 0 }, 1028 { X86::VADDSUBPSYrr, X86::VADDSUBPSYrm, 0 }, 1029 { X86::VANDNPDYrr, X86::VANDNPDYrm, 0 }, 1030 { X86::VANDNPSYrr, X86::VANDNPSYrm, 0 }, 1031 { X86::VANDPDYrr, X86::VANDPDYrm, 0 }, 1032 { X86::VANDPSYrr, X86::VANDPSYrm, 0 }, 1033 { X86::VBLENDPDYrri, X86::VBLENDPDYrmi, 0 }, 1034 { X86::VBLENDPSYrri, X86::VBLENDPSYrmi, 0 }, 1035 { X86::VBLENDVPDYrr, X86::VBLENDVPDYrm, 0 }, 1036 { X86::VBLENDVPSYrr, X86::VBLENDVPSYrm, 0 }, 1037 { X86::VCMPPDYrri, X86::VCMPPDYrmi, 0 }, 1038 { X86::VCMPPSYrri, X86::VCMPPSYrmi, 0 }, 1039 { X86::VDIVPDYrr, X86::VDIVPDYrm, 0 }, 1040 { X86::VDIVPSYrr, X86::VDIVPSYrm, 0 }, 1041 { X86::VHADDPDYrr, X86::VHADDPDYrm, 0 }, 1042 { X86::VHADDPSYrr, X86::VHADDPSYrm, 0 }, 1043 { X86::VHSUBPDYrr, X86::VHSUBPDYrm, 0 }, 1044 { X86::VHSUBPSYrr, X86::VHSUBPSYrm, 0 }, 1045 { X86::VINSERTF128rr, X86::VINSERTF128rm, 0 }, 1046 { X86::VMAXPDYrr, X86::VMAXPDYrm, 0 }, 1047 { X86::VMAXPSYrr, X86::VMAXPSYrm, 0 }, 1048 { X86::VMINPDYrr, X86::VMINPDYrm, 0 }, 1049 { X86::VMINPSYrr, X86::VMINPSYrm, 0 }, 1050 { X86::VMULPDYrr, X86::VMULPDYrm, 0 }, 1051 { X86::VMULPSYrr, X86::VMULPSYrm, 0 }, 1052 { X86::VORPDYrr, X86::VORPDYrm, 0 }, 1053 { X86::VORPSYrr, X86::VORPSYrm, 0 }, 1054 { X86::VPERM2F128rr, X86::VPERM2F128rm, 0 }, 1055 { X86::VPERMILPDYrr, X86::VPERMILPDYrm, 0 }, 1056 { X86::VPERMILPSYrr, X86::VPERMILPSYrm, 0 }, 1057 { X86::VSHUFPDYrri, X86::VSHUFPDYrmi, 0 }, 1058 { X86::VSHUFPSYrri, X86::VSHUFPSYrmi, 0 }, 1059 { X86::VSUBPDYrr, X86::VSUBPDYrm, 0 }, 1060 { X86::VSUBPSYrr, X86::VSUBPSYrm, 0 }, 1061 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrm, 0 }, 1062 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrm, 0 }, 1063 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrm, 0 }, 1064 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrm, 0 }, 1065 { X86::VXORPDYrr, X86::VXORPDYrm, 0 }, 1066 { X86::VXORPSYrr, X86::VXORPSYrm, 0 }, 1067 // AVX2 foldable instructions 1068 { X86::VINSERTI128rr, X86::VINSERTI128rm, 0 }, 1069 { X86::VPACKSSDWYrr, X86::VPACKSSDWYrm, 0 }, 1070 { X86::VPACKSSWBYrr, X86::VPACKSSWBYrm, 0 }, 1071 { X86::VPACKUSDWYrr, X86::VPACKUSDWYrm, 0 }, 1072 { X86::VPACKUSWBYrr, X86::VPACKUSWBYrm, 0 }, 1073 { X86::VPADDBYrr, X86::VPADDBYrm, 0 }, 1074 { X86::VPADDDYrr, X86::VPADDDYrm, 0 }, 1075 { X86::VPADDQYrr, X86::VPADDQYrm, 0 }, 1076 { X86::VPADDSBYrr, X86::VPADDSBYrm, 0 }, 1077 { X86::VPADDSWYrr, X86::VPADDSWYrm, 0 }, 1078 { X86::VPADDUSBYrr, X86::VPADDUSBYrm, 0 }, 1079 { X86::VPADDUSWYrr, X86::VPADDUSWYrm, 0 }, 1080 { X86::VPADDWYrr, X86::VPADDWYrm, 0 }, 1081 { X86::VPALIGNR256rr, X86::VPALIGNR256rm, 0 }, 1082 { X86::VPANDNYrr, X86::VPANDNYrm, 0 }, 1083 { X86::VPANDYrr, X86::VPANDYrm, 0 }, 1084 { X86::VPAVGBYrr, X86::VPAVGBYrm, 0 }, 1085 { X86::VPAVGWYrr, X86::VPAVGWYrm, 0 }, 1086 { X86::VPBLENDDrri, X86::VPBLENDDrmi, 0 }, 1087 { X86::VPBLENDDYrri, X86::VPBLENDDYrmi, 0 }, 1088 { X86::VPBLENDWYrri, X86::VPBLENDWYrmi, 0 }, 1089 { X86::VPCMPEQBYrr, X86::VPCMPEQBYrm, 0 }, 1090 { X86::VPCMPEQDYrr, X86::VPCMPEQDYrm, 0 }, 1091 { X86::VPCMPEQQYrr, X86::VPCMPEQQYrm, 0 }, 1092 { X86::VPCMPEQWYrr, X86::VPCMPEQWYrm, 0 }, 1093 { X86::VPCMPGTBYrr, X86::VPCMPGTBYrm, 0 }, 1094 { X86::VPCMPGTDYrr, X86::VPCMPGTDYrm, 0 }, 1095 { X86::VPCMPGTQYrr, X86::VPCMPGTQYrm, 0 }, 1096 { X86::VPCMPGTWYrr, X86::VPCMPGTWYrm, 0 }, 1097 { X86::VPERM2I128rr, X86::VPERM2I128rm, 0 }, 1098 { X86::VPERMDYrr, X86::VPERMDYrm, 0 }, 1099 { X86::VPERMPDYri, X86::VPERMPDYmi, 0 }, 1100 { X86::VPERMPSYrr, X86::VPERMPSYrm, 0 }, 1101 { X86::VPERMQYri, X86::VPERMQYmi, 0 }, 1102 { X86::VPHADDDYrr, X86::VPHADDDYrm, 0 }, 1103 { X86::VPHADDSWrr256, X86::VPHADDSWrm256, 0 }, 1104 { X86::VPHADDWYrr, X86::VPHADDWYrm, 0 }, 1105 { X86::VPHSUBDYrr, X86::VPHSUBDYrm, 0 }, 1106 { X86::VPHSUBSWrr256, X86::VPHSUBSWrm256, 0 }, 1107 { X86::VPHSUBWYrr, X86::VPHSUBWYrm, 0 }, 1108 { X86::VPMADDUBSWrr256, X86::VPMADDUBSWrm256, 0 }, 1109 { X86::VPMADDWDYrr, X86::VPMADDWDYrm, 0 }, 1110 { X86::VPMAXSWYrr, X86::VPMAXSWYrm, 0 }, 1111 { X86::VPMAXUBYrr, X86::VPMAXUBYrm, 0 }, 1112 { X86::VPMINSWYrr, X86::VPMINSWYrm, 0 }, 1113 { X86::VPMINUBYrr, X86::VPMINUBYrm, 0 }, 1114 { X86::VPMINSBYrr, X86::VPMINSBYrm, 0 }, 1115 { X86::VPMINSDYrr, X86::VPMINSDYrm, 0 }, 1116 { X86::VPMINUDYrr, X86::VPMINUDYrm, 0 }, 1117 { X86::VPMINUWYrr, X86::VPMINUWYrm, 0 }, 1118 { X86::VPMAXSBYrr, X86::VPMAXSBYrm, 0 }, 1119 { X86::VPMAXSDYrr, X86::VPMAXSDYrm, 0 }, 1120 { X86::VPMAXUDYrr, X86::VPMAXUDYrm, 0 }, 1121 { X86::VPMAXUWYrr, X86::VPMAXUWYrm, 0 }, 1122 { X86::VMPSADBWYrri, X86::VMPSADBWYrmi, 0 }, 1123 { X86::VPMULDQYrr, X86::VPMULDQYrm, 0 }, 1124 { X86::VPMULHRSWrr256, X86::VPMULHRSWrm256, 0 }, 1125 { X86::VPMULHUWYrr, X86::VPMULHUWYrm, 0 }, 1126 { X86::VPMULHWYrr, X86::VPMULHWYrm, 0 }, 1127 { X86::VPMULLDYrr, X86::VPMULLDYrm, 0 }, 1128 { X86::VPMULLWYrr, X86::VPMULLWYrm, 0 }, 1129 { X86::VPMULUDQYrr, X86::VPMULUDQYrm, 0 }, 1130 { X86::VPORYrr, X86::VPORYrm, 0 }, 1131 { X86::VPSADBWYrr, X86::VPSADBWYrm, 0 }, 1132 { X86::VPSHUFBYrr, X86::VPSHUFBYrm, 0 }, 1133 { X86::VPSIGNBYrr, X86::VPSIGNBYrm, 0 }, 1134 { X86::VPSIGNWYrr, X86::VPSIGNWYrm, 0 }, 1135 { X86::VPSIGNDYrr, X86::VPSIGNDYrm, 0 }, 1136 { X86::VPSLLDYrr, X86::VPSLLDYrm, 0 }, 1137 { X86::VPSLLQYrr, X86::VPSLLQYrm, 0 }, 1138 { X86::VPSLLWYrr, X86::VPSLLWYrm, 0 }, 1139 { X86::VPSLLVDrr, X86::VPSLLVDrm, 0 }, 1140 { X86::VPSLLVDYrr, X86::VPSLLVDYrm, 0 }, 1141 { X86::VPSLLVQrr, X86::VPSLLVQrm, 0 }, 1142 { X86::VPSLLVQYrr, X86::VPSLLVQYrm, 0 }, 1143 { X86::VPSRADYrr, X86::VPSRADYrm, 0 }, 1144 { X86::VPSRAWYrr, X86::VPSRAWYrm, 0 }, 1145 { X86::VPSRAVDrr, X86::VPSRAVDrm, 0 }, 1146 { X86::VPSRAVDYrr, X86::VPSRAVDYrm, 0 }, 1147 { X86::VPSRLDYrr, X86::VPSRLDYrm, 0 }, 1148 { X86::VPSRLQYrr, X86::VPSRLQYrm, 0 }, 1149 { X86::VPSRLWYrr, X86::VPSRLWYrm, 0 }, 1150 { X86::VPSRLVDrr, X86::VPSRLVDrm, 0 }, 1151 { X86::VPSRLVDYrr, X86::VPSRLVDYrm, 0 }, 1152 { X86::VPSRLVQrr, X86::VPSRLVQrm, 0 }, 1153 { X86::VPSRLVQYrr, X86::VPSRLVQYrm, 0 }, 1154 { X86::VPSUBBYrr, X86::VPSUBBYrm, 0 }, 1155 { X86::VPSUBDYrr, X86::VPSUBDYrm, 0 }, 1156 { X86::VPSUBSBYrr, X86::VPSUBSBYrm, 0 }, 1157 { X86::VPSUBSWYrr, X86::VPSUBSWYrm, 0 }, 1158 { X86::VPSUBWYrr, X86::VPSUBWYrm, 0 }, 1159 { X86::VPUNPCKHBWYrr, X86::VPUNPCKHBWYrm, 0 }, 1160 { X86::VPUNPCKHDQYrr, X86::VPUNPCKHDQYrm, 0 }, 1161 { X86::VPUNPCKHQDQYrr, X86::VPUNPCKHQDQYrm, 0 }, 1162 { X86::VPUNPCKHWDYrr, X86::VPUNPCKHWDYrm, 0 }, 1163 { X86::VPUNPCKLBWYrr, X86::VPUNPCKLBWYrm, 0 }, 1164 { X86::VPUNPCKLDQYrr, X86::VPUNPCKLDQYrm, 0 }, 1165 { X86::VPUNPCKLQDQYrr, X86::VPUNPCKLQDQYrm, 0 }, 1166 { X86::VPUNPCKLWDYrr, X86::VPUNPCKLWDYrm, 0 }, 1167 { X86::VPXORYrr, X86::VPXORYrm, 0 }, 1168 // FIXME: add AVX 256-bit foldable instructions 1169 1170 // FMA4 foldable patterns 1171 { X86::VFMADDSS4rr, X86::VFMADDSS4mr, 0 }, 1172 { X86::VFMADDSD4rr, X86::VFMADDSD4mr, 0 }, 1173 { X86::VFMADDPS4rr, X86::VFMADDPS4mr, TB_ALIGN_16 }, 1174 { X86::VFMADDPD4rr, X86::VFMADDPD4mr, TB_ALIGN_16 }, 1175 { X86::VFMADDPS4rrY, X86::VFMADDPS4mrY, TB_ALIGN_32 }, 1176 { X86::VFMADDPD4rrY, X86::VFMADDPD4mrY, TB_ALIGN_32 }, 1177 { X86::VFNMADDSS4rr, X86::VFNMADDSS4mr, 0 }, 1178 { X86::VFNMADDSD4rr, X86::VFNMADDSD4mr, 0 }, 1179 { X86::VFNMADDPS4rr, X86::VFNMADDPS4mr, TB_ALIGN_16 }, 1180 { X86::VFNMADDPD4rr, X86::VFNMADDPD4mr, TB_ALIGN_16 }, 1181 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4mrY, TB_ALIGN_32 }, 1182 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4mrY, TB_ALIGN_32 }, 1183 { X86::VFMSUBSS4rr, X86::VFMSUBSS4mr, 0 }, 1184 { X86::VFMSUBSD4rr, X86::VFMSUBSD4mr, 0 }, 1185 { X86::VFMSUBPS4rr, X86::VFMSUBPS4mr, TB_ALIGN_16 }, 1186 { X86::VFMSUBPD4rr, X86::VFMSUBPD4mr, TB_ALIGN_16 }, 1187 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4mrY, TB_ALIGN_32 }, 1188 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4mrY, TB_ALIGN_32 }, 1189 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4mr, 0 }, 1190 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4mr, 0 }, 1191 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4mr, TB_ALIGN_16 }, 1192 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4mr, TB_ALIGN_16 }, 1193 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4mrY, TB_ALIGN_32 }, 1194 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4mrY, TB_ALIGN_32 }, 1195 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4mr, TB_ALIGN_16 }, 1196 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4mr, TB_ALIGN_16 }, 1197 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4mrY, TB_ALIGN_32 }, 1198 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4mrY, TB_ALIGN_32 }, 1199 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4mr, TB_ALIGN_16 }, 1200 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4mr, TB_ALIGN_16 }, 1201 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4mrY, TB_ALIGN_32 }, 1202 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4mrY, TB_ALIGN_32 }, 1203 1204 // BMI/BMI2 foldable instructions 1205 { X86::ANDN32rr, X86::ANDN32rm, 0 }, 1206 { X86::ANDN64rr, X86::ANDN64rm, 0 }, 1207 { X86::MULX32rr, X86::MULX32rm, 0 }, 1208 { X86::MULX64rr, X86::MULX64rm, 0 }, 1209 { X86::PDEP32rr, X86::PDEP32rm, 0 }, 1210 { X86::PDEP64rr, X86::PDEP64rm, 0 }, 1211 { X86::PEXT32rr, X86::PEXT32rm, 0 }, 1212 { X86::PEXT64rr, X86::PEXT64rm, 0 }, 1213 1214 // AVX-512 foldable instructions 1215 { X86::VADDPSZrr, X86::VADDPSZrm, 0 }, 1216 { X86::VADDPDZrr, X86::VADDPDZrm, 0 }, 1217 { X86::VSUBPSZrr, X86::VSUBPSZrm, 0 }, 1218 { X86::VSUBPDZrr, X86::VSUBPDZrm, 0 }, 1219 { X86::VMULPSZrr, X86::VMULPSZrm, 0 }, 1220 { X86::VMULPDZrr, X86::VMULPDZrm, 0 }, 1221 { X86::VDIVPSZrr, X86::VDIVPSZrm, 0 }, 1222 { X86::VDIVPDZrr, X86::VDIVPDZrm, 0 }, 1223 { X86::VMINPSZrr, X86::VMINPSZrm, 0 }, 1224 { X86::VMINPDZrr, X86::VMINPDZrm, 0 }, 1225 { X86::VMAXPSZrr, X86::VMAXPSZrm, 0 }, 1226 { X86::VMAXPDZrr, X86::VMAXPDZrm, 0 }, 1227 { X86::VPADDDZrr, X86::VPADDDZrm, 0 }, 1228 { X86::VPADDQZrr, X86::VPADDQZrm, 0 }, 1229 { X86::VPERMPDZri, X86::VPERMPDZmi, 0 }, 1230 { X86::VPERMPSZrr, X86::VPERMPSZrm, 0 }, 1231 { X86::VPMAXSDZrr, X86::VPMAXSDZrm, 0 }, 1232 { X86::VPMAXSQZrr, X86::VPMAXSQZrm, 0 }, 1233 { X86::VPMAXUDZrr, X86::VPMAXUDZrm, 0 }, 1234 { X86::VPMAXUQZrr, X86::VPMAXUQZrm, 0 }, 1235 { X86::VPMINSDZrr, X86::VPMINSDZrm, 0 }, 1236 { X86::VPMINSQZrr, X86::VPMINSQZrm, 0 }, 1237 { X86::VPMINUDZrr, X86::VPMINUDZrm, 0 }, 1238 { X86::VPMINUQZrr, X86::VPMINUQZrm, 0 }, 1239 { X86::VPMULDQZrr, X86::VPMULDQZrm, 0 }, 1240 { X86::VPSLLVDZrr, X86::VPSLLVDZrm, 0 }, 1241 { X86::VPSLLVQZrr, X86::VPSLLVQZrm, 0 }, 1242 { X86::VPSRAVDZrr, X86::VPSRAVDZrm, 0 }, 1243 { X86::VPSRLVDZrr, X86::VPSRLVDZrm, 0 }, 1244 { X86::VPSRLVQZrr, X86::VPSRLVQZrm, 0 }, 1245 { X86::VPSUBDZrr, X86::VPSUBDZrm, 0 }, 1246 { X86::VPSUBQZrr, X86::VPSUBQZrm, 0 }, 1247 { X86::VSHUFPDZrri, X86::VSHUFPDZrmi, 0 }, 1248 { X86::VSHUFPSZrri, X86::VSHUFPSZrmi, 0 }, 1249 { X86::VALIGNQrri, X86::VALIGNQrmi, 0 }, 1250 { X86::VALIGNDrri, X86::VALIGNDrmi, 0 }, 1251 { X86::VPMULUDQZrr, X86::VPMULUDQZrm, 0 }, 1252 1253 // AES foldable instructions 1254 { X86::AESDECLASTrr, X86::AESDECLASTrm, TB_ALIGN_16 }, 1255 { X86::AESDECrr, X86::AESDECrm, TB_ALIGN_16 }, 1256 { X86::AESENCLASTrr, X86::AESENCLASTrm, TB_ALIGN_16 }, 1257 { X86::AESENCrr, X86::AESENCrm, TB_ALIGN_16 }, 1258 { X86::VAESDECLASTrr, X86::VAESDECLASTrm, TB_ALIGN_16 }, 1259 { X86::VAESDECrr, X86::VAESDECrm, TB_ALIGN_16 }, 1260 { X86::VAESENCLASTrr, X86::VAESENCLASTrm, TB_ALIGN_16 }, 1261 { X86::VAESENCrr, X86::VAESENCrm, TB_ALIGN_16 }, 1262 1263 // SHA foldable instructions 1264 { X86::SHA1MSG1rr, X86::SHA1MSG1rm, TB_ALIGN_16 }, 1265 { X86::SHA1MSG2rr, X86::SHA1MSG2rm, TB_ALIGN_16 }, 1266 { X86::SHA1NEXTErr, X86::SHA1NEXTErm, TB_ALIGN_16 }, 1267 { X86::SHA1RNDS4rri, X86::SHA1RNDS4rmi, TB_ALIGN_16 }, 1268 { X86::SHA256MSG1rr, X86::SHA256MSG1rm, TB_ALIGN_16 }, 1269 { X86::SHA256MSG2rr, X86::SHA256MSG2rm, TB_ALIGN_16 }, 1270 { X86::SHA256RNDS2rr, X86::SHA256RNDS2rm, TB_ALIGN_16 }, 1271 }; 1272 1273 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) { 1274 unsigned RegOp = OpTbl2[i].RegOp; 1275 unsigned MemOp = OpTbl2[i].MemOp; 1276 unsigned Flags = OpTbl2[i].Flags; 1277 AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable, 1278 RegOp, MemOp, 1279 // Index 2, folded load 1280 Flags | TB_INDEX_2 | TB_FOLDED_LOAD); 1281 } 1282 1283 static const X86OpTblEntry OpTbl3[] = { 1284 // FMA foldable instructions 1285 { X86::VFMADDSSr231r, X86::VFMADDSSr231m, TB_ALIGN_NONE }, 1286 { X86::VFMADDSDr231r, X86::VFMADDSDr231m, TB_ALIGN_NONE }, 1287 { X86::VFMADDSSr132r, X86::VFMADDSSr132m, TB_ALIGN_NONE }, 1288 { X86::VFMADDSDr132r, X86::VFMADDSDr132m, TB_ALIGN_NONE }, 1289 { X86::VFMADDSSr213r, X86::VFMADDSSr213m, TB_ALIGN_NONE }, 1290 { X86::VFMADDSDr213r, X86::VFMADDSDr213m, TB_ALIGN_NONE }, 1291 1292 { X86::VFMADDPSr231r, X86::VFMADDPSr231m, TB_ALIGN_NONE }, 1293 { X86::VFMADDPDr231r, X86::VFMADDPDr231m, TB_ALIGN_NONE }, 1294 { X86::VFMADDPSr132r, X86::VFMADDPSr132m, TB_ALIGN_NONE }, 1295 { X86::VFMADDPDr132r, X86::VFMADDPDr132m, TB_ALIGN_NONE }, 1296 { X86::VFMADDPSr213r, X86::VFMADDPSr213m, TB_ALIGN_NONE }, 1297 { X86::VFMADDPDr213r, X86::VFMADDPDr213m, TB_ALIGN_NONE }, 1298 { X86::VFMADDPSr231rY, X86::VFMADDPSr231mY, TB_ALIGN_NONE }, 1299 { X86::VFMADDPDr231rY, X86::VFMADDPDr231mY, TB_ALIGN_NONE }, 1300 { X86::VFMADDPSr132rY, X86::VFMADDPSr132mY, TB_ALIGN_NONE }, 1301 { X86::VFMADDPDr132rY, X86::VFMADDPDr132mY, TB_ALIGN_NONE }, 1302 { X86::VFMADDPSr213rY, X86::VFMADDPSr213mY, TB_ALIGN_NONE }, 1303 { X86::VFMADDPDr213rY, X86::VFMADDPDr213mY, TB_ALIGN_NONE }, 1304 1305 { X86::VFNMADDSSr231r, X86::VFNMADDSSr231m, TB_ALIGN_NONE }, 1306 { X86::VFNMADDSDr231r, X86::VFNMADDSDr231m, TB_ALIGN_NONE }, 1307 { X86::VFNMADDSSr132r, X86::VFNMADDSSr132m, TB_ALIGN_NONE }, 1308 { X86::VFNMADDSDr132r, X86::VFNMADDSDr132m, TB_ALIGN_NONE }, 1309 { X86::VFNMADDSSr213r, X86::VFNMADDSSr213m, TB_ALIGN_NONE }, 1310 { X86::VFNMADDSDr213r, X86::VFNMADDSDr213m, TB_ALIGN_NONE }, 1311 1312 { X86::VFNMADDPSr231r, X86::VFNMADDPSr231m, TB_ALIGN_NONE }, 1313 { X86::VFNMADDPDr231r, X86::VFNMADDPDr231m, TB_ALIGN_NONE }, 1314 { X86::VFNMADDPSr132r, X86::VFNMADDPSr132m, TB_ALIGN_NONE }, 1315 { X86::VFNMADDPDr132r, X86::VFNMADDPDr132m, TB_ALIGN_NONE }, 1316 { X86::VFNMADDPSr213r, X86::VFNMADDPSr213m, TB_ALIGN_NONE }, 1317 { X86::VFNMADDPDr213r, X86::VFNMADDPDr213m, TB_ALIGN_NONE }, 1318 { X86::VFNMADDPSr231rY, X86::VFNMADDPSr231mY, TB_ALIGN_NONE }, 1319 { X86::VFNMADDPDr231rY, X86::VFNMADDPDr231mY, TB_ALIGN_NONE }, 1320 { X86::VFNMADDPSr132rY, X86::VFNMADDPSr132mY, TB_ALIGN_NONE }, 1321 { X86::VFNMADDPDr132rY, X86::VFNMADDPDr132mY, TB_ALIGN_NONE }, 1322 { X86::VFNMADDPSr213rY, X86::VFNMADDPSr213mY, TB_ALIGN_NONE }, 1323 { X86::VFNMADDPDr213rY, X86::VFNMADDPDr213mY, TB_ALIGN_NONE }, 1324 1325 { X86::VFMSUBSSr231r, X86::VFMSUBSSr231m, TB_ALIGN_NONE }, 1326 { X86::VFMSUBSDr231r, X86::VFMSUBSDr231m, TB_ALIGN_NONE }, 1327 { X86::VFMSUBSSr132r, X86::VFMSUBSSr132m, TB_ALIGN_NONE }, 1328 { X86::VFMSUBSDr132r, X86::VFMSUBSDr132m, TB_ALIGN_NONE }, 1329 { X86::VFMSUBSSr213r, X86::VFMSUBSSr213m, TB_ALIGN_NONE }, 1330 { X86::VFMSUBSDr213r, X86::VFMSUBSDr213m, TB_ALIGN_NONE }, 1331 1332 { X86::VFMSUBPSr231r, X86::VFMSUBPSr231m, TB_ALIGN_NONE }, 1333 { X86::VFMSUBPDr231r, X86::VFMSUBPDr231m, TB_ALIGN_NONE }, 1334 { X86::VFMSUBPSr132r, X86::VFMSUBPSr132m, TB_ALIGN_NONE }, 1335 { X86::VFMSUBPDr132r, X86::VFMSUBPDr132m, TB_ALIGN_NONE }, 1336 { X86::VFMSUBPSr213r, X86::VFMSUBPSr213m, TB_ALIGN_NONE }, 1337 { X86::VFMSUBPDr213r, X86::VFMSUBPDr213m, TB_ALIGN_NONE }, 1338 { X86::VFMSUBPSr231rY, X86::VFMSUBPSr231mY, TB_ALIGN_NONE }, 1339 { X86::VFMSUBPDr231rY, X86::VFMSUBPDr231mY, TB_ALIGN_NONE }, 1340 { X86::VFMSUBPSr132rY, X86::VFMSUBPSr132mY, TB_ALIGN_NONE }, 1341 { X86::VFMSUBPDr132rY, X86::VFMSUBPDr132mY, TB_ALIGN_NONE }, 1342 { X86::VFMSUBPSr213rY, X86::VFMSUBPSr213mY, TB_ALIGN_NONE }, 1343 { X86::VFMSUBPDr213rY, X86::VFMSUBPDr213mY, TB_ALIGN_NONE }, 1344 1345 { X86::VFNMSUBSSr231r, X86::VFNMSUBSSr231m, TB_ALIGN_NONE }, 1346 { X86::VFNMSUBSDr231r, X86::VFNMSUBSDr231m, TB_ALIGN_NONE }, 1347 { X86::VFNMSUBSSr132r, X86::VFNMSUBSSr132m, TB_ALIGN_NONE }, 1348 { X86::VFNMSUBSDr132r, X86::VFNMSUBSDr132m, TB_ALIGN_NONE }, 1349 { X86::VFNMSUBSSr213r, X86::VFNMSUBSSr213m, TB_ALIGN_NONE }, 1350 { X86::VFNMSUBSDr213r, X86::VFNMSUBSDr213m, TB_ALIGN_NONE }, 1351 1352 { X86::VFNMSUBPSr231r, X86::VFNMSUBPSr231m, TB_ALIGN_NONE }, 1353 { X86::VFNMSUBPDr231r, X86::VFNMSUBPDr231m, TB_ALIGN_NONE }, 1354 { X86::VFNMSUBPSr132r, X86::VFNMSUBPSr132m, TB_ALIGN_NONE }, 1355 { X86::VFNMSUBPDr132r, X86::VFNMSUBPDr132m, TB_ALIGN_NONE }, 1356 { X86::VFNMSUBPSr213r, X86::VFNMSUBPSr213m, TB_ALIGN_NONE }, 1357 { X86::VFNMSUBPDr213r, X86::VFNMSUBPDr213m, TB_ALIGN_NONE }, 1358 { X86::VFNMSUBPSr231rY, X86::VFNMSUBPSr231mY, TB_ALIGN_NONE }, 1359 { X86::VFNMSUBPDr231rY, X86::VFNMSUBPDr231mY, TB_ALIGN_NONE }, 1360 { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr132mY, TB_ALIGN_NONE }, 1361 { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr132mY, TB_ALIGN_NONE }, 1362 { X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr213mY, TB_ALIGN_NONE }, 1363 { X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr213mY, TB_ALIGN_NONE }, 1364 1365 { X86::VFMADDSUBPSr231r, X86::VFMADDSUBPSr231m, TB_ALIGN_NONE }, 1366 { X86::VFMADDSUBPDr231r, X86::VFMADDSUBPDr231m, TB_ALIGN_NONE }, 1367 { X86::VFMADDSUBPSr132r, X86::VFMADDSUBPSr132m, TB_ALIGN_NONE }, 1368 { X86::VFMADDSUBPDr132r, X86::VFMADDSUBPDr132m, TB_ALIGN_NONE }, 1369 { X86::VFMADDSUBPSr213r, X86::VFMADDSUBPSr213m, TB_ALIGN_NONE }, 1370 { X86::VFMADDSUBPDr213r, X86::VFMADDSUBPDr213m, TB_ALIGN_NONE }, 1371 { X86::VFMADDSUBPSr231rY, X86::VFMADDSUBPSr231mY, TB_ALIGN_NONE }, 1372 { X86::VFMADDSUBPDr231rY, X86::VFMADDSUBPDr231mY, TB_ALIGN_NONE }, 1373 { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr132mY, TB_ALIGN_NONE }, 1374 { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr132mY, TB_ALIGN_NONE }, 1375 { X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr213mY, TB_ALIGN_NONE }, 1376 { X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr213mY, TB_ALIGN_NONE }, 1377 1378 { X86::VFMSUBADDPSr231r, X86::VFMSUBADDPSr231m, TB_ALIGN_NONE }, 1379 { X86::VFMSUBADDPDr231r, X86::VFMSUBADDPDr231m, TB_ALIGN_NONE }, 1380 { X86::VFMSUBADDPSr132r, X86::VFMSUBADDPSr132m, TB_ALIGN_NONE }, 1381 { X86::VFMSUBADDPDr132r, X86::VFMSUBADDPDr132m, TB_ALIGN_NONE }, 1382 { X86::VFMSUBADDPSr213r, X86::VFMSUBADDPSr213m, TB_ALIGN_NONE }, 1383 { X86::VFMSUBADDPDr213r, X86::VFMSUBADDPDr213m, TB_ALIGN_NONE }, 1384 { X86::VFMSUBADDPSr231rY, X86::VFMSUBADDPSr231mY, TB_ALIGN_NONE }, 1385 { X86::VFMSUBADDPDr231rY, X86::VFMSUBADDPDr231mY, TB_ALIGN_NONE }, 1386 { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr132mY, TB_ALIGN_NONE }, 1387 { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr132mY, TB_ALIGN_NONE }, 1388 { X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr213mY, TB_ALIGN_NONE }, 1389 { X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr213mY, TB_ALIGN_NONE }, 1390 1391 // FMA4 foldable patterns 1392 { X86::VFMADDSS4rr, X86::VFMADDSS4rm, 0 }, 1393 { X86::VFMADDSD4rr, X86::VFMADDSD4rm, 0 }, 1394 { X86::VFMADDPS4rr, X86::VFMADDPS4rm, TB_ALIGN_16 }, 1395 { X86::VFMADDPD4rr, X86::VFMADDPD4rm, TB_ALIGN_16 }, 1396 { X86::VFMADDPS4rrY, X86::VFMADDPS4rmY, TB_ALIGN_32 }, 1397 { X86::VFMADDPD4rrY, X86::VFMADDPD4rmY, TB_ALIGN_32 }, 1398 { X86::VFNMADDSS4rr, X86::VFNMADDSS4rm, 0 }, 1399 { X86::VFNMADDSD4rr, X86::VFNMADDSD4rm, 0 }, 1400 { X86::VFNMADDPS4rr, X86::VFNMADDPS4rm, TB_ALIGN_16 }, 1401 { X86::VFNMADDPD4rr, X86::VFNMADDPD4rm, TB_ALIGN_16 }, 1402 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4rmY, TB_ALIGN_32 }, 1403 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4rmY, TB_ALIGN_32 }, 1404 { X86::VFMSUBSS4rr, X86::VFMSUBSS4rm, 0 }, 1405 { X86::VFMSUBSD4rr, X86::VFMSUBSD4rm, 0 }, 1406 { X86::VFMSUBPS4rr, X86::VFMSUBPS4rm, TB_ALIGN_16 }, 1407 { X86::VFMSUBPD4rr, X86::VFMSUBPD4rm, TB_ALIGN_16 }, 1408 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4rmY, TB_ALIGN_32 }, 1409 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4rmY, TB_ALIGN_32 }, 1410 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4rm, 0 }, 1411 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4rm, 0 }, 1412 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4rm, TB_ALIGN_16 }, 1413 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4rm, TB_ALIGN_16 }, 1414 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4rmY, TB_ALIGN_32 }, 1415 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4rmY, TB_ALIGN_32 }, 1416 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4rm, TB_ALIGN_16 }, 1417 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4rm, TB_ALIGN_16 }, 1418 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4rmY, TB_ALIGN_32 }, 1419 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4rmY, TB_ALIGN_32 }, 1420 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4rm, TB_ALIGN_16 }, 1421 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4rm, TB_ALIGN_16 }, 1422 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4rmY, TB_ALIGN_32 }, 1423 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4rmY, TB_ALIGN_32 }, 1424 // AVX-512 VPERMI instructions with 3 source operands. 1425 { X86::VPERMI2Drr, X86::VPERMI2Drm, 0 }, 1426 { X86::VPERMI2Qrr, X86::VPERMI2Qrm, 0 }, 1427 { X86::VPERMI2PSrr, X86::VPERMI2PSrm, 0 }, 1428 { X86::VPERMI2PDrr, X86::VPERMI2PDrm, 0 }, 1429 { X86::VBLENDMPDZrr, X86::VBLENDMPDZrm, 0 }, 1430 { X86::VBLENDMPSZrr, X86::VBLENDMPSZrm, 0 }, 1431 { X86::VPBLENDMDZrr, X86::VPBLENDMDZrm, 0 }, 1432 { X86::VPBLENDMQZrr, X86::VPBLENDMQZrm, 0 } 1433 }; 1434 1435 for (unsigned i = 0, e = array_lengthof(OpTbl3); i != e; ++i) { 1436 unsigned RegOp = OpTbl3[i].RegOp; 1437 unsigned MemOp = OpTbl3[i].MemOp; 1438 unsigned Flags = OpTbl3[i].Flags; 1439 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable, 1440 RegOp, MemOp, 1441 // Index 3, folded load 1442 Flags | TB_INDEX_3 | TB_FOLDED_LOAD); 1443 } 1444 1445 } 1446 1447 void 1448 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable, 1449 MemOp2RegOpTableType &M2RTable, 1450 unsigned RegOp, unsigned MemOp, unsigned Flags) { 1451 if ((Flags & TB_NO_FORWARD) == 0) { 1452 assert(!R2MTable.count(RegOp) && "Duplicate entry!"); 1453 R2MTable[RegOp] = std::make_pair(MemOp, Flags); 1454 } 1455 if ((Flags & TB_NO_REVERSE) == 0) { 1456 assert(!M2RTable.count(MemOp) && 1457 "Duplicated entries in unfolding maps?"); 1458 M2RTable[MemOp] = std::make_pair(RegOp, Flags); 1459 } 1460 } 1461 1462 bool 1463 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI, 1464 unsigned &SrcReg, unsigned &DstReg, 1465 unsigned &SubIdx) const { 1466 switch (MI.getOpcode()) { 1467 default: break; 1468 case X86::MOVSX16rr8: 1469 case X86::MOVZX16rr8: 1470 case X86::MOVSX32rr8: 1471 case X86::MOVZX32rr8: 1472 case X86::MOVSX64rr8: 1473 if (!Subtarget.is64Bit()) 1474 // It's not always legal to reference the low 8-bit of the larger 1475 // register in 32-bit mode. 1476 return false; 1477 case X86::MOVSX32rr16: 1478 case X86::MOVZX32rr16: 1479 case X86::MOVSX64rr16: 1480 case X86::MOVSX64rr32: { 1481 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg()) 1482 // Be conservative. 1483 return false; 1484 SrcReg = MI.getOperand(1).getReg(); 1485 DstReg = MI.getOperand(0).getReg(); 1486 switch (MI.getOpcode()) { 1487 default: llvm_unreachable("Unreachable!"); 1488 case X86::MOVSX16rr8: 1489 case X86::MOVZX16rr8: 1490 case X86::MOVSX32rr8: 1491 case X86::MOVZX32rr8: 1492 case X86::MOVSX64rr8: 1493 SubIdx = X86::sub_8bit; 1494 break; 1495 case X86::MOVSX32rr16: 1496 case X86::MOVZX32rr16: 1497 case X86::MOVSX64rr16: 1498 SubIdx = X86::sub_16bit; 1499 break; 1500 case X86::MOVSX64rr32: 1501 SubIdx = X86::sub_32bit; 1502 break; 1503 } 1504 return true; 1505 } 1506 } 1507 return false; 1508 } 1509 1510 /// isFrameOperand - Return true and the FrameIndex if the specified 1511 /// operand and follow operands form a reference to the stack frame. 1512 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op, 1513 int &FrameIndex) const { 1514 if (MI->getOperand(Op+X86::AddrBaseReg).isFI() && 1515 MI->getOperand(Op+X86::AddrScaleAmt).isImm() && 1516 MI->getOperand(Op+X86::AddrIndexReg).isReg() && 1517 MI->getOperand(Op+X86::AddrDisp).isImm() && 1518 MI->getOperand(Op+X86::AddrScaleAmt).getImm() == 1 && 1519 MI->getOperand(Op+X86::AddrIndexReg).getReg() == 0 && 1520 MI->getOperand(Op+X86::AddrDisp).getImm() == 0) { 1521 FrameIndex = MI->getOperand(Op+X86::AddrBaseReg).getIndex(); 1522 return true; 1523 } 1524 return false; 1525 } 1526 1527 static bool isFrameLoadOpcode(int Opcode) { 1528 switch (Opcode) { 1529 default: 1530 return false; 1531 case X86::MOV8rm: 1532 case X86::MOV16rm: 1533 case X86::MOV32rm: 1534 case X86::MOV64rm: 1535 case X86::LD_Fp64m: 1536 case X86::MOVSSrm: 1537 case X86::MOVSDrm: 1538 case X86::MOVAPSrm: 1539 case X86::MOVAPDrm: 1540 case X86::MOVDQArm: 1541 case X86::VMOVSSrm: 1542 case X86::VMOVSDrm: 1543 case X86::VMOVAPSrm: 1544 case X86::VMOVAPDrm: 1545 case X86::VMOVDQArm: 1546 case X86::VMOVAPSYrm: 1547 case X86::VMOVAPDYrm: 1548 case X86::VMOVDQAYrm: 1549 case X86::MMX_MOVD64rm: 1550 case X86::MMX_MOVQ64rm: 1551 case X86::VMOVAPSZrm: 1552 case X86::VMOVUPSZrm: 1553 return true; 1554 } 1555 } 1556 1557 static bool isFrameStoreOpcode(int Opcode) { 1558 switch (Opcode) { 1559 default: break; 1560 case X86::MOV8mr: 1561 case X86::MOV16mr: 1562 case X86::MOV32mr: 1563 case X86::MOV64mr: 1564 case X86::ST_FpP64m: 1565 case X86::MOVSSmr: 1566 case X86::MOVSDmr: 1567 case X86::MOVAPSmr: 1568 case X86::MOVAPDmr: 1569 case X86::MOVDQAmr: 1570 case X86::VMOVSSmr: 1571 case X86::VMOVSDmr: 1572 case X86::VMOVAPSmr: 1573 case X86::VMOVAPDmr: 1574 case X86::VMOVDQAmr: 1575 case X86::VMOVAPSYmr: 1576 case X86::VMOVAPDYmr: 1577 case X86::VMOVDQAYmr: 1578 case X86::VMOVUPSZmr: 1579 case X86::VMOVAPSZmr: 1580 case X86::MMX_MOVD64mr: 1581 case X86::MMX_MOVQ64mr: 1582 case X86::MMX_MOVNTQmr: 1583 return true; 1584 } 1585 return false; 1586 } 1587 1588 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 1589 int &FrameIndex) const { 1590 if (isFrameLoadOpcode(MI->getOpcode())) 1591 if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex)) 1592 return MI->getOperand(0).getReg(); 1593 return 0; 1594 } 1595 1596 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, 1597 int &FrameIndex) const { 1598 if (isFrameLoadOpcode(MI->getOpcode())) { 1599 unsigned Reg; 1600 if ((Reg = isLoadFromStackSlot(MI, FrameIndex))) 1601 return Reg; 1602 // Check for post-frame index elimination operations 1603 const MachineMemOperand *Dummy; 1604 return hasLoadFromStackSlot(MI, Dummy, FrameIndex); 1605 } 1606 return 0; 1607 } 1608 1609 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI, 1610 int &FrameIndex) const { 1611 if (isFrameStoreOpcode(MI->getOpcode())) 1612 if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 && 1613 isFrameOperand(MI, 0, FrameIndex)) 1614 return MI->getOperand(X86::AddrNumOperands).getReg(); 1615 return 0; 1616 } 1617 1618 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI, 1619 int &FrameIndex) const { 1620 if (isFrameStoreOpcode(MI->getOpcode())) { 1621 unsigned Reg; 1622 if ((Reg = isStoreToStackSlot(MI, FrameIndex))) 1623 return Reg; 1624 // Check for post-frame index elimination operations 1625 const MachineMemOperand *Dummy; 1626 return hasStoreToStackSlot(MI, Dummy, FrameIndex); 1627 } 1628 return 0; 1629 } 1630 1631 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by 1632 /// X86::MOVPC32r. 1633 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) { 1634 // Don't waste compile time scanning use-def chains of physregs. 1635 if (!TargetRegisterInfo::isVirtualRegister(BaseReg)) 1636 return false; 1637 bool isPICBase = false; 1638 for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg), 1639 E = MRI.def_instr_end(); I != E; ++I) { 1640 MachineInstr *DefMI = &*I; 1641 if (DefMI->getOpcode() != X86::MOVPC32r) 1642 return false; 1643 assert(!isPICBase && "More than one PIC base?"); 1644 isPICBase = true; 1645 } 1646 return isPICBase; 1647 } 1648 1649 bool 1650 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI, 1651 AliasAnalysis *AA) const { 1652 switch (MI->getOpcode()) { 1653 default: break; 1654 case X86::MOV8rm: 1655 case X86::MOV16rm: 1656 case X86::MOV32rm: 1657 case X86::MOV64rm: 1658 case X86::LD_Fp64m: 1659 case X86::MOVSSrm: 1660 case X86::MOVSDrm: 1661 case X86::MOVAPSrm: 1662 case X86::MOVUPSrm: 1663 case X86::MOVAPDrm: 1664 case X86::MOVDQArm: 1665 case X86::MOVDQUrm: 1666 case X86::VMOVSSrm: 1667 case X86::VMOVSDrm: 1668 case X86::VMOVAPSrm: 1669 case X86::VMOVUPSrm: 1670 case X86::VMOVAPDrm: 1671 case X86::VMOVDQArm: 1672 case X86::VMOVDQUrm: 1673 case X86::VMOVAPSYrm: 1674 case X86::VMOVUPSYrm: 1675 case X86::VMOVAPDYrm: 1676 case X86::VMOVDQAYrm: 1677 case X86::VMOVDQUYrm: 1678 case X86::MMX_MOVD64rm: 1679 case X86::MMX_MOVQ64rm: 1680 case X86::FsVMOVAPSrm: 1681 case X86::FsVMOVAPDrm: 1682 case X86::FsMOVAPSrm: 1683 case X86::FsMOVAPDrm: { 1684 // Loads from constant pools are trivially rematerializable. 1685 if (MI->getOperand(1+X86::AddrBaseReg).isReg() && 1686 MI->getOperand(1+X86::AddrScaleAmt).isImm() && 1687 MI->getOperand(1+X86::AddrIndexReg).isReg() && 1688 MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 && 1689 MI->isInvariantLoad(AA)) { 1690 unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg(); 1691 if (BaseReg == 0 || BaseReg == X86::RIP) 1692 return true; 1693 // Allow re-materialization of PIC load. 1694 if (!ReMatPICStubLoad && MI->getOperand(1+X86::AddrDisp).isGlobal()) 1695 return false; 1696 const MachineFunction &MF = *MI->getParent()->getParent(); 1697 const MachineRegisterInfo &MRI = MF.getRegInfo(); 1698 return regIsPICBase(BaseReg, MRI); 1699 } 1700 return false; 1701 } 1702 1703 case X86::LEA32r: 1704 case X86::LEA64r: { 1705 if (MI->getOperand(1+X86::AddrScaleAmt).isImm() && 1706 MI->getOperand(1+X86::AddrIndexReg).isReg() && 1707 MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 && 1708 !MI->getOperand(1+X86::AddrDisp).isReg()) { 1709 // lea fi#, lea GV, etc. are all rematerializable. 1710 if (!MI->getOperand(1+X86::AddrBaseReg).isReg()) 1711 return true; 1712 unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg(); 1713 if (BaseReg == 0) 1714 return true; 1715 // Allow re-materialization of lea PICBase + x. 1716 const MachineFunction &MF = *MI->getParent()->getParent(); 1717 const MachineRegisterInfo &MRI = MF.getRegInfo(); 1718 return regIsPICBase(BaseReg, MRI); 1719 } 1720 return false; 1721 } 1722 } 1723 1724 // All other instructions marked M_REMATERIALIZABLE are always trivially 1725 // rematerializable. 1726 return true; 1727 } 1728 1729 bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB, 1730 MachineBasicBlock::iterator I) const { 1731 MachineBasicBlock::iterator E = MBB.end(); 1732 1733 // For compile time consideration, if we are not able to determine the 1734 // safety after visiting 4 instructions in each direction, we will assume 1735 // it's not safe. 1736 MachineBasicBlock::iterator Iter = I; 1737 for (unsigned i = 0; Iter != E && i < 4; ++i) { 1738 bool SeenDef = false; 1739 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) { 1740 MachineOperand &MO = Iter->getOperand(j); 1741 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS)) 1742 SeenDef = true; 1743 if (!MO.isReg()) 1744 continue; 1745 if (MO.getReg() == X86::EFLAGS) { 1746 if (MO.isUse()) 1747 return false; 1748 SeenDef = true; 1749 } 1750 } 1751 1752 if (SeenDef) 1753 // This instruction defines EFLAGS, no need to look any further. 1754 return true; 1755 ++Iter; 1756 // Skip over DBG_VALUE. 1757 while (Iter != E && Iter->isDebugValue()) 1758 ++Iter; 1759 } 1760 1761 // It is safe to clobber EFLAGS at the end of a block of no successor has it 1762 // live in. 1763 if (Iter == E) { 1764 for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(), 1765 SE = MBB.succ_end(); SI != SE; ++SI) 1766 if ((*SI)->isLiveIn(X86::EFLAGS)) 1767 return false; 1768 return true; 1769 } 1770 1771 MachineBasicBlock::iterator B = MBB.begin(); 1772 Iter = I; 1773 for (unsigned i = 0; i < 4; ++i) { 1774 // If we make it to the beginning of the block, it's safe to clobber 1775 // EFLAGS iff EFLAGS is not live-in. 1776 if (Iter == B) 1777 return !MBB.isLiveIn(X86::EFLAGS); 1778 1779 --Iter; 1780 // Skip over DBG_VALUE. 1781 while (Iter != B && Iter->isDebugValue()) 1782 --Iter; 1783 1784 bool SawKill = false; 1785 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) { 1786 MachineOperand &MO = Iter->getOperand(j); 1787 // A register mask may clobber EFLAGS, but we should still look for a 1788 // live EFLAGS def. 1789 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS)) 1790 SawKill = true; 1791 if (MO.isReg() && MO.getReg() == X86::EFLAGS) { 1792 if (MO.isDef()) return MO.isDead(); 1793 if (MO.isKill()) SawKill = true; 1794 } 1795 } 1796 1797 if (SawKill) 1798 // This instruction kills EFLAGS and doesn't redefine it, so 1799 // there's no need to look further. 1800 return true; 1801 } 1802 1803 // Conservative answer. 1804 return false; 1805 } 1806 1807 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB, 1808 MachineBasicBlock::iterator I, 1809 unsigned DestReg, unsigned SubIdx, 1810 const MachineInstr *Orig, 1811 const TargetRegisterInfo &TRI) const { 1812 // MOV32r0 is implemented with a xor which clobbers condition code. 1813 // Re-materialize it as movri instructions to avoid side effects. 1814 unsigned Opc = Orig->getOpcode(); 1815 if (Opc == X86::MOV32r0 && !isSafeToClobberEFLAGS(MBB, I)) { 1816 DebugLoc DL = Orig->getDebugLoc(); 1817 BuildMI(MBB, I, DL, get(X86::MOV32ri)).addOperand(Orig->getOperand(0)) 1818 .addImm(0); 1819 } else { 1820 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 1821 MBB.insert(I, MI); 1822 } 1823 1824 MachineInstr *NewMI = std::prev(I); 1825 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); 1826 } 1827 1828 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that 1829 /// is not marked dead. 1830 static bool hasLiveCondCodeDef(MachineInstr *MI) { 1831 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1832 MachineOperand &MO = MI->getOperand(i); 1833 if (MO.isReg() && MO.isDef() && 1834 MO.getReg() == X86::EFLAGS && !MO.isDead()) { 1835 return true; 1836 } 1837 } 1838 return false; 1839 } 1840 1841 /// getTruncatedShiftCount - check whether the shift count for a machine operand 1842 /// is non-zero. 1843 inline static unsigned getTruncatedShiftCount(MachineInstr *MI, 1844 unsigned ShiftAmtOperandIdx) { 1845 // The shift count is six bits with the REX.W prefix and five bits without. 1846 unsigned ShiftCountMask = (MI->getDesc().TSFlags & X86II::REX_W) ? 63 : 31; 1847 unsigned Imm = MI->getOperand(ShiftAmtOperandIdx).getImm(); 1848 return Imm & ShiftCountMask; 1849 } 1850 1851 /// isTruncatedShiftCountForLEA - check whether the given shift count is appropriate 1852 /// can be represented by a LEA instruction. 1853 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) { 1854 // Left shift instructions can be transformed into load-effective-address 1855 // instructions if we can encode them appropriately. 1856 // A LEA instruction utilizes a SIB byte to encode it's scale factor. 1857 // The SIB.scale field is two bits wide which means that we can encode any 1858 // shift amount less than 4. 1859 return ShAmt < 4 && ShAmt > 0; 1860 } 1861 1862 bool X86InstrInfo::classifyLEAReg(MachineInstr *MI, const MachineOperand &Src, 1863 unsigned Opc, bool AllowSP, 1864 unsigned &NewSrc, bool &isKill, bool &isUndef, 1865 MachineOperand &ImplicitOp) const { 1866 MachineFunction &MF = *MI->getParent()->getParent(); 1867 const TargetRegisterClass *RC; 1868 if (AllowSP) { 1869 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass; 1870 } else { 1871 RC = Opc != X86::LEA32r ? 1872 &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass; 1873 } 1874 unsigned SrcReg = Src.getReg(); 1875 1876 // For both LEA64 and LEA32 the register already has essentially the right 1877 // type (32-bit or 64-bit) we may just need to forbid SP. 1878 if (Opc != X86::LEA64_32r) { 1879 NewSrc = SrcReg; 1880 isKill = Src.isKill(); 1881 isUndef = Src.isUndef(); 1882 1883 if (TargetRegisterInfo::isVirtualRegister(NewSrc) && 1884 !MF.getRegInfo().constrainRegClass(NewSrc, RC)) 1885 return false; 1886 1887 return true; 1888 } 1889 1890 // This is for an LEA64_32r and incoming registers are 32-bit. One way or 1891 // another we need to add 64-bit registers to the final MI. 1892 if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) { 1893 ImplicitOp = Src; 1894 ImplicitOp.setImplicit(); 1895 1896 NewSrc = getX86SubSuperRegister(Src.getReg(), MVT::i64); 1897 MachineBasicBlock::LivenessQueryResult LQR = 1898 MI->getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI); 1899 1900 switch (LQR) { 1901 case MachineBasicBlock::LQR_Unknown: 1902 // We can't give sane liveness flags to the instruction, abandon LEA 1903 // formation. 1904 return false; 1905 case MachineBasicBlock::LQR_Live: 1906 isKill = MI->killsRegister(SrcReg); 1907 isUndef = false; 1908 break; 1909 default: 1910 // The physreg itself is dead, so we have to use it as an <undef>. 1911 isKill = false; 1912 isUndef = true; 1913 break; 1914 } 1915 } else { 1916 // Virtual register of the wrong class, we have to create a temporary 64-bit 1917 // vreg to feed into the LEA. 1918 NewSrc = MF.getRegInfo().createVirtualRegister(RC); 1919 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), 1920 get(TargetOpcode::COPY)) 1921 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit) 1922 .addOperand(Src); 1923 1924 // Which is obviously going to be dead after we're done with it. 1925 isKill = true; 1926 isUndef = false; 1927 } 1928 1929 // We've set all the parameters without issue. 1930 return true; 1931 } 1932 1933 /// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when 1934 /// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting 1935 /// to a 32-bit superregister and then truncating back down to a 16-bit 1936 /// subregister. 1937 MachineInstr * 1938 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc, 1939 MachineFunction::iterator &MFI, 1940 MachineBasicBlock::iterator &MBBI, 1941 LiveVariables *LV) const { 1942 MachineInstr *MI = MBBI; 1943 unsigned Dest = MI->getOperand(0).getReg(); 1944 unsigned Src = MI->getOperand(1).getReg(); 1945 bool isDead = MI->getOperand(0).isDead(); 1946 bool isKill = MI->getOperand(1).isKill(); 1947 1948 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo(); 1949 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass); 1950 unsigned Opc, leaInReg; 1951 if (Subtarget.is64Bit()) { 1952 Opc = X86::LEA64_32r; 1953 leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass); 1954 } else { 1955 Opc = X86::LEA32r; 1956 leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass); 1957 } 1958 1959 // Build and insert into an implicit UNDEF value. This is OK because 1960 // well be shifting and then extracting the lower 16-bits. 1961 // This has the potential to cause partial register stall. e.g. 1962 // movw (%rbp,%rcx,2), %dx 1963 // leal -65(%rdx), %esi 1964 // But testing has shown this *does* help performance in 64-bit mode (at 1965 // least on modern x86 machines). 1966 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg); 1967 MachineInstr *InsMI = 1968 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY)) 1969 .addReg(leaInReg, RegState::Define, X86::sub_16bit) 1970 .addReg(Src, getKillRegState(isKill)); 1971 1972 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(), 1973 get(Opc), leaOutReg); 1974 switch (MIOpc) { 1975 default: llvm_unreachable("Unreachable!"); 1976 case X86::SHL16ri: { 1977 unsigned ShAmt = MI->getOperand(2).getImm(); 1978 MIB.addReg(0).addImm(1 << ShAmt) 1979 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0); 1980 break; 1981 } 1982 case X86::INC16r: 1983 case X86::INC64_16r: 1984 addRegOffset(MIB, leaInReg, true, 1); 1985 break; 1986 case X86::DEC16r: 1987 case X86::DEC64_16r: 1988 addRegOffset(MIB, leaInReg, true, -1); 1989 break; 1990 case X86::ADD16ri: 1991 case X86::ADD16ri8: 1992 case X86::ADD16ri_DB: 1993 case X86::ADD16ri8_DB: 1994 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm()); 1995 break; 1996 case X86::ADD16rr: 1997 case X86::ADD16rr_DB: { 1998 unsigned Src2 = MI->getOperand(2).getReg(); 1999 bool isKill2 = MI->getOperand(2).isKill(); 2000 unsigned leaInReg2 = 0; 2001 MachineInstr *InsMI2 = nullptr; 2002 if (Src == Src2) { 2003 // ADD16rr %reg1028<kill>, %reg1028 2004 // just a single insert_subreg. 2005 addRegReg(MIB, leaInReg, true, leaInReg, false); 2006 } else { 2007 if (Subtarget.is64Bit()) 2008 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass); 2009 else 2010 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass); 2011 // Build and insert into an implicit UNDEF value. This is OK because 2012 // well be shifting and then extracting the lower 16-bits. 2013 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2); 2014 InsMI2 = 2015 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY)) 2016 .addReg(leaInReg2, RegState::Define, X86::sub_16bit) 2017 .addReg(Src2, getKillRegState(isKill2)); 2018 addRegReg(MIB, leaInReg, true, leaInReg2, true); 2019 } 2020 if (LV && isKill2 && InsMI2) 2021 LV->replaceKillInstruction(Src2, MI, InsMI2); 2022 break; 2023 } 2024 } 2025 2026 MachineInstr *NewMI = MIB; 2027 MachineInstr *ExtMI = 2028 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY)) 2029 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) 2030 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit); 2031 2032 if (LV) { 2033 // Update live variables 2034 LV->getVarInfo(leaInReg).Kills.push_back(NewMI); 2035 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI); 2036 if (isKill) 2037 LV->replaceKillInstruction(Src, MI, InsMI); 2038 if (isDead) 2039 LV->replaceKillInstruction(Dest, MI, ExtMI); 2040 } 2041 2042 return ExtMI; 2043 } 2044 2045 /// convertToThreeAddress - This method must be implemented by targets that 2046 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 2047 /// may be able to convert a two-address instruction into a true 2048 /// three-address instruction on demand. This allows the X86 target (for 2049 /// example) to convert ADD and SHL instructions into LEA instructions if they 2050 /// would require register copies due to two-addressness. 2051 /// 2052 /// This method returns a null pointer if the transformation cannot be 2053 /// performed, otherwise it returns the new instruction. 2054 /// 2055 MachineInstr * 2056 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 2057 MachineBasicBlock::iterator &MBBI, 2058 LiveVariables *LV) const { 2059 MachineInstr *MI = MBBI; 2060 2061 // The following opcodes also sets the condition code register(s). Only 2062 // convert them to equivalent lea if the condition code register def's 2063 // are dead! 2064 if (hasLiveCondCodeDef(MI)) 2065 return nullptr; 2066 2067 MachineFunction &MF = *MI->getParent()->getParent(); 2068 // All instructions input are two-addr instructions. Get the known operands. 2069 const MachineOperand &Dest = MI->getOperand(0); 2070 const MachineOperand &Src = MI->getOperand(1); 2071 2072 MachineInstr *NewMI = nullptr; 2073 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When 2074 // we have better subtarget support, enable the 16-bit LEA generation here. 2075 // 16-bit LEA is also slow on Core2. 2076 bool DisableLEA16 = true; 2077 bool is64Bit = Subtarget.is64Bit(); 2078 2079 unsigned MIOpc = MI->getOpcode(); 2080 switch (MIOpc) { 2081 case X86::SHUFPSrri: { 2082 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!"); 2083 if (!Subtarget.hasSSE2()) return nullptr; 2084 2085 unsigned B = MI->getOperand(1).getReg(); 2086 unsigned C = MI->getOperand(2).getReg(); 2087 if (B != C) return nullptr; 2088 unsigned M = MI->getOperand(3).getImm(); 2089 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri)) 2090 .addOperand(Dest).addOperand(Src).addImm(M); 2091 break; 2092 } 2093 case X86::SHUFPDrri: { 2094 assert(MI->getNumOperands() == 4 && "Unknown shufpd instruction!"); 2095 if (!Subtarget.hasSSE2()) return nullptr; 2096 2097 unsigned B = MI->getOperand(1).getReg(); 2098 unsigned C = MI->getOperand(2).getReg(); 2099 if (B != C) return nullptr; 2100 unsigned M = MI->getOperand(3).getImm(); 2101 2102 // Convert to PSHUFD mask. 2103 M = ((M & 1) << 1) | ((M & 1) << 3) | ((M & 2) << 4) | ((M & 2) << 6)| 0x44; 2104 2105 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri)) 2106 .addOperand(Dest).addOperand(Src).addImm(M); 2107 break; 2108 } 2109 case X86::SHL64ri: { 2110 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 2111 unsigned ShAmt = getTruncatedShiftCount(MI, 2); 2112 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr; 2113 2114 // LEA can't handle RSP. 2115 if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) && 2116 !MF.getRegInfo().constrainRegClass(Src.getReg(), 2117 &X86::GR64_NOSPRegClass)) 2118 return nullptr; 2119 2120 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r)) 2121 .addOperand(Dest) 2122 .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0); 2123 break; 2124 } 2125 case X86::SHL32ri: { 2126 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 2127 unsigned ShAmt = getTruncatedShiftCount(MI, 2); 2128 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr; 2129 2130 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 2131 2132 // LEA can't handle ESP. 2133 bool isKill, isUndef; 2134 unsigned SrcReg; 2135 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); 2136 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, 2137 SrcReg, isKill, isUndef, ImplicitOp)) 2138 return nullptr; 2139 2140 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc)) 2141 .addOperand(Dest) 2142 .addReg(0).addImm(1 << ShAmt) 2143 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef)) 2144 .addImm(0).addReg(0); 2145 if (ImplicitOp.getReg() != 0) 2146 MIB.addOperand(ImplicitOp); 2147 NewMI = MIB; 2148 2149 break; 2150 } 2151 case X86::SHL16ri: { 2152 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 2153 unsigned ShAmt = getTruncatedShiftCount(MI, 2); 2154 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr; 2155 2156 if (DisableLEA16) 2157 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : nullptr; 2158 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 2159 .addOperand(Dest) 2160 .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0); 2161 break; 2162 } 2163 default: { 2164 2165 switch (MIOpc) { 2166 default: return nullptr; 2167 case X86::INC64r: 2168 case X86::INC32r: 2169 case X86::INC64_32r: { 2170 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); 2171 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r 2172 : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 2173 bool isKill, isUndef; 2174 unsigned SrcReg; 2175 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); 2176 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, 2177 SrcReg, isKill, isUndef, ImplicitOp)) 2178 return nullptr; 2179 2180 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc)) 2181 .addOperand(Dest) 2182 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef)); 2183 if (ImplicitOp.getReg() != 0) 2184 MIB.addOperand(ImplicitOp); 2185 2186 NewMI = addOffset(MIB, 1); 2187 break; 2188 } 2189 case X86::INC16r: 2190 case X86::INC64_16r: 2191 if (DisableLEA16) 2192 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) 2193 : nullptr; 2194 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); 2195 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 2196 .addOperand(Dest).addOperand(Src), 1); 2197 break; 2198 case X86::DEC64r: 2199 case X86::DEC32r: 2200 case X86::DEC64_32r: { 2201 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); 2202 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r 2203 : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 2204 2205 bool isKill, isUndef; 2206 unsigned SrcReg; 2207 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); 2208 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, 2209 SrcReg, isKill, isUndef, ImplicitOp)) 2210 return nullptr; 2211 2212 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc)) 2213 .addOperand(Dest) 2214 .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill)); 2215 if (ImplicitOp.getReg() != 0) 2216 MIB.addOperand(ImplicitOp); 2217 2218 NewMI = addOffset(MIB, -1); 2219 2220 break; 2221 } 2222 case X86::DEC16r: 2223 case X86::DEC64_16r: 2224 if (DisableLEA16) 2225 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) 2226 : nullptr; 2227 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); 2228 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 2229 .addOperand(Dest).addOperand(Src), -1); 2230 break; 2231 case X86::ADD64rr: 2232 case X86::ADD64rr_DB: 2233 case X86::ADD32rr: 2234 case X86::ADD32rr_DB: { 2235 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2236 unsigned Opc; 2237 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB) 2238 Opc = X86::LEA64r; 2239 else 2240 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 2241 2242 bool isKill, isUndef; 2243 unsigned SrcReg; 2244 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); 2245 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true, 2246 SrcReg, isKill, isUndef, ImplicitOp)) 2247 return nullptr; 2248 2249 const MachineOperand &Src2 = MI->getOperand(2); 2250 bool isKill2, isUndef2; 2251 unsigned SrcReg2; 2252 MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false); 2253 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false, 2254 SrcReg2, isKill2, isUndef2, ImplicitOp2)) 2255 return nullptr; 2256 2257 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc)) 2258 .addOperand(Dest); 2259 if (ImplicitOp.getReg() != 0) 2260 MIB.addOperand(ImplicitOp); 2261 if (ImplicitOp2.getReg() != 0) 2262 MIB.addOperand(ImplicitOp2); 2263 2264 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2); 2265 2266 // Preserve undefness of the operands. 2267 NewMI->getOperand(1).setIsUndef(isUndef); 2268 NewMI->getOperand(3).setIsUndef(isUndef2); 2269 2270 if (LV && Src2.isKill()) 2271 LV->replaceKillInstruction(SrcReg2, MI, NewMI); 2272 break; 2273 } 2274 case X86::ADD16rr: 2275 case X86::ADD16rr_DB: { 2276 if (DisableLEA16) 2277 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) 2278 : nullptr; 2279 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2280 unsigned Src2 = MI->getOperand(2).getReg(); 2281 bool isKill2 = MI->getOperand(2).isKill(); 2282 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 2283 .addOperand(Dest), 2284 Src.getReg(), Src.isKill(), Src2, isKill2); 2285 2286 // Preserve undefness of the operands. 2287 bool isUndef = MI->getOperand(1).isUndef(); 2288 bool isUndef2 = MI->getOperand(2).isUndef(); 2289 NewMI->getOperand(1).setIsUndef(isUndef); 2290 NewMI->getOperand(3).setIsUndef(isUndef2); 2291 2292 if (LV && isKill2) 2293 LV->replaceKillInstruction(Src2, MI, NewMI); 2294 break; 2295 } 2296 case X86::ADD64ri32: 2297 case X86::ADD64ri8: 2298 case X86::ADD64ri32_DB: 2299 case X86::ADD64ri8_DB: 2300 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2301 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r)) 2302 .addOperand(Dest).addOperand(Src), 2303 MI->getOperand(2).getImm()); 2304 break; 2305 case X86::ADD32ri: 2306 case X86::ADD32ri8: 2307 case X86::ADD32ri_DB: 2308 case X86::ADD32ri8_DB: { 2309 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2310 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 2311 2312 bool isKill, isUndef; 2313 unsigned SrcReg; 2314 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); 2315 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true, 2316 SrcReg, isKill, isUndef, ImplicitOp)) 2317 return nullptr; 2318 2319 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc)) 2320 .addOperand(Dest) 2321 .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill)); 2322 if (ImplicitOp.getReg() != 0) 2323 MIB.addOperand(ImplicitOp); 2324 2325 NewMI = addOffset(MIB, MI->getOperand(2).getImm()); 2326 break; 2327 } 2328 case X86::ADD16ri: 2329 case X86::ADD16ri8: 2330 case X86::ADD16ri_DB: 2331 case X86::ADD16ri8_DB: 2332 if (DisableLEA16) 2333 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) 2334 : nullptr; 2335 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2336 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 2337 .addOperand(Dest).addOperand(Src), 2338 MI->getOperand(2).getImm()); 2339 break; 2340 } 2341 } 2342 } 2343 2344 if (!NewMI) return nullptr; 2345 2346 if (LV) { // Update live variables 2347 if (Src.isKill()) 2348 LV->replaceKillInstruction(Src.getReg(), MI, NewMI); 2349 if (Dest.isDead()) 2350 LV->replaceKillInstruction(Dest.getReg(), MI, NewMI); 2351 } 2352 2353 MFI->insert(MBBI, NewMI); // Insert the new inst 2354 return NewMI; 2355 } 2356 2357 /// commuteInstruction - We have a few instructions that must be hacked on to 2358 /// commute them. 2359 /// 2360 MachineInstr * 2361 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { 2362 switch (MI->getOpcode()) { 2363 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I) 2364 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I) 2365 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I) 2366 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I) 2367 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I) 2368 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I) 2369 unsigned Opc; 2370 unsigned Size; 2371 switch (MI->getOpcode()) { 2372 default: llvm_unreachable("Unreachable!"); 2373 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break; 2374 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break; 2375 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break; 2376 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break; 2377 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break; 2378 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break; 2379 } 2380 unsigned Amt = MI->getOperand(3).getImm(); 2381 if (NewMI) { 2382 MachineFunction &MF = *MI->getParent()->getParent(); 2383 MI = MF.CloneMachineInstr(MI); 2384 NewMI = false; 2385 } 2386 MI->setDesc(get(Opc)); 2387 MI->getOperand(3).setImm(Size-Amt); 2388 return TargetInstrInfo::commuteInstruction(MI, NewMI); 2389 } 2390 case X86::CMOVB16rr: case X86::CMOVB32rr: case X86::CMOVB64rr: 2391 case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr: 2392 case X86::CMOVE16rr: case X86::CMOVE32rr: case X86::CMOVE64rr: 2393 case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr: 2394 case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr: 2395 case X86::CMOVA16rr: case X86::CMOVA32rr: case X86::CMOVA64rr: 2396 case X86::CMOVL16rr: case X86::CMOVL32rr: case X86::CMOVL64rr: 2397 case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr: 2398 case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr: 2399 case X86::CMOVG16rr: case X86::CMOVG32rr: case X86::CMOVG64rr: 2400 case X86::CMOVS16rr: case X86::CMOVS32rr: case X86::CMOVS64rr: 2401 case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr: 2402 case X86::CMOVP16rr: case X86::CMOVP32rr: case X86::CMOVP64rr: 2403 case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr: 2404 case X86::CMOVO16rr: case X86::CMOVO32rr: case X86::CMOVO64rr: 2405 case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: { 2406 unsigned Opc; 2407 switch (MI->getOpcode()) { 2408 default: llvm_unreachable("Unreachable!"); 2409 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break; 2410 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break; 2411 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break; 2412 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break; 2413 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break; 2414 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break; 2415 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break; 2416 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break; 2417 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break; 2418 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break; 2419 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break; 2420 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break; 2421 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break; 2422 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break; 2423 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break; 2424 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break; 2425 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break; 2426 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break; 2427 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break; 2428 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break; 2429 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break; 2430 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break; 2431 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break; 2432 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break; 2433 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break; 2434 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break; 2435 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break; 2436 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break; 2437 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break; 2438 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break; 2439 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break; 2440 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break; 2441 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break; 2442 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break; 2443 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break; 2444 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break; 2445 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break; 2446 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break; 2447 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break; 2448 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break; 2449 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break; 2450 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break; 2451 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break; 2452 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break; 2453 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break; 2454 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break; 2455 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break; 2456 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break; 2457 } 2458 if (NewMI) { 2459 MachineFunction &MF = *MI->getParent()->getParent(); 2460 MI = MF.CloneMachineInstr(MI); 2461 NewMI = false; 2462 } 2463 MI->setDesc(get(Opc)); 2464 // Fallthrough intended. 2465 } 2466 default: 2467 return TargetInstrInfo::commuteInstruction(MI, NewMI); 2468 } 2469 } 2470 2471 bool X86InstrInfo::findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 2472 unsigned &SrcOpIdx2) const { 2473 switch (MI->getOpcode()) { 2474 case X86::VFMADDPDr231r: 2475 case X86::VFMADDPSr231r: 2476 case X86::VFMADDSDr231r: 2477 case X86::VFMADDSSr231r: 2478 case X86::VFMSUBPDr231r: 2479 case X86::VFMSUBPSr231r: 2480 case X86::VFMSUBSDr231r: 2481 case X86::VFMSUBSSr231r: 2482 case X86::VFNMADDPDr231r: 2483 case X86::VFNMADDPSr231r: 2484 case X86::VFNMADDSDr231r: 2485 case X86::VFNMADDSSr231r: 2486 case X86::VFNMSUBPDr231r: 2487 case X86::VFNMSUBPSr231r: 2488 case X86::VFNMSUBSDr231r: 2489 case X86::VFNMSUBSSr231r: 2490 case X86::VFMADDPDr231rY: 2491 case X86::VFMADDPSr231rY: 2492 case X86::VFMSUBPDr231rY: 2493 case X86::VFMSUBPSr231rY: 2494 case X86::VFNMADDPDr231rY: 2495 case X86::VFNMADDPSr231rY: 2496 case X86::VFNMSUBPDr231rY: 2497 case X86::VFNMSUBPSr231rY: 2498 SrcOpIdx1 = 2; 2499 SrcOpIdx2 = 3; 2500 return true; 2501 default: 2502 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2); 2503 } 2504 } 2505 2506 static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) { 2507 switch (BrOpc) { 2508 default: return X86::COND_INVALID; 2509 case X86::JE_4: return X86::COND_E; 2510 case X86::JNE_4: return X86::COND_NE; 2511 case X86::JL_4: return X86::COND_L; 2512 case X86::JLE_4: return X86::COND_LE; 2513 case X86::JG_4: return X86::COND_G; 2514 case X86::JGE_4: return X86::COND_GE; 2515 case X86::JB_4: return X86::COND_B; 2516 case X86::JBE_4: return X86::COND_BE; 2517 case X86::JA_4: return X86::COND_A; 2518 case X86::JAE_4: return X86::COND_AE; 2519 case X86::JS_4: return X86::COND_S; 2520 case X86::JNS_4: return X86::COND_NS; 2521 case X86::JP_4: return X86::COND_P; 2522 case X86::JNP_4: return X86::COND_NP; 2523 case X86::JO_4: return X86::COND_O; 2524 case X86::JNO_4: return X86::COND_NO; 2525 } 2526 } 2527 2528 /// getCondFromSETOpc - return condition code of a SET opcode. 2529 static X86::CondCode getCondFromSETOpc(unsigned Opc) { 2530 switch (Opc) { 2531 default: return X86::COND_INVALID; 2532 case X86::SETAr: case X86::SETAm: return X86::COND_A; 2533 case X86::SETAEr: case X86::SETAEm: return X86::COND_AE; 2534 case X86::SETBr: case X86::SETBm: return X86::COND_B; 2535 case X86::SETBEr: case X86::SETBEm: return X86::COND_BE; 2536 case X86::SETEr: case X86::SETEm: return X86::COND_E; 2537 case X86::SETGr: case X86::SETGm: return X86::COND_G; 2538 case X86::SETGEr: case X86::SETGEm: return X86::COND_GE; 2539 case X86::SETLr: case X86::SETLm: return X86::COND_L; 2540 case X86::SETLEr: case X86::SETLEm: return X86::COND_LE; 2541 case X86::SETNEr: case X86::SETNEm: return X86::COND_NE; 2542 case X86::SETNOr: case X86::SETNOm: return X86::COND_NO; 2543 case X86::SETNPr: case X86::SETNPm: return X86::COND_NP; 2544 case X86::SETNSr: case X86::SETNSm: return X86::COND_NS; 2545 case X86::SETOr: case X86::SETOm: return X86::COND_O; 2546 case X86::SETPr: case X86::SETPm: return X86::COND_P; 2547 case X86::SETSr: case X86::SETSm: return X86::COND_S; 2548 } 2549 } 2550 2551 /// getCondFromCmovOpc - return condition code of a CMov opcode. 2552 X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) { 2553 switch (Opc) { 2554 default: return X86::COND_INVALID; 2555 case X86::CMOVA16rm: case X86::CMOVA16rr: case X86::CMOVA32rm: 2556 case X86::CMOVA32rr: case X86::CMOVA64rm: case X86::CMOVA64rr: 2557 return X86::COND_A; 2558 case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm: 2559 case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr: 2560 return X86::COND_AE; 2561 case X86::CMOVB16rm: case X86::CMOVB16rr: case X86::CMOVB32rm: 2562 case X86::CMOVB32rr: case X86::CMOVB64rm: case X86::CMOVB64rr: 2563 return X86::COND_B; 2564 case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm: 2565 case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr: 2566 return X86::COND_BE; 2567 case X86::CMOVE16rm: case X86::CMOVE16rr: case X86::CMOVE32rm: 2568 case X86::CMOVE32rr: case X86::CMOVE64rm: case X86::CMOVE64rr: 2569 return X86::COND_E; 2570 case X86::CMOVG16rm: case X86::CMOVG16rr: case X86::CMOVG32rm: 2571 case X86::CMOVG32rr: case X86::CMOVG64rm: case X86::CMOVG64rr: 2572 return X86::COND_G; 2573 case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm: 2574 case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr: 2575 return X86::COND_GE; 2576 case X86::CMOVL16rm: case X86::CMOVL16rr: case X86::CMOVL32rm: 2577 case X86::CMOVL32rr: case X86::CMOVL64rm: case X86::CMOVL64rr: 2578 return X86::COND_L; 2579 case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm: 2580 case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr: 2581 return X86::COND_LE; 2582 case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm: 2583 case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr: 2584 return X86::COND_NE; 2585 case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm: 2586 case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr: 2587 return X86::COND_NO; 2588 case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm: 2589 case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr: 2590 return X86::COND_NP; 2591 case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm: 2592 case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr: 2593 return X86::COND_NS; 2594 case X86::CMOVO16rm: case X86::CMOVO16rr: case X86::CMOVO32rm: 2595 case X86::CMOVO32rr: case X86::CMOVO64rm: case X86::CMOVO64rr: 2596 return X86::COND_O; 2597 case X86::CMOVP16rm: case X86::CMOVP16rr: case X86::CMOVP32rm: 2598 case X86::CMOVP32rr: case X86::CMOVP64rm: case X86::CMOVP64rr: 2599 return X86::COND_P; 2600 case X86::CMOVS16rm: case X86::CMOVS16rr: case X86::CMOVS32rm: 2601 case X86::CMOVS32rr: case X86::CMOVS64rm: case X86::CMOVS64rr: 2602 return X86::COND_S; 2603 } 2604 } 2605 2606 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) { 2607 switch (CC) { 2608 default: llvm_unreachable("Illegal condition code!"); 2609 case X86::COND_E: return X86::JE_4; 2610 case X86::COND_NE: return X86::JNE_4; 2611 case X86::COND_L: return X86::JL_4; 2612 case X86::COND_LE: return X86::JLE_4; 2613 case X86::COND_G: return X86::JG_4; 2614 case X86::COND_GE: return X86::JGE_4; 2615 case X86::COND_B: return X86::JB_4; 2616 case X86::COND_BE: return X86::JBE_4; 2617 case X86::COND_A: return X86::JA_4; 2618 case X86::COND_AE: return X86::JAE_4; 2619 case X86::COND_S: return X86::JS_4; 2620 case X86::COND_NS: return X86::JNS_4; 2621 case X86::COND_P: return X86::JP_4; 2622 case X86::COND_NP: return X86::JNP_4; 2623 case X86::COND_O: return X86::JO_4; 2624 case X86::COND_NO: return X86::JNO_4; 2625 } 2626 } 2627 2628 /// GetOppositeBranchCondition - Return the inverse of the specified condition, 2629 /// e.g. turning COND_E to COND_NE. 2630 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) { 2631 switch (CC) { 2632 default: llvm_unreachable("Illegal condition code!"); 2633 case X86::COND_E: return X86::COND_NE; 2634 case X86::COND_NE: return X86::COND_E; 2635 case X86::COND_L: return X86::COND_GE; 2636 case X86::COND_LE: return X86::COND_G; 2637 case X86::COND_G: return X86::COND_LE; 2638 case X86::COND_GE: return X86::COND_L; 2639 case X86::COND_B: return X86::COND_AE; 2640 case X86::COND_BE: return X86::COND_A; 2641 case X86::COND_A: return X86::COND_BE; 2642 case X86::COND_AE: return X86::COND_B; 2643 case X86::COND_S: return X86::COND_NS; 2644 case X86::COND_NS: return X86::COND_S; 2645 case X86::COND_P: return X86::COND_NP; 2646 case X86::COND_NP: return X86::COND_P; 2647 case X86::COND_O: return X86::COND_NO; 2648 case X86::COND_NO: return X86::COND_O; 2649 } 2650 } 2651 2652 /// getSwappedCondition - assume the flags are set by MI(a,b), return 2653 /// the condition code if we modify the instructions such that flags are 2654 /// set by MI(b,a). 2655 static X86::CondCode getSwappedCondition(X86::CondCode CC) { 2656 switch (CC) { 2657 default: return X86::COND_INVALID; 2658 case X86::COND_E: return X86::COND_E; 2659 case X86::COND_NE: return X86::COND_NE; 2660 case X86::COND_L: return X86::COND_G; 2661 case X86::COND_LE: return X86::COND_GE; 2662 case X86::COND_G: return X86::COND_L; 2663 case X86::COND_GE: return X86::COND_LE; 2664 case X86::COND_B: return X86::COND_A; 2665 case X86::COND_BE: return X86::COND_AE; 2666 case X86::COND_A: return X86::COND_B; 2667 case X86::COND_AE: return X86::COND_BE; 2668 } 2669 } 2670 2671 /// getSETFromCond - Return a set opcode for the given condition and 2672 /// whether it has memory operand. 2673 unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) { 2674 static const uint16_t Opc[16][2] = { 2675 { X86::SETAr, X86::SETAm }, 2676 { X86::SETAEr, X86::SETAEm }, 2677 { X86::SETBr, X86::SETBm }, 2678 { X86::SETBEr, X86::SETBEm }, 2679 { X86::SETEr, X86::SETEm }, 2680 { X86::SETGr, X86::SETGm }, 2681 { X86::SETGEr, X86::SETGEm }, 2682 { X86::SETLr, X86::SETLm }, 2683 { X86::SETLEr, X86::SETLEm }, 2684 { X86::SETNEr, X86::SETNEm }, 2685 { X86::SETNOr, X86::SETNOm }, 2686 { X86::SETNPr, X86::SETNPm }, 2687 { X86::SETNSr, X86::SETNSm }, 2688 { X86::SETOr, X86::SETOm }, 2689 { X86::SETPr, X86::SETPm }, 2690 { X86::SETSr, X86::SETSm } 2691 }; 2692 2693 assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes"); 2694 return Opc[CC][HasMemoryOperand ? 1 : 0]; 2695 } 2696 2697 /// getCMovFromCond - Return a cmov opcode for the given condition, 2698 /// register size in bytes, and operand type. 2699 unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes, 2700 bool HasMemoryOperand) { 2701 static const uint16_t Opc[32][3] = { 2702 { X86::CMOVA16rr, X86::CMOVA32rr, X86::CMOVA64rr }, 2703 { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr }, 2704 { X86::CMOVB16rr, X86::CMOVB32rr, X86::CMOVB64rr }, 2705 { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr }, 2706 { X86::CMOVE16rr, X86::CMOVE32rr, X86::CMOVE64rr }, 2707 { X86::CMOVG16rr, X86::CMOVG32rr, X86::CMOVG64rr }, 2708 { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr }, 2709 { X86::CMOVL16rr, X86::CMOVL32rr, X86::CMOVL64rr }, 2710 { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr }, 2711 { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr }, 2712 { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr }, 2713 { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr }, 2714 { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr }, 2715 { X86::CMOVO16rr, X86::CMOVO32rr, X86::CMOVO64rr }, 2716 { X86::CMOVP16rr, X86::CMOVP32rr, X86::CMOVP64rr }, 2717 { X86::CMOVS16rr, X86::CMOVS32rr, X86::CMOVS64rr }, 2718 { X86::CMOVA16rm, X86::CMOVA32rm, X86::CMOVA64rm }, 2719 { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm }, 2720 { X86::CMOVB16rm, X86::CMOVB32rm, X86::CMOVB64rm }, 2721 { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm }, 2722 { X86::CMOVE16rm, X86::CMOVE32rm, X86::CMOVE64rm }, 2723 { X86::CMOVG16rm, X86::CMOVG32rm, X86::CMOVG64rm }, 2724 { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm }, 2725 { X86::CMOVL16rm, X86::CMOVL32rm, X86::CMOVL64rm }, 2726 { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm }, 2727 { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm }, 2728 { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm }, 2729 { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm }, 2730 { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm }, 2731 { X86::CMOVO16rm, X86::CMOVO32rm, X86::CMOVO64rm }, 2732 { X86::CMOVP16rm, X86::CMOVP32rm, X86::CMOVP64rm }, 2733 { X86::CMOVS16rm, X86::CMOVS32rm, X86::CMOVS64rm } 2734 }; 2735 2736 assert(CC < 16 && "Can only handle standard cond codes"); 2737 unsigned Idx = HasMemoryOperand ? 16+CC : CC; 2738 switch(RegBytes) { 2739 default: llvm_unreachable("Illegal register size!"); 2740 case 2: return Opc[Idx][0]; 2741 case 4: return Opc[Idx][1]; 2742 case 8: return Opc[Idx][2]; 2743 } 2744 } 2745 2746 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { 2747 if (!MI->isTerminator()) return false; 2748 2749 // Conditional branch is a special case. 2750 if (MI->isBranch() && !MI->isBarrier()) 2751 return true; 2752 if (!MI->isPredicable()) 2753 return true; 2754 return !isPredicated(MI); 2755 } 2756 2757 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 2758 MachineBasicBlock *&TBB, 2759 MachineBasicBlock *&FBB, 2760 SmallVectorImpl<MachineOperand> &Cond, 2761 bool AllowModify) const { 2762 // Start from the bottom of the block and work up, examining the 2763 // terminator instructions. 2764 MachineBasicBlock::iterator I = MBB.end(); 2765 MachineBasicBlock::iterator UnCondBrIter = MBB.end(); 2766 while (I != MBB.begin()) { 2767 --I; 2768 if (I->isDebugValue()) 2769 continue; 2770 2771 // Working from the bottom, when we see a non-terminator instruction, we're 2772 // done. 2773 if (!isUnpredicatedTerminator(I)) 2774 break; 2775 2776 // A terminator that isn't a branch can't easily be handled by this 2777 // analysis. 2778 if (!I->isBranch()) 2779 return true; 2780 2781 // Handle unconditional branches. 2782 if (I->getOpcode() == X86::JMP_4) { 2783 UnCondBrIter = I; 2784 2785 if (!AllowModify) { 2786 TBB = I->getOperand(0).getMBB(); 2787 continue; 2788 } 2789 2790 // If the block has any instructions after a JMP, delete them. 2791 while (std::next(I) != MBB.end()) 2792 std::next(I)->eraseFromParent(); 2793 2794 Cond.clear(); 2795 FBB = nullptr; 2796 2797 // Delete the JMP if it's equivalent to a fall-through. 2798 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) { 2799 TBB = nullptr; 2800 I->eraseFromParent(); 2801 I = MBB.end(); 2802 UnCondBrIter = MBB.end(); 2803 continue; 2804 } 2805 2806 // TBB is used to indicate the unconditional destination. 2807 TBB = I->getOperand(0).getMBB(); 2808 continue; 2809 } 2810 2811 // Handle conditional branches. 2812 X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode()); 2813 if (BranchCode == X86::COND_INVALID) 2814 return true; // Can't handle indirect branch. 2815 2816 // Working from the bottom, handle the first conditional branch. 2817 if (Cond.empty()) { 2818 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB(); 2819 if (AllowModify && UnCondBrIter != MBB.end() && 2820 MBB.isLayoutSuccessor(TargetBB)) { 2821 // If we can modify the code and it ends in something like: 2822 // 2823 // jCC L1 2824 // jmp L2 2825 // L1: 2826 // ... 2827 // L2: 2828 // 2829 // Then we can change this to: 2830 // 2831 // jnCC L2 2832 // L1: 2833 // ... 2834 // L2: 2835 // 2836 // Which is a bit more efficient. 2837 // We conditionally jump to the fall-through block. 2838 BranchCode = GetOppositeBranchCondition(BranchCode); 2839 unsigned JNCC = GetCondBranchFromCond(BranchCode); 2840 MachineBasicBlock::iterator OldInst = I; 2841 2842 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC)) 2843 .addMBB(UnCondBrIter->getOperand(0).getMBB()); 2844 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4)) 2845 .addMBB(TargetBB); 2846 2847 OldInst->eraseFromParent(); 2848 UnCondBrIter->eraseFromParent(); 2849 2850 // Restart the analysis. 2851 UnCondBrIter = MBB.end(); 2852 I = MBB.end(); 2853 continue; 2854 } 2855 2856 FBB = TBB; 2857 TBB = I->getOperand(0).getMBB(); 2858 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 2859 continue; 2860 } 2861 2862 // Handle subsequent conditional branches. Only handle the case where all 2863 // conditional branches branch to the same destination and their condition 2864 // opcodes fit one of the special multi-branch idioms. 2865 assert(Cond.size() == 1); 2866 assert(TBB); 2867 2868 // Only handle the case where all conditional branches branch to the same 2869 // destination. 2870 if (TBB != I->getOperand(0).getMBB()) 2871 return true; 2872 2873 // If the conditions are the same, we can leave them alone. 2874 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm(); 2875 if (OldBranchCode == BranchCode) 2876 continue; 2877 2878 // If they differ, see if they fit one of the known patterns. Theoretically, 2879 // we could handle more patterns here, but we shouldn't expect to see them 2880 // if instruction selection has done a reasonable job. 2881 if ((OldBranchCode == X86::COND_NP && 2882 BranchCode == X86::COND_E) || 2883 (OldBranchCode == X86::COND_E && 2884 BranchCode == X86::COND_NP)) 2885 BranchCode = X86::COND_NP_OR_E; 2886 else if ((OldBranchCode == X86::COND_P && 2887 BranchCode == X86::COND_NE) || 2888 (OldBranchCode == X86::COND_NE && 2889 BranchCode == X86::COND_P)) 2890 BranchCode = X86::COND_NE_OR_P; 2891 else 2892 return true; 2893 2894 // Update the MachineOperand. 2895 Cond[0].setImm(BranchCode); 2896 } 2897 2898 return false; 2899 } 2900 2901 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 2902 MachineBasicBlock::iterator I = MBB.end(); 2903 unsigned Count = 0; 2904 2905 while (I != MBB.begin()) { 2906 --I; 2907 if (I->isDebugValue()) 2908 continue; 2909 if (I->getOpcode() != X86::JMP_4 && 2910 getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID) 2911 break; 2912 // Remove the branch. 2913 I->eraseFromParent(); 2914 I = MBB.end(); 2915 ++Count; 2916 } 2917 2918 return Count; 2919 } 2920 2921 unsigned 2922 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 2923 MachineBasicBlock *FBB, 2924 const SmallVectorImpl<MachineOperand> &Cond, 2925 DebugLoc DL) const { 2926 // Shouldn't be a fall through. 2927 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 2928 assert((Cond.size() == 1 || Cond.size() == 0) && 2929 "X86 branch conditions have one component!"); 2930 2931 if (Cond.empty()) { 2932 // Unconditional branch? 2933 assert(!FBB && "Unconditional branch with multiple successors!"); 2934 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB); 2935 return 1; 2936 } 2937 2938 // Conditional branch. 2939 unsigned Count = 0; 2940 X86::CondCode CC = (X86::CondCode)Cond[0].getImm(); 2941 switch (CC) { 2942 case X86::COND_NP_OR_E: 2943 // Synthesize NP_OR_E with two branches. 2944 BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB); 2945 ++Count; 2946 BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB); 2947 ++Count; 2948 break; 2949 case X86::COND_NE_OR_P: 2950 // Synthesize NE_OR_P with two branches. 2951 BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB); 2952 ++Count; 2953 BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB); 2954 ++Count; 2955 break; 2956 default: { 2957 unsigned Opc = GetCondBranchFromCond(CC); 2958 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB); 2959 ++Count; 2960 } 2961 } 2962 if (FBB) { 2963 // Two-way Conditional branch. Insert the second branch. 2964 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB); 2965 ++Count; 2966 } 2967 return Count; 2968 } 2969 2970 bool X86InstrInfo:: 2971 canInsertSelect(const MachineBasicBlock &MBB, 2972 const SmallVectorImpl<MachineOperand> &Cond, 2973 unsigned TrueReg, unsigned FalseReg, 2974 int &CondCycles, int &TrueCycles, int &FalseCycles) const { 2975 // Not all subtargets have cmov instructions. 2976 if (!Subtarget.hasCMov()) 2977 return false; 2978 if (Cond.size() != 1) 2979 return false; 2980 // We cannot do the composite conditions, at least not in SSA form. 2981 if ((X86::CondCode)Cond[0].getImm() > X86::COND_S) 2982 return false; 2983 2984 // Check register classes. 2985 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 2986 const TargetRegisterClass *RC = 2987 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); 2988 if (!RC) 2989 return false; 2990 2991 // We have cmov instructions for 16, 32, and 64 bit general purpose registers. 2992 if (X86::GR16RegClass.hasSubClassEq(RC) || 2993 X86::GR32RegClass.hasSubClassEq(RC) || 2994 X86::GR64RegClass.hasSubClassEq(RC)) { 2995 // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy 2996 // Bridge. Probably Ivy Bridge as well. 2997 CondCycles = 2; 2998 TrueCycles = 2; 2999 FalseCycles = 2; 3000 return true; 3001 } 3002 3003 // Can't do vectors. 3004 return false; 3005 } 3006 3007 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB, 3008 MachineBasicBlock::iterator I, DebugLoc DL, 3009 unsigned DstReg, 3010 const SmallVectorImpl<MachineOperand> &Cond, 3011 unsigned TrueReg, unsigned FalseReg) const { 3012 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 3013 assert(Cond.size() == 1 && "Invalid Cond array"); 3014 unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(), 3015 MRI.getRegClass(DstReg)->getSize(), 3016 false/*HasMemoryOperand*/); 3017 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg); 3018 } 3019 3020 /// isHReg - Test if the given register is a physical h register. 3021 static bool isHReg(unsigned Reg) { 3022 return X86::GR8_ABCD_HRegClass.contains(Reg); 3023 } 3024 3025 // Try and copy between VR128/VR64 and GR64 registers. 3026 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg, 3027 const X86Subtarget &Subtarget) { 3028 3029 // SrcReg(VR128) -> DestReg(GR64) 3030 // SrcReg(VR64) -> DestReg(GR64) 3031 // SrcReg(GR64) -> DestReg(VR128) 3032 // SrcReg(GR64) -> DestReg(VR64) 3033 3034 bool HasAVX = Subtarget.hasAVX(); 3035 bool HasAVX512 = Subtarget.hasAVX512(); 3036 if (X86::GR64RegClass.contains(DestReg)) { 3037 if (X86::VR128XRegClass.contains(SrcReg)) 3038 // Copy from a VR128 register to a GR64 register. 3039 return HasAVX512 ? X86::VMOVPQIto64Zrr: (HasAVX ? X86::VMOVPQIto64rr : 3040 X86::MOVPQIto64rr); 3041 if (X86::VR64RegClass.contains(SrcReg)) 3042 // Copy from a VR64 register to a GR64 register. 3043 return X86::MOVSDto64rr; 3044 } else if (X86::GR64RegClass.contains(SrcReg)) { 3045 // Copy from a GR64 register to a VR128 register. 3046 if (X86::VR128XRegClass.contains(DestReg)) 3047 return HasAVX512 ? X86::VMOV64toPQIZrr: (HasAVX ? X86::VMOV64toPQIrr : 3048 X86::MOV64toPQIrr); 3049 // Copy from a GR64 register to a VR64 register. 3050 if (X86::VR64RegClass.contains(DestReg)) 3051 return X86::MOV64toSDrr; 3052 } 3053 3054 // SrcReg(FR32) -> DestReg(GR32) 3055 // SrcReg(GR32) -> DestReg(FR32) 3056 3057 if (X86::GR32RegClass.contains(DestReg) && X86::FR32XRegClass.contains(SrcReg)) 3058 // Copy from a FR32 register to a GR32 register. 3059 return HasAVX512 ? X86::VMOVSS2DIZrr : (HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr); 3060 3061 if (X86::FR32XRegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg)) 3062 // Copy from a GR32 register to a FR32 register. 3063 return HasAVX512 ? X86::VMOVDI2SSZrr : (HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr); 3064 return 0; 3065 } 3066 3067 inline static bool MaskRegClassContains(unsigned Reg) { 3068 return X86::VK8RegClass.contains(Reg) || 3069 X86::VK16RegClass.contains(Reg) || 3070 X86::VK1RegClass.contains(Reg); 3071 } 3072 static 3073 unsigned copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg) { 3074 if (X86::VR128XRegClass.contains(DestReg, SrcReg) || 3075 X86::VR256XRegClass.contains(DestReg, SrcReg) || 3076 X86::VR512RegClass.contains(DestReg, SrcReg)) { 3077 DestReg = get512BitSuperRegister(DestReg); 3078 SrcReg = get512BitSuperRegister(SrcReg); 3079 return X86::VMOVAPSZrr; 3080 } 3081 if (MaskRegClassContains(DestReg) && 3082 MaskRegClassContains(SrcReg)) 3083 return X86::KMOVWkk; 3084 if (MaskRegClassContains(DestReg) && 3085 (X86::GR32RegClass.contains(SrcReg) || 3086 X86::GR16RegClass.contains(SrcReg) || 3087 X86::GR8RegClass.contains(SrcReg))) { 3088 SrcReg = getX86SubSuperRegister(SrcReg, MVT::i32); 3089 return X86::KMOVWkr; 3090 } 3091 if ((X86::GR32RegClass.contains(DestReg) || 3092 X86::GR16RegClass.contains(DestReg) || 3093 X86::GR8RegClass.contains(DestReg)) && 3094 MaskRegClassContains(SrcReg)) { 3095 DestReg = getX86SubSuperRegister(DestReg, MVT::i32); 3096 return X86::KMOVWrk; 3097 } 3098 return 0; 3099 } 3100 3101 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB, 3102 MachineBasicBlock::iterator MI, DebugLoc DL, 3103 unsigned DestReg, unsigned SrcReg, 3104 bool KillSrc) const { 3105 // First deal with the normal symmetric copies. 3106 bool HasAVX = Subtarget.hasAVX(); 3107 bool HasAVX512 = Subtarget.hasAVX512(); 3108 unsigned Opc = 0; 3109 if (X86::GR64RegClass.contains(DestReg, SrcReg)) 3110 Opc = X86::MOV64rr; 3111 else if (X86::GR32RegClass.contains(DestReg, SrcReg)) 3112 Opc = X86::MOV32rr; 3113 else if (X86::GR16RegClass.contains(DestReg, SrcReg)) 3114 Opc = X86::MOV16rr; 3115 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) { 3116 // Copying to or from a physical H register on x86-64 requires a NOREX 3117 // move. Otherwise use a normal move. 3118 if ((isHReg(DestReg) || isHReg(SrcReg)) && 3119 Subtarget.is64Bit()) { 3120 Opc = X86::MOV8rr_NOREX; 3121 // Both operands must be encodable without an REX prefix. 3122 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) && 3123 "8-bit H register can not be copied outside GR8_NOREX"); 3124 } else 3125 Opc = X86::MOV8rr; 3126 } 3127 else if (X86::VR64RegClass.contains(DestReg, SrcReg)) 3128 Opc = X86::MMX_MOVQ64rr; 3129 else if (HasAVX512) 3130 Opc = copyPhysRegOpcode_AVX512(DestReg, SrcReg); 3131 else if (X86::VR128RegClass.contains(DestReg, SrcReg)) 3132 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr; 3133 else if (X86::VR256RegClass.contains(DestReg, SrcReg)) 3134 Opc = X86::VMOVAPSYrr; 3135 if (!Opc) 3136 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget); 3137 3138 if (Opc) { 3139 BuildMI(MBB, MI, DL, get(Opc), DestReg) 3140 .addReg(SrcReg, getKillRegState(KillSrc)); 3141 return; 3142 } 3143 3144 // Moving EFLAGS to / from another register requires a push and a pop. 3145 // Notice that we have to adjust the stack if we don't want to clobber the 3146 // first frame index. See X86FrameLowering.cpp - colobbersTheStack. 3147 if (SrcReg == X86::EFLAGS) { 3148 if (X86::GR64RegClass.contains(DestReg)) { 3149 BuildMI(MBB, MI, DL, get(X86::PUSHF64)); 3150 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg); 3151 return; 3152 } 3153 if (X86::GR32RegClass.contains(DestReg)) { 3154 BuildMI(MBB, MI, DL, get(X86::PUSHF32)); 3155 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg); 3156 return; 3157 } 3158 } 3159 if (DestReg == X86::EFLAGS) { 3160 if (X86::GR64RegClass.contains(SrcReg)) { 3161 BuildMI(MBB, MI, DL, get(X86::PUSH64r)) 3162 .addReg(SrcReg, getKillRegState(KillSrc)); 3163 BuildMI(MBB, MI, DL, get(X86::POPF64)); 3164 return; 3165 } 3166 if (X86::GR32RegClass.contains(SrcReg)) { 3167 BuildMI(MBB, MI, DL, get(X86::PUSH32r)) 3168 .addReg(SrcReg, getKillRegState(KillSrc)); 3169 BuildMI(MBB, MI, DL, get(X86::POPF32)); 3170 return; 3171 } 3172 } 3173 3174 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) 3175 << " to " << RI.getName(DestReg) << '\n'); 3176 llvm_unreachable("Cannot emit physreg copy instruction"); 3177 } 3178 3179 static unsigned getLoadStoreRegOpcode(unsigned Reg, 3180 const TargetRegisterClass *RC, 3181 bool isStackAligned, 3182 const X86Subtarget &STI, 3183 bool load) { 3184 if (STI.hasAVX512()) { 3185 if (X86::VK8RegClass.hasSubClassEq(RC) || 3186 X86::VK16RegClass.hasSubClassEq(RC)) 3187 return load ? X86::KMOVWkm : X86::KMOVWmk; 3188 if (RC->getSize() == 4 && X86::FR32XRegClass.hasSubClassEq(RC)) 3189 return load ? X86::VMOVSSZrm : X86::VMOVSSZmr; 3190 if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC)) 3191 return load ? X86::VMOVSDZrm : X86::VMOVSDZmr; 3192 if (X86::VR512RegClass.hasSubClassEq(RC)) 3193 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr; 3194 } 3195 3196 bool HasAVX = STI.hasAVX(); 3197 switch (RC->getSize()) { 3198 default: 3199 llvm_unreachable("Unknown spill size"); 3200 case 1: 3201 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass"); 3202 if (STI.is64Bit()) 3203 // Copying to or from a physical H register on x86-64 requires a NOREX 3204 // move. Otherwise use a normal move. 3205 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC)) 3206 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX; 3207 return load ? X86::MOV8rm : X86::MOV8mr; 3208 case 2: 3209 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass"); 3210 return load ? X86::MOV16rm : X86::MOV16mr; 3211 case 4: 3212 if (X86::GR32RegClass.hasSubClassEq(RC)) 3213 return load ? X86::MOV32rm : X86::MOV32mr; 3214 if (X86::FR32RegClass.hasSubClassEq(RC)) 3215 return load ? 3216 (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) : 3217 (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr); 3218 if (X86::RFP32RegClass.hasSubClassEq(RC)) 3219 return load ? X86::LD_Fp32m : X86::ST_Fp32m; 3220 llvm_unreachable("Unknown 4-byte regclass"); 3221 case 8: 3222 if (X86::GR64RegClass.hasSubClassEq(RC)) 3223 return load ? X86::MOV64rm : X86::MOV64mr; 3224 if (X86::FR64RegClass.hasSubClassEq(RC)) 3225 return load ? 3226 (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) : 3227 (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr); 3228 if (X86::VR64RegClass.hasSubClassEq(RC)) 3229 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr; 3230 if (X86::RFP64RegClass.hasSubClassEq(RC)) 3231 return load ? X86::LD_Fp64m : X86::ST_Fp64m; 3232 llvm_unreachable("Unknown 8-byte regclass"); 3233 case 10: 3234 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass"); 3235 return load ? X86::LD_Fp80m : X86::ST_FpP80m; 3236 case 16: { 3237 assert((X86::VR128RegClass.hasSubClassEq(RC) || 3238 X86::VR128XRegClass.hasSubClassEq(RC))&& "Unknown 16-byte regclass"); 3239 // If stack is realigned we can use aligned stores. 3240 if (isStackAligned) 3241 return load ? 3242 (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) : 3243 (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr); 3244 else 3245 return load ? 3246 (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) : 3247 (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr); 3248 } 3249 case 32: 3250 assert((X86::VR256RegClass.hasSubClassEq(RC) || 3251 X86::VR256XRegClass.hasSubClassEq(RC)) && "Unknown 32-byte regclass"); 3252 // If stack is realigned we can use aligned stores. 3253 if (isStackAligned) 3254 return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr; 3255 else 3256 return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr; 3257 case 64: 3258 assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass"); 3259 if (isStackAligned) 3260 return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr; 3261 else 3262 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr; 3263 } 3264 } 3265 3266 static unsigned getStoreRegOpcode(unsigned SrcReg, 3267 const TargetRegisterClass *RC, 3268 bool isStackAligned, 3269 const X86Subtarget &STI) { 3270 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false); 3271 } 3272 3273 3274 static unsigned getLoadRegOpcode(unsigned DestReg, 3275 const TargetRegisterClass *RC, 3276 bool isStackAligned, 3277 const X86Subtarget &STI) { 3278 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true); 3279 } 3280 3281 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 3282 MachineBasicBlock::iterator MI, 3283 unsigned SrcReg, bool isKill, int FrameIdx, 3284 const TargetRegisterClass *RC, 3285 const TargetRegisterInfo *TRI) const { 3286 const MachineFunction &MF = *MBB.getParent(); 3287 assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() && 3288 "Stack slot too small for store"); 3289 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16); 3290 bool isAligned = 3291 (MF.getTarget().getFrameLowering()->getStackAlignment() >= Alignment) || 3292 RI.canRealignStack(MF); 3293 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget); 3294 DebugLoc DL = MBB.findDebugLoc(MI); 3295 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx) 3296 .addReg(SrcReg, getKillRegState(isKill)); 3297 } 3298 3299 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, 3300 bool isKill, 3301 SmallVectorImpl<MachineOperand> &Addr, 3302 const TargetRegisterClass *RC, 3303 MachineInstr::mmo_iterator MMOBegin, 3304 MachineInstr::mmo_iterator MMOEnd, 3305 SmallVectorImpl<MachineInstr*> &NewMIs) const { 3306 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16); 3307 bool isAligned = MMOBegin != MMOEnd && 3308 (*MMOBegin)->getAlignment() >= Alignment; 3309 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget); 3310 DebugLoc DL; 3311 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)); 3312 for (unsigned i = 0, e = Addr.size(); i != e; ++i) 3313 MIB.addOperand(Addr[i]); 3314 MIB.addReg(SrcReg, getKillRegState(isKill)); 3315 (*MIB).setMemRefs(MMOBegin, MMOEnd); 3316 NewMIs.push_back(MIB); 3317 } 3318 3319 3320 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 3321 MachineBasicBlock::iterator MI, 3322 unsigned DestReg, int FrameIdx, 3323 const TargetRegisterClass *RC, 3324 const TargetRegisterInfo *TRI) const { 3325 const MachineFunction &MF = *MBB.getParent(); 3326 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16); 3327 bool isAligned = 3328 (MF.getTarget().getFrameLowering()->getStackAlignment() >= Alignment) || 3329 RI.canRealignStack(MF); 3330 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget); 3331 DebugLoc DL = MBB.findDebugLoc(MI); 3332 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx); 3333 } 3334 3335 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 3336 SmallVectorImpl<MachineOperand> &Addr, 3337 const TargetRegisterClass *RC, 3338 MachineInstr::mmo_iterator MMOBegin, 3339 MachineInstr::mmo_iterator MMOEnd, 3340 SmallVectorImpl<MachineInstr*> &NewMIs) const { 3341 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16); 3342 bool isAligned = MMOBegin != MMOEnd && 3343 (*MMOBegin)->getAlignment() >= Alignment; 3344 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget); 3345 DebugLoc DL; 3346 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); 3347 for (unsigned i = 0, e = Addr.size(); i != e; ++i) 3348 MIB.addOperand(Addr[i]); 3349 (*MIB).setMemRefs(MMOBegin, MMOEnd); 3350 NewMIs.push_back(MIB); 3351 } 3352 3353 bool X86InstrInfo:: 3354 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, 3355 int &CmpMask, int &CmpValue) const { 3356 switch (MI->getOpcode()) { 3357 default: break; 3358 case X86::CMP64ri32: 3359 case X86::CMP64ri8: 3360 case X86::CMP32ri: 3361 case X86::CMP32ri8: 3362 case X86::CMP16ri: 3363 case X86::CMP16ri8: 3364 case X86::CMP8ri: 3365 SrcReg = MI->getOperand(0).getReg(); 3366 SrcReg2 = 0; 3367 CmpMask = ~0; 3368 CmpValue = MI->getOperand(1).getImm(); 3369 return true; 3370 // A SUB can be used to perform comparison. 3371 case X86::SUB64rm: 3372 case X86::SUB32rm: 3373 case X86::SUB16rm: 3374 case X86::SUB8rm: 3375 SrcReg = MI->getOperand(1).getReg(); 3376 SrcReg2 = 0; 3377 CmpMask = ~0; 3378 CmpValue = 0; 3379 return true; 3380 case X86::SUB64rr: 3381 case X86::SUB32rr: 3382 case X86::SUB16rr: 3383 case X86::SUB8rr: 3384 SrcReg = MI->getOperand(1).getReg(); 3385 SrcReg2 = MI->getOperand(2).getReg(); 3386 CmpMask = ~0; 3387 CmpValue = 0; 3388 return true; 3389 case X86::SUB64ri32: 3390 case X86::SUB64ri8: 3391 case X86::SUB32ri: 3392 case X86::SUB32ri8: 3393 case X86::SUB16ri: 3394 case X86::SUB16ri8: 3395 case X86::SUB8ri: 3396 SrcReg = MI->getOperand(1).getReg(); 3397 SrcReg2 = 0; 3398 CmpMask = ~0; 3399 CmpValue = MI->getOperand(2).getImm(); 3400 return true; 3401 case X86::CMP64rr: 3402 case X86::CMP32rr: 3403 case X86::CMP16rr: 3404 case X86::CMP8rr: 3405 SrcReg = MI->getOperand(0).getReg(); 3406 SrcReg2 = MI->getOperand(1).getReg(); 3407 CmpMask = ~0; 3408 CmpValue = 0; 3409 return true; 3410 case X86::TEST8rr: 3411 case X86::TEST16rr: 3412 case X86::TEST32rr: 3413 case X86::TEST64rr: 3414 SrcReg = MI->getOperand(0).getReg(); 3415 if (MI->getOperand(1).getReg() != SrcReg) return false; 3416 // Compare against zero. 3417 SrcReg2 = 0; 3418 CmpMask = ~0; 3419 CmpValue = 0; 3420 return true; 3421 } 3422 return false; 3423 } 3424 3425 /// isRedundantFlagInstr - check whether the first instruction, whose only 3426 /// purpose is to update flags, can be made redundant. 3427 /// CMPrr can be made redundant by SUBrr if the operands are the same. 3428 /// This function can be extended later on. 3429 /// SrcReg, SrcRegs: register operands for FlagI. 3430 /// ImmValue: immediate for FlagI if it takes an immediate. 3431 inline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg, 3432 unsigned SrcReg2, int ImmValue, 3433 MachineInstr *OI) { 3434 if (((FlagI->getOpcode() == X86::CMP64rr && 3435 OI->getOpcode() == X86::SUB64rr) || 3436 (FlagI->getOpcode() == X86::CMP32rr && 3437 OI->getOpcode() == X86::SUB32rr)|| 3438 (FlagI->getOpcode() == X86::CMP16rr && 3439 OI->getOpcode() == X86::SUB16rr)|| 3440 (FlagI->getOpcode() == X86::CMP8rr && 3441 OI->getOpcode() == X86::SUB8rr)) && 3442 ((OI->getOperand(1).getReg() == SrcReg && 3443 OI->getOperand(2).getReg() == SrcReg2) || 3444 (OI->getOperand(1).getReg() == SrcReg2 && 3445 OI->getOperand(2).getReg() == SrcReg))) 3446 return true; 3447 3448 if (((FlagI->getOpcode() == X86::CMP64ri32 && 3449 OI->getOpcode() == X86::SUB64ri32) || 3450 (FlagI->getOpcode() == X86::CMP64ri8 && 3451 OI->getOpcode() == X86::SUB64ri8) || 3452 (FlagI->getOpcode() == X86::CMP32ri && 3453 OI->getOpcode() == X86::SUB32ri) || 3454 (FlagI->getOpcode() == X86::CMP32ri8 && 3455 OI->getOpcode() == X86::SUB32ri8) || 3456 (FlagI->getOpcode() == X86::CMP16ri && 3457 OI->getOpcode() == X86::SUB16ri) || 3458 (FlagI->getOpcode() == X86::CMP16ri8 && 3459 OI->getOpcode() == X86::SUB16ri8) || 3460 (FlagI->getOpcode() == X86::CMP8ri && 3461 OI->getOpcode() == X86::SUB8ri)) && 3462 OI->getOperand(1).getReg() == SrcReg && 3463 OI->getOperand(2).getImm() == ImmValue) 3464 return true; 3465 return false; 3466 } 3467 3468 /// isDefConvertible - check whether the definition can be converted 3469 /// to remove a comparison against zero. 3470 inline static bool isDefConvertible(MachineInstr *MI) { 3471 switch (MI->getOpcode()) { 3472 default: return false; 3473 3474 // The shift instructions only modify ZF if their shift count is non-zero. 3475 // N.B.: The processor truncates the shift count depending on the encoding. 3476 case X86::SAR8ri: case X86::SAR16ri: case X86::SAR32ri:case X86::SAR64ri: 3477 case X86::SHR8ri: case X86::SHR16ri: case X86::SHR32ri:case X86::SHR64ri: 3478 return getTruncatedShiftCount(MI, 2) != 0; 3479 3480 // Some left shift instructions can be turned into LEA instructions but only 3481 // if their flags aren't used. Avoid transforming such instructions. 3482 case X86::SHL8ri: case X86::SHL16ri: case X86::SHL32ri:case X86::SHL64ri:{ 3483 unsigned ShAmt = getTruncatedShiftCount(MI, 2); 3484 if (isTruncatedShiftCountForLEA(ShAmt)) return false; 3485 return ShAmt != 0; 3486 } 3487 3488 case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8: 3489 case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8: 3490 return getTruncatedShiftCount(MI, 3) != 0; 3491 3492 case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri: 3493 case X86::SUB32ri8: case X86::SUB16ri: case X86::SUB16ri8: 3494 case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr: 3495 case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm: 3496 case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm: 3497 case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r: 3498 case X86::DEC64_32r: case X86::DEC64_16r: 3499 case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri: 3500 case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8: 3501 case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr: 3502 case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm: 3503 case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm: 3504 case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r: 3505 case X86::INC64_32r: case X86::INC64_16r: 3506 case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri: 3507 case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8: 3508 case X86::AND8ri: case X86::AND64rr: case X86::AND32rr: 3509 case X86::AND16rr: case X86::AND8rr: case X86::AND64rm: 3510 case X86::AND32rm: case X86::AND16rm: case X86::AND8rm: 3511 case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri: 3512 case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8: 3513 case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr: 3514 case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm: 3515 case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm: 3516 case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri: 3517 case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8: 3518 case X86::OR8ri: case X86::OR64rr: case X86::OR32rr: 3519 case X86::OR16rr: case X86::OR8rr: case X86::OR64rm: 3520 case X86::OR32rm: case X86::OR16rm: case X86::OR8rm: 3521 case X86::NEG8r: case X86::NEG16r: case X86::NEG32r: case X86::NEG64r: 3522 case X86::SAR8r1: case X86::SAR16r1: case X86::SAR32r1:case X86::SAR64r1: 3523 case X86::SHR8r1: case X86::SHR16r1: case X86::SHR32r1:case X86::SHR64r1: 3524 case X86::SHL8r1: case X86::SHL16r1: case X86::SHL32r1:case X86::SHL64r1: 3525 case X86::ADC32ri: case X86::ADC32ri8: 3526 case X86::ADC32rr: case X86::ADC64ri32: 3527 case X86::ADC64ri8: case X86::ADC64rr: 3528 case X86::SBB32ri: case X86::SBB32ri8: 3529 case X86::SBB32rr: case X86::SBB64ri32: 3530 case X86::SBB64ri8: case X86::SBB64rr: 3531 case X86::ANDN32rr: case X86::ANDN32rm: 3532 case X86::ANDN64rr: case X86::ANDN64rm: 3533 case X86::BEXTR32rr: case X86::BEXTR64rr: 3534 case X86::BEXTR32rm: case X86::BEXTR64rm: 3535 case X86::BLSI32rr: case X86::BLSI32rm: 3536 case X86::BLSI64rr: case X86::BLSI64rm: 3537 case X86::BLSMSK32rr:case X86::BLSMSK32rm: 3538 case X86::BLSMSK64rr:case X86::BLSMSK64rm: 3539 case X86::BLSR32rr: case X86::BLSR32rm: 3540 case X86::BLSR64rr: case X86::BLSR64rm: 3541 case X86::BZHI32rr: case X86::BZHI32rm: 3542 case X86::BZHI64rr: case X86::BZHI64rm: 3543 case X86::LZCNT16rr: case X86::LZCNT16rm: 3544 case X86::LZCNT32rr: case X86::LZCNT32rm: 3545 case X86::LZCNT64rr: case X86::LZCNT64rm: 3546 case X86::POPCNT16rr:case X86::POPCNT16rm: 3547 case X86::POPCNT32rr:case X86::POPCNT32rm: 3548 case X86::POPCNT64rr:case X86::POPCNT64rm: 3549 case X86::TZCNT16rr: case X86::TZCNT16rm: 3550 case X86::TZCNT32rr: case X86::TZCNT32rm: 3551 case X86::TZCNT64rr: case X86::TZCNT64rm: 3552 return true; 3553 } 3554 } 3555 3556 /// isUseDefConvertible - check whether the use can be converted 3557 /// to remove a comparison against zero. 3558 static X86::CondCode isUseDefConvertible(MachineInstr *MI) { 3559 switch (MI->getOpcode()) { 3560 default: return X86::COND_INVALID; 3561 case X86::LZCNT16rr: case X86::LZCNT16rm: 3562 case X86::LZCNT32rr: case X86::LZCNT32rm: 3563 case X86::LZCNT64rr: case X86::LZCNT64rm: 3564 return X86::COND_B; 3565 case X86::POPCNT16rr:case X86::POPCNT16rm: 3566 case X86::POPCNT32rr:case X86::POPCNT32rm: 3567 case X86::POPCNT64rr:case X86::POPCNT64rm: 3568 return X86::COND_E; 3569 case X86::TZCNT16rr: case X86::TZCNT16rm: 3570 case X86::TZCNT32rr: case X86::TZCNT32rm: 3571 case X86::TZCNT64rr: case X86::TZCNT64rm: 3572 return X86::COND_B; 3573 } 3574 } 3575 3576 /// optimizeCompareInstr - Check if there exists an earlier instruction that 3577 /// operates on the same source operands and sets flags in the same way as 3578 /// Compare; remove Compare if possible. 3579 bool X86InstrInfo:: 3580 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, 3581 int CmpMask, int CmpValue, 3582 const MachineRegisterInfo *MRI) const { 3583 // Check whether we can replace SUB with CMP. 3584 unsigned NewOpcode = 0; 3585 switch (CmpInstr->getOpcode()) { 3586 default: break; 3587 case X86::SUB64ri32: 3588 case X86::SUB64ri8: 3589 case X86::SUB32ri: 3590 case X86::SUB32ri8: 3591 case X86::SUB16ri: 3592 case X86::SUB16ri8: 3593 case X86::SUB8ri: 3594 case X86::SUB64rm: 3595 case X86::SUB32rm: 3596 case X86::SUB16rm: 3597 case X86::SUB8rm: 3598 case X86::SUB64rr: 3599 case X86::SUB32rr: 3600 case X86::SUB16rr: 3601 case X86::SUB8rr: { 3602 if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg())) 3603 return false; 3604 // There is no use of the destination register, we can replace SUB with CMP. 3605 switch (CmpInstr->getOpcode()) { 3606 default: llvm_unreachable("Unreachable!"); 3607 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break; 3608 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break; 3609 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break; 3610 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break; 3611 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break; 3612 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break; 3613 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break; 3614 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break; 3615 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break; 3616 case X86::SUB64ri8: NewOpcode = X86::CMP64ri8; break; 3617 case X86::SUB32ri: NewOpcode = X86::CMP32ri; break; 3618 case X86::SUB32ri8: NewOpcode = X86::CMP32ri8; break; 3619 case X86::SUB16ri: NewOpcode = X86::CMP16ri; break; 3620 case X86::SUB16ri8: NewOpcode = X86::CMP16ri8; break; 3621 case X86::SUB8ri: NewOpcode = X86::CMP8ri; break; 3622 } 3623 CmpInstr->setDesc(get(NewOpcode)); 3624 CmpInstr->RemoveOperand(0); 3625 // Fall through to optimize Cmp if Cmp is CMPrr or CMPri. 3626 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm || 3627 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm) 3628 return false; 3629 } 3630 } 3631 3632 // Get the unique definition of SrcReg. 3633 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg); 3634 if (!MI) return false; 3635 3636 // CmpInstr is the first instruction of the BB. 3637 MachineBasicBlock::iterator I = CmpInstr, Def = MI; 3638 3639 // If we are comparing against zero, check whether we can use MI to update 3640 // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize. 3641 bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0); 3642 if (IsCmpZero && MI->getParent() != CmpInstr->getParent()) 3643 return false; 3644 3645 // If we have a use of the source register between the def and our compare 3646 // instruction we can eliminate the compare iff the use sets EFLAGS in the 3647 // right way. 3648 bool ShouldUpdateCC = false; 3649 X86::CondCode NewCC = X86::COND_INVALID; 3650 if (IsCmpZero && !isDefConvertible(MI)) { 3651 // Scan forward from the use until we hit the use we're looking for or the 3652 // compare instruction. 3653 for (MachineBasicBlock::iterator J = MI;; ++J) { 3654 // Do we have a convertible instruction? 3655 NewCC = isUseDefConvertible(J); 3656 if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() && 3657 J->getOperand(1).getReg() == SrcReg) { 3658 assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!"); 3659 ShouldUpdateCC = true; // Update CC later on. 3660 // This is not a def of SrcReg, but still a def of EFLAGS. Keep going 3661 // with the new def. 3662 MI = Def = J; 3663 break; 3664 } 3665 3666 if (J == I) 3667 return false; 3668 } 3669 } 3670 3671 // We are searching for an earlier instruction that can make CmpInstr 3672 // redundant and that instruction will be saved in Sub. 3673 MachineInstr *Sub = nullptr; 3674 const TargetRegisterInfo *TRI = &getRegisterInfo(); 3675 3676 // We iterate backward, starting from the instruction before CmpInstr and 3677 // stop when reaching the definition of a source register or done with the BB. 3678 // RI points to the instruction before CmpInstr. 3679 // If the definition is in this basic block, RE points to the definition; 3680 // otherwise, RE is the rend of the basic block. 3681 MachineBasicBlock::reverse_iterator 3682 RI = MachineBasicBlock::reverse_iterator(I), 3683 RE = CmpInstr->getParent() == MI->getParent() ? 3684 MachineBasicBlock::reverse_iterator(++Def) /* points to MI */ : 3685 CmpInstr->getParent()->rend(); 3686 MachineInstr *Movr0Inst = nullptr; 3687 for (; RI != RE; ++RI) { 3688 MachineInstr *Instr = &*RI; 3689 // Check whether CmpInstr can be made redundant by the current instruction. 3690 if (!IsCmpZero && 3691 isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) { 3692 Sub = Instr; 3693 break; 3694 } 3695 3696 if (Instr->modifiesRegister(X86::EFLAGS, TRI) || 3697 Instr->readsRegister(X86::EFLAGS, TRI)) { 3698 // This instruction modifies or uses EFLAGS. 3699 3700 // MOV32r0 etc. are implemented with xor which clobbers condition code. 3701 // They are safe to move up, if the definition to EFLAGS is dead and 3702 // earlier instructions do not read or write EFLAGS. 3703 if (!Movr0Inst && Instr->getOpcode() == X86::MOV32r0 && 3704 Instr->registerDefIsDead(X86::EFLAGS, TRI)) { 3705 Movr0Inst = Instr; 3706 continue; 3707 } 3708 3709 // We can't remove CmpInstr. 3710 return false; 3711 } 3712 } 3713 3714 // Return false if no candidates exist. 3715 if (!IsCmpZero && !Sub) 3716 return false; 3717 3718 bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && 3719 Sub->getOperand(2).getReg() == SrcReg); 3720 3721 // Scan forward from the instruction after CmpInstr for uses of EFLAGS. 3722 // It is safe to remove CmpInstr if EFLAGS is redefined or killed. 3723 // If we are done with the basic block, we need to check whether EFLAGS is 3724 // live-out. 3725 bool IsSafe = false; 3726 SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate; 3727 MachineBasicBlock::iterator E = CmpInstr->getParent()->end(); 3728 for (++I; I != E; ++I) { 3729 const MachineInstr &Instr = *I; 3730 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI); 3731 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI); 3732 // We should check the usage if this instruction uses and updates EFLAGS. 3733 if (!UseEFLAGS && ModifyEFLAGS) { 3734 // It is safe to remove CmpInstr if EFLAGS is updated again. 3735 IsSafe = true; 3736 break; 3737 } 3738 if (!UseEFLAGS && !ModifyEFLAGS) 3739 continue; 3740 3741 // EFLAGS is used by this instruction. 3742 X86::CondCode OldCC = X86::COND_INVALID; 3743 bool OpcIsSET = false; 3744 if (IsCmpZero || IsSwapped) { 3745 // We decode the condition code from opcode. 3746 if (Instr.isBranch()) 3747 OldCC = getCondFromBranchOpc(Instr.getOpcode()); 3748 else { 3749 OldCC = getCondFromSETOpc(Instr.getOpcode()); 3750 if (OldCC != X86::COND_INVALID) 3751 OpcIsSET = true; 3752 else 3753 OldCC = X86::getCondFromCMovOpc(Instr.getOpcode()); 3754 } 3755 if (OldCC == X86::COND_INVALID) return false; 3756 } 3757 if (IsCmpZero) { 3758 switch (OldCC) { 3759 default: break; 3760 case X86::COND_A: case X86::COND_AE: 3761 case X86::COND_B: case X86::COND_BE: 3762 case X86::COND_G: case X86::COND_GE: 3763 case X86::COND_L: case X86::COND_LE: 3764 case X86::COND_O: case X86::COND_NO: 3765 // CF and OF are used, we can't perform this optimization. 3766 return false; 3767 } 3768 3769 // If we're updating the condition code check if we have to reverse the 3770 // condition. 3771 if (ShouldUpdateCC) 3772 switch (OldCC) { 3773 default: 3774 return false; 3775 case X86::COND_E: 3776 break; 3777 case X86::COND_NE: 3778 NewCC = GetOppositeBranchCondition(NewCC); 3779 break; 3780 } 3781 } else if (IsSwapped) { 3782 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs 3783 // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc. 3784 // We swap the condition code and synthesize the new opcode. 3785 NewCC = getSwappedCondition(OldCC); 3786 if (NewCC == X86::COND_INVALID) return false; 3787 } 3788 3789 if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) { 3790 // Synthesize the new opcode. 3791 bool HasMemoryOperand = Instr.hasOneMemOperand(); 3792 unsigned NewOpc; 3793 if (Instr.isBranch()) 3794 NewOpc = GetCondBranchFromCond(NewCC); 3795 else if(OpcIsSET) 3796 NewOpc = getSETFromCond(NewCC, HasMemoryOperand); 3797 else { 3798 unsigned DstReg = Instr.getOperand(0).getReg(); 3799 NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(), 3800 HasMemoryOperand); 3801 } 3802 3803 // Push the MachineInstr to OpsToUpdate. 3804 // If it is safe to remove CmpInstr, the condition code of these 3805 // instructions will be modified. 3806 OpsToUpdate.push_back(std::make_pair(&*I, NewOpc)); 3807 } 3808 if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) { 3809 // It is safe to remove CmpInstr if EFLAGS is updated again or killed. 3810 IsSafe = true; 3811 break; 3812 } 3813 } 3814 3815 // If EFLAGS is not killed nor re-defined, we should check whether it is 3816 // live-out. If it is live-out, do not optimize. 3817 if ((IsCmpZero || IsSwapped) && !IsSafe) { 3818 MachineBasicBlock *MBB = CmpInstr->getParent(); 3819 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), 3820 SE = MBB->succ_end(); SI != SE; ++SI) 3821 if ((*SI)->isLiveIn(X86::EFLAGS)) 3822 return false; 3823 } 3824 3825 // The instruction to be updated is either Sub or MI. 3826 Sub = IsCmpZero ? MI : Sub; 3827 // Move Movr0Inst to the appropriate place before Sub. 3828 if (Movr0Inst) { 3829 // Look backwards until we find a def that doesn't use the current EFLAGS. 3830 Def = Sub; 3831 MachineBasicBlock::reverse_iterator 3832 InsertI = MachineBasicBlock::reverse_iterator(++Def), 3833 InsertE = Sub->getParent()->rend(); 3834 for (; InsertI != InsertE; ++InsertI) { 3835 MachineInstr *Instr = &*InsertI; 3836 if (!Instr->readsRegister(X86::EFLAGS, TRI) && 3837 Instr->modifiesRegister(X86::EFLAGS, TRI)) { 3838 Sub->getParent()->remove(Movr0Inst); 3839 Instr->getParent()->insert(MachineBasicBlock::iterator(Instr), 3840 Movr0Inst); 3841 break; 3842 } 3843 } 3844 if (InsertI == InsertE) 3845 return false; 3846 } 3847 3848 // Make sure Sub instruction defines EFLAGS and mark the def live. 3849 unsigned i = 0, e = Sub->getNumOperands(); 3850 for (; i != e; ++i) { 3851 MachineOperand &MO = Sub->getOperand(i); 3852 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) { 3853 MO.setIsDead(false); 3854 break; 3855 } 3856 } 3857 assert(i != e && "Unable to locate a def EFLAGS operand"); 3858 3859 CmpInstr->eraseFromParent(); 3860 3861 // Modify the condition code of instructions in OpsToUpdate. 3862 for (unsigned i = 0, e = OpsToUpdate.size(); i < e; i++) 3863 OpsToUpdate[i].first->setDesc(get(OpsToUpdate[i].second)); 3864 return true; 3865 } 3866 3867 /// optimizeLoadInstr - Try to remove the load by folding it to a register 3868 /// operand at the use. We fold the load instructions if load defines a virtual 3869 /// register, the virtual register is used once in the same BB, and the 3870 /// instructions in-between do not load or store, and have no side effects. 3871 MachineInstr* X86InstrInfo:: 3872 optimizeLoadInstr(MachineInstr *MI, const MachineRegisterInfo *MRI, 3873 unsigned &FoldAsLoadDefReg, 3874 MachineInstr *&DefMI) const { 3875 if (FoldAsLoadDefReg == 0) 3876 return nullptr; 3877 // To be conservative, if there exists another load, clear the load candidate. 3878 if (MI->mayLoad()) { 3879 FoldAsLoadDefReg = 0; 3880 return nullptr; 3881 } 3882 3883 // Check whether we can move DefMI here. 3884 DefMI = MRI->getVRegDef(FoldAsLoadDefReg); 3885 assert(DefMI); 3886 bool SawStore = false; 3887 if (!DefMI->isSafeToMove(this, nullptr, SawStore)) 3888 return nullptr; 3889 3890 // We try to commute MI if possible. 3891 unsigned IdxEnd = (MI->isCommutable()) ? 2 : 1; 3892 for (unsigned Idx = 0; Idx < IdxEnd; Idx++) { 3893 // Collect information about virtual register operands of MI. 3894 unsigned SrcOperandId = 0; 3895 bool FoundSrcOperand = false; 3896 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) { 3897 MachineOperand &MO = MI->getOperand(i); 3898 if (!MO.isReg()) 3899 continue; 3900 unsigned Reg = MO.getReg(); 3901 if (Reg != FoldAsLoadDefReg) 3902 continue; 3903 // Do not fold if we have a subreg use or a def or multiple uses. 3904 if (MO.getSubReg() || MO.isDef() || FoundSrcOperand) 3905 return nullptr; 3906 3907 SrcOperandId = i; 3908 FoundSrcOperand = true; 3909 } 3910 if (!FoundSrcOperand) return nullptr; 3911 3912 // Check whether we can fold the def into SrcOperandId. 3913 SmallVector<unsigned, 8> Ops; 3914 Ops.push_back(SrcOperandId); 3915 MachineInstr *FoldMI = foldMemoryOperand(MI, Ops, DefMI); 3916 if (FoldMI) { 3917 FoldAsLoadDefReg = 0; 3918 return FoldMI; 3919 } 3920 3921 if (Idx == 1) { 3922 // MI was changed but it didn't help, commute it back! 3923 commuteInstruction(MI, false); 3924 return nullptr; 3925 } 3926 3927 // Check whether we can commute MI and enable folding. 3928 if (MI->isCommutable()) { 3929 MachineInstr *NewMI = commuteInstruction(MI, false); 3930 // Unable to commute. 3931 if (!NewMI) return nullptr; 3932 if (NewMI != MI) { 3933 // New instruction. It doesn't need to be kept. 3934 NewMI->eraseFromParent(); 3935 return nullptr; 3936 } 3937 } 3938 } 3939 return nullptr; 3940 } 3941 3942 /// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr 3943 /// instruction with two undef reads of the register being defined. This is 3944 /// used for mapping: 3945 /// %xmm4 = V_SET0 3946 /// to: 3947 /// %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef> 3948 /// 3949 static bool Expand2AddrUndef(MachineInstrBuilder &MIB, 3950 const MCInstrDesc &Desc) { 3951 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction."); 3952 unsigned Reg = MIB->getOperand(0).getReg(); 3953 MIB->setDesc(Desc); 3954 3955 // MachineInstr::addOperand() will insert explicit operands before any 3956 // implicit operands. 3957 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef); 3958 // But we don't trust that. 3959 assert(MIB->getOperand(1).getReg() == Reg && 3960 MIB->getOperand(2).getReg() == Reg && "Misplaced operand"); 3961 return true; 3962 } 3963 3964 bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { 3965 bool HasAVX = Subtarget.hasAVX(); 3966 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI); 3967 switch (MI->getOpcode()) { 3968 case X86::MOV32r0: 3969 return Expand2AddrUndef(MIB, get(X86::XOR32rr)); 3970 case X86::SETB_C8r: 3971 return Expand2AddrUndef(MIB, get(X86::SBB8rr)); 3972 case X86::SETB_C16r: 3973 return Expand2AddrUndef(MIB, get(X86::SBB16rr)); 3974 case X86::SETB_C32r: 3975 return Expand2AddrUndef(MIB, get(X86::SBB32rr)); 3976 case X86::SETB_C64r: 3977 return Expand2AddrUndef(MIB, get(X86::SBB64rr)); 3978 case X86::V_SET0: 3979 case X86::FsFLD0SS: 3980 case X86::FsFLD0SD: 3981 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr)); 3982 case X86::AVX_SET0: 3983 assert(HasAVX && "AVX not supported"); 3984 return Expand2AddrUndef(MIB, get(X86::VXORPSYrr)); 3985 case X86::AVX512_512_SET0: 3986 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr)); 3987 case X86::V_SETALLONES: 3988 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr)); 3989 case X86::AVX2_SETALLONES: 3990 return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr)); 3991 case X86::TEST8ri_NOREX: 3992 MI->setDesc(get(X86::TEST8ri)); 3993 return true; 3994 case X86::KSET0B: 3995 case X86::KSET0W: return Expand2AddrUndef(MIB, get(X86::KXORWrr)); 3996 case X86::KSET1B: 3997 case X86::KSET1W: return Expand2AddrUndef(MIB, get(X86::KXNORWrr)); 3998 } 3999 return false; 4000 } 4001 4002 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode, 4003 const SmallVectorImpl<MachineOperand> &MOs, 4004 MachineInstr *MI, 4005 const TargetInstrInfo &TII) { 4006 // Create the base instruction with the memory operand as the first part. 4007 // Omit the implicit operands, something BuildMI can't do. 4008 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), 4009 MI->getDebugLoc(), true); 4010 MachineInstrBuilder MIB(MF, NewMI); 4011 unsigned NumAddrOps = MOs.size(); 4012 for (unsigned i = 0; i != NumAddrOps; ++i) 4013 MIB.addOperand(MOs[i]); 4014 if (NumAddrOps < 4) // FrameIndex only 4015 addOffset(MIB, 0); 4016 4017 // Loop over the rest of the ri operands, converting them over. 4018 unsigned NumOps = MI->getDesc().getNumOperands()-2; 4019 for (unsigned i = 0; i != NumOps; ++i) { 4020 MachineOperand &MO = MI->getOperand(i+2); 4021 MIB.addOperand(MO); 4022 } 4023 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) { 4024 MachineOperand &MO = MI->getOperand(i); 4025 MIB.addOperand(MO); 4026 } 4027 return MIB; 4028 } 4029 4030 static MachineInstr *FuseInst(MachineFunction &MF, 4031 unsigned Opcode, unsigned OpNo, 4032 const SmallVectorImpl<MachineOperand> &MOs, 4033 MachineInstr *MI, const TargetInstrInfo &TII) { 4034 // Omit the implicit operands, something BuildMI can't do. 4035 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), 4036 MI->getDebugLoc(), true); 4037 MachineInstrBuilder MIB(MF, NewMI); 4038 4039 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 4040 MachineOperand &MO = MI->getOperand(i); 4041 if (i == OpNo) { 4042 assert(MO.isReg() && "Expected to fold into reg operand!"); 4043 unsigned NumAddrOps = MOs.size(); 4044 for (unsigned i = 0; i != NumAddrOps; ++i) 4045 MIB.addOperand(MOs[i]); 4046 if (NumAddrOps < 4) // FrameIndex only 4047 addOffset(MIB, 0); 4048 } else { 4049 MIB.addOperand(MO); 4050 } 4051 } 4052 return MIB; 4053 } 4054 4055 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode, 4056 const SmallVectorImpl<MachineOperand> &MOs, 4057 MachineInstr *MI) { 4058 MachineFunction &MF = *MI->getParent()->getParent(); 4059 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode)); 4060 4061 unsigned NumAddrOps = MOs.size(); 4062 for (unsigned i = 0; i != NumAddrOps; ++i) 4063 MIB.addOperand(MOs[i]); 4064 if (NumAddrOps < 4) // FrameIndex only 4065 addOffset(MIB, 0); 4066 return MIB.addImm(0); 4067 } 4068 4069 MachineInstr* 4070 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 4071 MachineInstr *MI, unsigned i, 4072 const SmallVectorImpl<MachineOperand> &MOs, 4073 unsigned Size, unsigned Align) const { 4074 const DenseMap<unsigned, 4075 std::pair<unsigned,unsigned> > *OpcodeTablePtr = nullptr; 4076 bool isCallRegIndirect = Subtarget.callRegIndirect(); 4077 bool isTwoAddrFold = false; 4078 4079 // Atom favors register form of call. So, we do not fold loads into calls 4080 // when X86Subtarget is Atom. 4081 if (isCallRegIndirect && 4082 (MI->getOpcode() == X86::CALL32r || MI->getOpcode() == X86::CALL64r)) { 4083 return nullptr; 4084 } 4085 4086 unsigned NumOps = MI->getDesc().getNumOperands(); 4087 bool isTwoAddr = NumOps > 1 && 4088 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1; 4089 4090 // FIXME: AsmPrinter doesn't know how to handle 4091 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding. 4092 if (MI->getOpcode() == X86::ADD32ri && 4093 MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS) 4094 return nullptr; 4095 4096 MachineInstr *NewMI = nullptr; 4097 // Folding a memory location into the two-address part of a two-address 4098 // instruction is different than folding it other places. It requires 4099 // replacing the *two* registers with the memory location. 4100 if (isTwoAddr && NumOps >= 2 && i < 2 && 4101 MI->getOperand(0).isReg() && 4102 MI->getOperand(1).isReg() && 4103 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) { 4104 OpcodeTablePtr = &RegOp2MemOpTable2Addr; 4105 isTwoAddrFold = true; 4106 } else if (i == 0) { // If operand 0 4107 if (MI->getOpcode() == X86::MOV32r0) { 4108 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI); 4109 if (NewMI) 4110 return NewMI; 4111 } 4112 4113 OpcodeTablePtr = &RegOp2MemOpTable0; 4114 } else if (i == 1) { 4115 OpcodeTablePtr = &RegOp2MemOpTable1; 4116 } else if (i == 2) { 4117 OpcodeTablePtr = &RegOp2MemOpTable2; 4118 } else if (i == 3) { 4119 OpcodeTablePtr = &RegOp2MemOpTable3; 4120 } 4121 4122 // If table selected... 4123 if (OpcodeTablePtr) { 4124 // Find the Opcode to fuse 4125 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 4126 OpcodeTablePtr->find(MI->getOpcode()); 4127 if (I != OpcodeTablePtr->end()) { 4128 unsigned Opcode = I->second.first; 4129 unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT; 4130 if (Align < MinAlign) 4131 return nullptr; 4132 bool NarrowToMOV32rm = false; 4133 if (Size) { 4134 unsigned RCSize = getRegClass(MI->getDesc(), i, &RI, MF)->getSize(); 4135 if (Size < RCSize) { 4136 // Check if it's safe to fold the load. If the size of the object is 4137 // narrower than the load width, then it's not. 4138 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4) 4139 return nullptr; 4140 // If this is a 64-bit load, but the spill slot is 32, then we can do 4141 // a 32-bit load which is implicitly zero-extended. This likely is due 4142 // to liveintervalanalysis remat'ing a load from stack slot. 4143 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg()) 4144 return nullptr; 4145 Opcode = X86::MOV32rm; 4146 NarrowToMOV32rm = true; 4147 } 4148 } 4149 4150 if (isTwoAddrFold) 4151 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this); 4152 else 4153 NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this); 4154 4155 if (NarrowToMOV32rm) { 4156 // If this is the special case where we use a MOV32rm to load a 32-bit 4157 // value and zero-extend the top bits. Change the destination register 4158 // to a 32-bit one. 4159 unsigned DstReg = NewMI->getOperand(0).getReg(); 4160 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) 4161 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, 4162 X86::sub_32bit)); 4163 else 4164 NewMI->getOperand(0).setSubReg(X86::sub_32bit); 4165 } 4166 return NewMI; 4167 } 4168 } 4169 4170 // No fusion 4171 if (PrintFailedFusing && !MI->isCopy()) 4172 dbgs() << "We failed to fuse operand " << i << " in " << *MI; 4173 return nullptr; 4174 } 4175 4176 /// hasPartialRegUpdate - Return true for all instructions that only update 4177 /// the first 32 or 64-bits of the destination register and leave the rest 4178 /// unmodified. This can be used to avoid folding loads if the instructions 4179 /// only update part of the destination register, and the non-updated part is 4180 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these 4181 /// instructions breaks the partial register dependency and it can improve 4182 /// performance. e.g.: 4183 /// 4184 /// movss (%rdi), %xmm0 4185 /// cvtss2sd %xmm0, %xmm0 4186 /// 4187 /// Instead of 4188 /// cvtss2sd (%rdi), %xmm0 4189 /// 4190 /// FIXME: This should be turned into a TSFlags. 4191 /// 4192 static bool hasPartialRegUpdate(unsigned Opcode) { 4193 switch (Opcode) { 4194 case X86::CVTSI2SSrr: 4195 case X86::CVTSI2SS64rr: 4196 case X86::CVTSI2SDrr: 4197 case X86::CVTSI2SD64rr: 4198 case X86::CVTSD2SSrr: 4199 case X86::Int_CVTSD2SSrr: 4200 case X86::CVTSS2SDrr: 4201 case X86::Int_CVTSS2SDrr: 4202 case X86::RCPSSr: 4203 case X86::RCPSSr_Int: 4204 case X86::ROUNDSDr: 4205 case X86::ROUNDSDr_Int: 4206 case X86::ROUNDSSr: 4207 case X86::ROUNDSSr_Int: 4208 case X86::RSQRTSSr: 4209 case X86::RSQRTSSr_Int: 4210 case X86::SQRTSSr: 4211 case X86::SQRTSSr_Int: 4212 return true; 4213 } 4214 4215 return false; 4216 } 4217 4218 /// getPartialRegUpdateClearance - Inform the ExeDepsFix pass how many idle 4219 /// instructions we would like before a partial register update. 4220 unsigned X86InstrInfo:: 4221 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, 4222 const TargetRegisterInfo *TRI) const { 4223 if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode())) 4224 return 0; 4225 4226 // If MI is marked as reading Reg, the partial register update is wanted. 4227 const MachineOperand &MO = MI->getOperand(0); 4228 unsigned Reg = MO.getReg(); 4229 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 4230 if (MO.readsReg() || MI->readsVirtualRegister(Reg)) 4231 return 0; 4232 } else { 4233 if (MI->readsRegister(Reg, TRI)) 4234 return 0; 4235 } 4236 4237 // If any of the preceding 16 instructions are reading Reg, insert a 4238 // dependency breaking instruction. The magic number is based on a few 4239 // Nehalem experiments. 4240 return 16; 4241 } 4242 4243 // Return true for any instruction the copies the high bits of the first source 4244 // operand into the unused high bits of the destination operand. 4245 static bool hasUndefRegUpdate(unsigned Opcode) { 4246 switch (Opcode) { 4247 case X86::VCVTSI2SSrr: 4248 case X86::Int_VCVTSI2SSrr: 4249 case X86::VCVTSI2SS64rr: 4250 case X86::Int_VCVTSI2SS64rr: 4251 case X86::VCVTSI2SDrr: 4252 case X86::Int_VCVTSI2SDrr: 4253 case X86::VCVTSI2SD64rr: 4254 case X86::Int_VCVTSI2SD64rr: 4255 case X86::VCVTSD2SSrr: 4256 case X86::Int_VCVTSD2SSrr: 4257 case X86::VCVTSS2SDrr: 4258 case X86::Int_VCVTSS2SDrr: 4259 case X86::VRCPSSr: 4260 case X86::VROUNDSDr: 4261 case X86::VROUNDSDr_Int: 4262 case X86::VROUNDSSr: 4263 case X86::VROUNDSSr_Int: 4264 case X86::VRSQRTSSr: 4265 case X86::VSQRTSSr: 4266 4267 // AVX-512 4268 case X86::VCVTSD2SSZrr: 4269 case X86::VCVTSS2SDZrr: 4270 return true; 4271 } 4272 4273 return false; 4274 } 4275 4276 /// Inform the ExeDepsFix pass how many idle instructions we would like before 4277 /// certain undef register reads. 4278 /// 4279 /// This catches the VCVTSI2SD family of instructions: 4280 /// 4281 /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14 4282 /// 4283 /// We should to be careful *not* to catch VXOR idioms which are presumably 4284 /// handled specially in the pipeline: 4285 /// 4286 /// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1 4287 /// 4288 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the 4289 /// high bits that are passed-through are not live. 4290 unsigned X86InstrInfo:: 4291 getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum, 4292 const TargetRegisterInfo *TRI) const { 4293 if (!hasUndefRegUpdate(MI->getOpcode())) 4294 return 0; 4295 4296 // Set the OpNum parameter to the first source operand. 4297 OpNum = 1; 4298 4299 const MachineOperand &MO = MI->getOperand(OpNum); 4300 if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) { 4301 // Use the same magic number as getPartialRegUpdateClearance. 4302 return 16; 4303 } 4304 return 0; 4305 } 4306 4307 void X86InstrInfo:: 4308 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, 4309 const TargetRegisterInfo *TRI) const { 4310 unsigned Reg = MI->getOperand(OpNum).getReg(); 4311 // If MI kills this register, the false dependence is already broken. 4312 if (MI->killsRegister(Reg, TRI)) 4313 return; 4314 if (X86::VR128RegClass.contains(Reg)) { 4315 // These instructions are all floating point domain, so xorps is the best 4316 // choice. 4317 bool HasAVX = Subtarget.hasAVX(); 4318 unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr; 4319 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg) 4320 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef); 4321 } else if (X86::VR256RegClass.contains(Reg)) { 4322 // Use vxorps to clear the full ymm register. 4323 // It wants to read and write the xmm sub-register. 4324 unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm); 4325 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg) 4326 .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef) 4327 .addReg(Reg, RegState::ImplicitDefine); 4328 } else 4329 return; 4330 MI->addRegisterKilled(Reg, TRI, true); 4331 } 4332 4333 MachineInstr* 4334 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, 4335 const SmallVectorImpl<unsigned> &Ops, 4336 int FrameIndex) const { 4337 // Check switch flag 4338 if (NoFusing) return nullptr; 4339 4340 // Unless optimizing for size, don't fold to avoid partial 4341 // register update stalls 4342 if (!MF.getFunction()->getAttributes(). 4343 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize) && 4344 hasPartialRegUpdate(MI->getOpcode())) 4345 return nullptr; 4346 4347 const MachineFrameInfo *MFI = MF.getFrameInfo(); 4348 unsigned Size = MFI->getObjectSize(FrameIndex); 4349 unsigned Alignment = MFI->getObjectAlignment(FrameIndex); 4350 // If the function stack isn't realigned we don't want to fold instructions 4351 // that need increased alignment. 4352 if (!RI.needsStackRealignment(MF)) 4353 Alignment = std::min( 4354 Alignment, MF.getTarget().getFrameLowering()->getStackAlignment()); 4355 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 4356 unsigned NewOpc = 0; 4357 unsigned RCSize = 0; 4358 switch (MI->getOpcode()) { 4359 default: return nullptr; 4360 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break; 4361 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break; 4362 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break; 4363 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break; 4364 } 4365 // Check if it's safe to fold the load. If the size of the object is 4366 // narrower than the load width, then it's not. 4367 if (Size < RCSize) 4368 return nullptr; 4369 // Change to CMPXXri r, 0 first. 4370 MI->setDesc(get(NewOpc)); 4371 MI->getOperand(1).ChangeToImmediate(0); 4372 } else if (Ops.size() != 1) 4373 return nullptr; 4374 4375 SmallVector<MachineOperand,4> MOs; 4376 MOs.push_back(MachineOperand::CreateFI(FrameIndex)); 4377 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment); 4378 } 4379 4380 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 4381 MachineInstr *MI, 4382 const SmallVectorImpl<unsigned> &Ops, 4383 MachineInstr *LoadMI) const { 4384 // If loading from a FrameIndex, fold directly from the FrameIndex. 4385 unsigned NumOps = LoadMI->getDesc().getNumOperands(); 4386 int FrameIndex; 4387 if (isLoadFromStackSlot(LoadMI, FrameIndex)) 4388 return foldMemoryOperandImpl(MF, MI, Ops, FrameIndex); 4389 4390 // Check switch flag 4391 if (NoFusing) return nullptr; 4392 4393 // Unless optimizing for size, don't fold to avoid partial 4394 // register update stalls 4395 if (!MF.getFunction()->getAttributes(). 4396 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize) && 4397 hasPartialRegUpdate(MI->getOpcode())) 4398 return nullptr; 4399 4400 // Determine the alignment of the load. 4401 unsigned Alignment = 0; 4402 if (LoadMI->hasOneMemOperand()) 4403 Alignment = (*LoadMI->memoperands_begin())->getAlignment(); 4404 else 4405 switch (LoadMI->getOpcode()) { 4406 case X86::AVX2_SETALLONES: 4407 case X86::AVX_SET0: 4408 Alignment = 32; 4409 break; 4410 case X86::V_SET0: 4411 case X86::V_SETALLONES: 4412 Alignment = 16; 4413 break; 4414 case X86::FsFLD0SD: 4415 Alignment = 8; 4416 break; 4417 case X86::FsFLD0SS: 4418 Alignment = 4; 4419 break; 4420 default: 4421 return nullptr; 4422 } 4423 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 4424 unsigned NewOpc = 0; 4425 switch (MI->getOpcode()) { 4426 default: return nullptr; 4427 case X86::TEST8rr: NewOpc = X86::CMP8ri; break; 4428 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break; 4429 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break; 4430 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break; 4431 } 4432 // Change to CMPXXri r, 0 first. 4433 MI->setDesc(get(NewOpc)); 4434 MI->getOperand(1).ChangeToImmediate(0); 4435 } else if (Ops.size() != 1) 4436 return nullptr; 4437 4438 // Make sure the subregisters match. 4439 // Otherwise we risk changing the size of the load. 4440 if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg()) 4441 return nullptr; 4442 4443 SmallVector<MachineOperand,X86::AddrNumOperands> MOs; 4444 switch (LoadMI->getOpcode()) { 4445 case X86::V_SET0: 4446 case X86::V_SETALLONES: 4447 case X86::AVX2_SETALLONES: 4448 case X86::AVX_SET0: 4449 case X86::FsFLD0SD: 4450 case X86::FsFLD0SS: { 4451 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure. 4452 // Create a constant-pool entry and operands to load from it. 4453 4454 // Medium and large mode can't fold loads this way. 4455 if (MF.getTarget().getCodeModel() != CodeModel::Small && 4456 MF.getTarget().getCodeModel() != CodeModel::Kernel) 4457 return nullptr; 4458 4459 // x86-32 PIC requires a PIC base register for constant pools. 4460 unsigned PICBase = 0; 4461 if (MF.getTarget().getRelocationModel() == Reloc::PIC_) { 4462 if (Subtarget.is64Bit()) 4463 PICBase = X86::RIP; 4464 else 4465 // FIXME: PICBase = getGlobalBaseReg(&MF); 4466 // This doesn't work for several reasons. 4467 // 1. GlobalBaseReg may have been spilled. 4468 // 2. It may not be live at MI. 4469 return nullptr; 4470 } 4471 4472 // Create a constant-pool entry. 4473 MachineConstantPool &MCP = *MF.getConstantPool(); 4474 Type *Ty; 4475 unsigned Opc = LoadMI->getOpcode(); 4476 if (Opc == X86::FsFLD0SS) 4477 Ty = Type::getFloatTy(MF.getFunction()->getContext()); 4478 else if (Opc == X86::FsFLD0SD) 4479 Ty = Type::getDoubleTy(MF.getFunction()->getContext()); 4480 else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0) 4481 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8); 4482 else 4483 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4); 4484 4485 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES); 4486 const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) : 4487 Constant::getNullValue(Ty); 4488 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment); 4489 4490 // Create operands to load from the constant pool entry. 4491 MOs.push_back(MachineOperand::CreateReg(PICBase, false)); 4492 MOs.push_back(MachineOperand::CreateImm(1)); 4493 MOs.push_back(MachineOperand::CreateReg(0, false)); 4494 MOs.push_back(MachineOperand::CreateCPI(CPI, 0)); 4495 MOs.push_back(MachineOperand::CreateReg(0, false)); 4496 break; 4497 } 4498 default: { 4499 if ((LoadMI->getOpcode() == X86::MOVSSrm || 4500 LoadMI->getOpcode() == X86::VMOVSSrm) && 4501 MF.getRegInfo().getRegClass(LoadMI->getOperand(0).getReg())->getSize() 4502 > 4) 4503 // These instructions only load 32 bits, we can't fold them if the 4504 // destination register is wider than 32 bits (4 bytes). 4505 return nullptr; 4506 if ((LoadMI->getOpcode() == X86::MOVSDrm || 4507 LoadMI->getOpcode() == X86::VMOVSDrm) && 4508 MF.getRegInfo().getRegClass(LoadMI->getOperand(0).getReg())->getSize() 4509 > 8) 4510 // These instructions only load 64 bits, we can't fold them if the 4511 // destination register is wider than 64 bits (8 bytes). 4512 return nullptr; 4513 4514 // Folding a normal load. Just copy the load's address operands. 4515 for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i) 4516 MOs.push_back(LoadMI->getOperand(i)); 4517 break; 4518 } 4519 } 4520 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment); 4521 } 4522 4523 4524 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI, 4525 const SmallVectorImpl<unsigned> &Ops) const { 4526 // Check switch flag 4527 if (NoFusing) return 0; 4528 4529 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 4530 switch (MI->getOpcode()) { 4531 default: return false; 4532 case X86::TEST8rr: 4533 case X86::TEST16rr: 4534 case X86::TEST32rr: 4535 case X86::TEST64rr: 4536 return true; 4537 case X86::ADD32ri: 4538 // FIXME: AsmPrinter doesn't know how to handle 4539 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding. 4540 if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS) 4541 return false; 4542 break; 4543 } 4544 } 4545 4546 if (Ops.size() != 1) 4547 return false; 4548 4549 unsigned OpNum = Ops[0]; 4550 unsigned Opc = MI->getOpcode(); 4551 unsigned NumOps = MI->getDesc().getNumOperands(); 4552 bool isTwoAddr = NumOps > 1 && 4553 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1; 4554 4555 // Folding a memory location into the two-address part of a two-address 4556 // instruction is different than folding it other places. It requires 4557 // replacing the *two* registers with the memory location. 4558 const DenseMap<unsigned, 4559 std::pair<unsigned,unsigned> > *OpcodeTablePtr = nullptr; 4560 if (isTwoAddr && NumOps >= 2 && OpNum < 2) { 4561 OpcodeTablePtr = &RegOp2MemOpTable2Addr; 4562 } else if (OpNum == 0) { // If operand 0 4563 if (Opc == X86::MOV32r0) 4564 return true; 4565 4566 OpcodeTablePtr = &RegOp2MemOpTable0; 4567 } else if (OpNum == 1) { 4568 OpcodeTablePtr = &RegOp2MemOpTable1; 4569 } else if (OpNum == 2) { 4570 OpcodeTablePtr = &RegOp2MemOpTable2; 4571 } else if (OpNum == 3) { 4572 OpcodeTablePtr = &RegOp2MemOpTable3; 4573 } 4574 4575 if (OpcodeTablePtr && OpcodeTablePtr->count(Opc)) 4576 return true; 4577 return TargetInstrInfo::canFoldMemoryOperand(MI, Ops); 4578 } 4579 4580 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 4581 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 4582 SmallVectorImpl<MachineInstr*> &NewMIs) const { 4583 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 4584 MemOp2RegOpTable.find(MI->getOpcode()); 4585 if (I == MemOp2RegOpTable.end()) 4586 return false; 4587 unsigned Opc = I->second.first; 4588 unsigned Index = I->second.second & TB_INDEX_MASK; 4589 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD; 4590 bool FoldedStore = I->second.second & TB_FOLDED_STORE; 4591 if (UnfoldLoad && !FoldedLoad) 4592 return false; 4593 UnfoldLoad &= FoldedLoad; 4594 if (UnfoldStore && !FoldedStore) 4595 return false; 4596 UnfoldStore &= FoldedStore; 4597 4598 const MCInstrDesc &MCID = get(Opc); 4599 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF); 4600 if (!MI->hasOneMemOperand() && 4601 RC == &X86::VR128RegClass && 4602 !Subtarget.isUnalignedMemAccessFast()) 4603 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will 4604 // conservatively assume the address is unaligned. That's bad for 4605 // performance. 4606 return false; 4607 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps; 4608 SmallVector<MachineOperand,2> BeforeOps; 4609 SmallVector<MachineOperand,2> AfterOps; 4610 SmallVector<MachineOperand,4> ImpOps; 4611 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 4612 MachineOperand &Op = MI->getOperand(i); 4613 if (i >= Index && i < Index + X86::AddrNumOperands) 4614 AddrOps.push_back(Op); 4615 else if (Op.isReg() && Op.isImplicit()) 4616 ImpOps.push_back(Op); 4617 else if (i < Index) 4618 BeforeOps.push_back(Op); 4619 else if (i > Index) 4620 AfterOps.push_back(Op); 4621 } 4622 4623 // Emit the load instruction. 4624 if (UnfoldLoad) { 4625 std::pair<MachineInstr::mmo_iterator, 4626 MachineInstr::mmo_iterator> MMOs = 4627 MF.extractLoadMemRefs(MI->memoperands_begin(), 4628 MI->memoperands_end()); 4629 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs); 4630 if (UnfoldStore) { 4631 // Address operands cannot be marked isKill. 4632 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) { 4633 MachineOperand &MO = NewMIs[0]->getOperand(i); 4634 if (MO.isReg()) 4635 MO.setIsKill(false); 4636 } 4637 } 4638 } 4639 4640 // Emit the data processing instruction. 4641 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true); 4642 MachineInstrBuilder MIB(MF, DataMI); 4643 4644 if (FoldedStore) 4645 MIB.addReg(Reg, RegState::Define); 4646 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i) 4647 MIB.addOperand(BeforeOps[i]); 4648 if (FoldedLoad) 4649 MIB.addReg(Reg); 4650 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i) 4651 MIB.addOperand(AfterOps[i]); 4652 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) { 4653 MachineOperand &MO = ImpOps[i]; 4654 MIB.addReg(MO.getReg(), 4655 getDefRegState(MO.isDef()) | 4656 RegState::Implicit | 4657 getKillRegState(MO.isKill()) | 4658 getDeadRegState(MO.isDead()) | 4659 getUndefRegState(MO.isUndef())); 4660 } 4661 // Change CMP32ri r, 0 back to TEST32rr r, r, etc. 4662 switch (DataMI->getOpcode()) { 4663 default: break; 4664 case X86::CMP64ri32: 4665 case X86::CMP64ri8: 4666 case X86::CMP32ri: 4667 case X86::CMP32ri8: 4668 case X86::CMP16ri: 4669 case X86::CMP16ri8: 4670 case X86::CMP8ri: { 4671 MachineOperand &MO0 = DataMI->getOperand(0); 4672 MachineOperand &MO1 = DataMI->getOperand(1); 4673 if (MO1.getImm() == 0) { 4674 unsigned NewOpc; 4675 switch (DataMI->getOpcode()) { 4676 default: llvm_unreachable("Unreachable!"); 4677 case X86::CMP64ri8: 4678 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break; 4679 case X86::CMP32ri8: 4680 case X86::CMP32ri: NewOpc = X86::TEST32rr; break; 4681 case X86::CMP16ri8: 4682 case X86::CMP16ri: NewOpc = X86::TEST16rr; break; 4683 case X86::CMP8ri: NewOpc = X86::TEST8rr; break; 4684 } 4685 DataMI->setDesc(get(NewOpc)); 4686 MO1.ChangeToRegister(MO0.getReg(), false); 4687 } 4688 } 4689 } 4690 NewMIs.push_back(DataMI); 4691 4692 // Emit the store instruction. 4693 if (UnfoldStore) { 4694 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF); 4695 std::pair<MachineInstr::mmo_iterator, 4696 MachineInstr::mmo_iterator> MMOs = 4697 MF.extractStoreMemRefs(MI->memoperands_begin(), 4698 MI->memoperands_end()); 4699 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs); 4700 } 4701 4702 return true; 4703 } 4704 4705 bool 4706 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 4707 SmallVectorImpl<SDNode*> &NewNodes) const { 4708 if (!N->isMachineOpcode()) 4709 return false; 4710 4711 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 4712 MemOp2RegOpTable.find(N->getMachineOpcode()); 4713 if (I == MemOp2RegOpTable.end()) 4714 return false; 4715 unsigned Opc = I->second.first; 4716 unsigned Index = I->second.second & TB_INDEX_MASK; 4717 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD; 4718 bool FoldedStore = I->second.second & TB_FOLDED_STORE; 4719 const MCInstrDesc &MCID = get(Opc); 4720 MachineFunction &MF = DAG.getMachineFunction(); 4721 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF); 4722 unsigned NumDefs = MCID.NumDefs; 4723 std::vector<SDValue> AddrOps; 4724 std::vector<SDValue> BeforeOps; 4725 std::vector<SDValue> AfterOps; 4726 SDLoc dl(N); 4727 unsigned NumOps = N->getNumOperands(); 4728 for (unsigned i = 0; i != NumOps-1; ++i) { 4729 SDValue Op = N->getOperand(i); 4730 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands) 4731 AddrOps.push_back(Op); 4732 else if (i < Index-NumDefs) 4733 BeforeOps.push_back(Op); 4734 else if (i > Index-NumDefs) 4735 AfterOps.push_back(Op); 4736 } 4737 SDValue Chain = N->getOperand(NumOps-1); 4738 AddrOps.push_back(Chain); 4739 4740 // Emit the load instruction. 4741 SDNode *Load = nullptr; 4742 if (FoldedLoad) { 4743 EVT VT = *RC->vt_begin(); 4744 std::pair<MachineInstr::mmo_iterator, 4745 MachineInstr::mmo_iterator> MMOs = 4746 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(), 4747 cast<MachineSDNode>(N)->memoperands_end()); 4748 if (!(*MMOs.first) && 4749 RC == &X86::VR128RegClass && 4750 !Subtarget.isUnalignedMemAccessFast()) 4751 // Do not introduce a slow unaligned load. 4752 return false; 4753 unsigned Alignment = RC->getSize() == 32 ? 32 : 16; 4754 bool isAligned = (*MMOs.first) && 4755 (*MMOs.first)->getAlignment() >= Alignment; 4756 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl, 4757 VT, MVT::Other, AddrOps); 4758 NewNodes.push_back(Load); 4759 4760 // Preserve memory reference information. 4761 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second); 4762 } 4763 4764 // Emit the data processing instruction. 4765 std::vector<EVT> VTs; 4766 const TargetRegisterClass *DstRC = nullptr; 4767 if (MCID.getNumDefs() > 0) { 4768 DstRC = getRegClass(MCID, 0, &RI, MF); 4769 VTs.push_back(*DstRC->vt_begin()); 4770 } 4771 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) { 4772 EVT VT = N->getValueType(i); 4773 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs()) 4774 VTs.push_back(VT); 4775 } 4776 if (Load) 4777 BeforeOps.push_back(SDValue(Load, 0)); 4778 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps)); 4779 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps); 4780 NewNodes.push_back(NewNode); 4781 4782 // Emit the store instruction. 4783 if (FoldedStore) { 4784 AddrOps.pop_back(); 4785 AddrOps.push_back(SDValue(NewNode, 0)); 4786 AddrOps.push_back(Chain); 4787 std::pair<MachineInstr::mmo_iterator, 4788 MachineInstr::mmo_iterator> MMOs = 4789 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(), 4790 cast<MachineSDNode>(N)->memoperands_end()); 4791 if (!(*MMOs.first) && 4792 RC == &X86::VR128RegClass && 4793 !Subtarget.isUnalignedMemAccessFast()) 4794 // Do not introduce a slow unaligned store. 4795 return false; 4796 unsigned Alignment = RC->getSize() == 32 ? 32 : 16; 4797 bool isAligned = (*MMOs.first) && 4798 (*MMOs.first)->getAlignment() >= Alignment; 4799 SDNode *Store = 4800 DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget), 4801 dl, MVT::Other, AddrOps); 4802 NewNodes.push_back(Store); 4803 4804 // Preserve memory reference information. 4805 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second); 4806 } 4807 4808 return true; 4809 } 4810 4811 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc, 4812 bool UnfoldLoad, bool UnfoldStore, 4813 unsigned *LoadRegIndex) const { 4814 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 4815 MemOp2RegOpTable.find(Opc); 4816 if (I == MemOp2RegOpTable.end()) 4817 return 0; 4818 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD; 4819 bool FoldedStore = I->second.second & TB_FOLDED_STORE; 4820 if (UnfoldLoad && !FoldedLoad) 4821 return 0; 4822 if (UnfoldStore && !FoldedStore) 4823 return 0; 4824 if (LoadRegIndex) 4825 *LoadRegIndex = I->second.second & TB_INDEX_MASK; 4826 return I->second.first; 4827 } 4828 4829 bool 4830 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 4831 int64_t &Offset1, int64_t &Offset2) const { 4832 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) 4833 return false; 4834 unsigned Opc1 = Load1->getMachineOpcode(); 4835 unsigned Opc2 = Load2->getMachineOpcode(); 4836 switch (Opc1) { 4837 default: return false; 4838 case X86::MOV8rm: 4839 case X86::MOV16rm: 4840 case X86::MOV32rm: 4841 case X86::MOV64rm: 4842 case X86::LD_Fp32m: 4843 case X86::LD_Fp64m: 4844 case X86::LD_Fp80m: 4845 case X86::MOVSSrm: 4846 case X86::MOVSDrm: 4847 case X86::MMX_MOVD64rm: 4848 case X86::MMX_MOVQ64rm: 4849 case X86::FsMOVAPSrm: 4850 case X86::FsMOVAPDrm: 4851 case X86::MOVAPSrm: 4852 case X86::MOVUPSrm: 4853 case X86::MOVAPDrm: 4854 case X86::MOVDQArm: 4855 case X86::MOVDQUrm: 4856 // AVX load instructions 4857 case X86::VMOVSSrm: 4858 case X86::VMOVSDrm: 4859 case X86::FsVMOVAPSrm: 4860 case X86::FsVMOVAPDrm: 4861 case X86::VMOVAPSrm: 4862 case X86::VMOVUPSrm: 4863 case X86::VMOVAPDrm: 4864 case X86::VMOVDQArm: 4865 case X86::VMOVDQUrm: 4866 case X86::VMOVAPSYrm: 4867 case X86::VMOVUPSYrm: 4868 case X86::VMOVAPDYrm: 4869 case X86::VMOVDQAYrm: 4870 case X86::VMOVDQUYrm: 4871 break; 4872 } 4873 switch (Opc2) { 4874 default: return false; 4875 case X86::MOV8rm: 4876 case X86::MOV16rm: 4877 case X86::MOV32rm: 4878 case X86::MOV64rm: 4879 case X86::LD_Fp32m: 4880 case X86::LD_Fp64m: 4881 case X86::LD_Fp80m: 4882 case X86::MOVSSrm: 4883 case X86::MOVSDrm: 4884 case X86::MMX_MOVD64rm: 4885 case X86::MMX_MOVQ64rm: 4886 case X86::FsMOVAPSrm: 4887 case X86::FsMOVAPDrm: 4888 case X86::MOVAPSrm: 4889 case X86::MOVUPSrm: 4890 case X86::MOVAPDrm: 4891 case X86::MOVDQArm: 4892 case X86::MOVDQUrm: 4893 // AVX load instructions 4894 case X86::VMOVSSrm: 4895 case X86::VMOVSDrm: 4896 case X86::FsVMOVAPSrm: 4897 case X86::FsVMOVAPDrm: 4898 case X86::VMOVAPSrm: 4899 case X86::VMOVUPSrm: 4900 case X86::VMOVAPDrm: 4901 case X86::VMOVDQArm: 4902 case X86::VMOVDQUrm: 4903 case X86::VMOVAPSYrm: 4904 case X86::VMOVUPSYrm: 4905 case X86::VMOVAPDYrm: 4906 case X86::VMOVDQAYrm: 4907 case X86::VMOVDQUYrm: 4908 break; 4909 } 4910 4911 // Check if chain operands and base addresses match. 4912 if (Load1->getOperand(0) != Load2->getOperand(0) || 4913 Load1->getOperand(5) != Load2->getOperand(5)) 4914 return false; 4915 // Segment operands should match as well. 4916 if (Load1->getOperand(4) != Load2->getOperand(4)) 4917 return false; 4918 // Scale should be 1, Index should be Reg0. 4919 if (Load1->getOperand(1) == Load2->getOperand(1) && 4920 Load1->getOperand(2) == Load2->getOperand(2)) { 4921 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1) 4922 return false; 4923 4924 // Now let's examine the displacements. 4925 if (isa<ConstantSDNode>(Load1->getOperand(3)) && 4926 isa<ConstantSDNode>(Load2->getOperand(3))) { 4927 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue(); 4928 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue(); 4929 return true; 4930 } 4931 } 4932 return false; 4933 } 4934 4935 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 4936 int64_t Offset1, int64_t Offset2, 4937 unsigned NumLoads) const { 4938 assert(Offset2 > Offset1); 4939 if ((Offset2 - Offset1) / 8 > 64) 4940 return false; 4941 4942 unsigned Opc1 = Load1->getMachineOpcode(); 4943 unsigned Opc2 = Load2->getMachineOpcode(); 4944 if (Opc1 != Opc2) 4945 return false; // FIXME: overly conservative? 4946 4947 switch (Opc1) { 4948 default: break; 4949 case X86::LD_Fp32m: 4950 case X86::LD_Fp64m: 4951 case X86::LD_Fp80m: 4952 case X86::MMX_MOVD64rm: 4953 case X86::MMX_MOVQ64rm: 4954 return false; 4955 } 4956 4957 EVT VT = Load1->getValueType(0); 4958 switch (VT.getSimpleVT().SimpleTy) { 4959 default: 4960 // XMM registers. In 64-bit mode we can be a bit more aggressive since we 4961 // have 16 of them to play with. 4962 if (Subtarget.is64Bit()) { 4963 if (NumLoads >= 3) 4964 return false; 4965 } else if (NumLoads) { 4966 return false; 4967 } 4968 break; 4969 case MVT::i8: 4970 case MVT::i16: 4971 case MVT::i32: 4972 case MVT::i64: 4973 case MVT::f32: 4974 case MVT::f64: 4975 if (NumLoads) 4976 return false; 4977 break; 4978 } 4979 4980 return true; 4981 } 4982 4983 bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr* First, 4984 MachineInstr *Second) const { 4985 // Check if this processor supports macro-fusion. Since this is a minor 4986 // heuristic, we haven't specifically reserved a feature. hasAVX is a decent 4987 // proxy for SandyBridge+. 4988 if (!Subtarget.hasAVX()) 4989 return false; 4990 4991 enum { 4992 FuseTest, 4993 FuseCmp, 4994 FuseInc 4995 } FuseKind; 4996 4997 switch(Second->getOpcode()) { 4998 default: 4999 return false; 5000 case X86::JE_4: 5001 case X86::JNE_4: 5002 case X86::JL_4: 5003 case X86::JLE_4: 5004 case X86::JG_4: 5005 case X86::JGE_4: 5006 FuseKind = FuseInc; 5007 break; 5008 case X86::JB_4: 5009 case X86::JBE_4: 5010 case X86::JA_4: 5011 case X86::JAE_4: 5012 FuseKind = FuseCmp; 5013 break; 5014 case X86::JS_4: 5015 case X86::JNS_4: 5016 case X86::JP_4: 5017 case X86::JNP_4: 5018 case X86::JO_4: 5019 case X86::JNO_4: 5020 FuseKind = FuseTest; 5021 break; 5022 } 5023 switch (First->getOpcode()) { 5024 default: 5025 return false; 5026 case X86::TEST8rr: 5027 case X86::TEST16rr: 5028 case X86::TEST32rr: 5029 case X86::TEST64rr: 5030 case X86::TEST8ri: 5031 case X86::TEST16ri: 5032 case X86::TEST32ri: 5033 case X86::TEST32i32: 5034 case X86::TEST64i32: 5035 case X86::TEST64ri32: 5036 case X86::TEST8rm: 5037 case X86::TEST16rm: 5038 case X86::TEST32rm: 5039 case X86::TEST64rm: 5040 case X86::TEST8ri_NOREX: 5041 case X86::AND16i16: 5042 case X86::AND16ri: 5043 case X86::AND16ri8: 5044 case X86::AND16rm: 5045 case X86::AND16rr: 5046 case X86::AND32i32: 5047 case X86::AND32ri: 5048 case X86::AND32ri8: 5049 case X86::AND32rm: 5050 case X86::AND32rr: 5051 case X86::AND64i32: 5052 case X86::AND64ri32: 5053 case X86::AND64ri8: 5054 case X86::AND64rm: 5055 case X86::AND64rr: 5056 case X86::AND8i8: 5057 case X86::AND8ri: 5058 case X86::AND8rm: 5059 case X86::AND8rr: 5060 return true; 5061 case X86::CMP16i16: 5062 case X86::CMP16ri: 5063 case X86::CMP16ri8: 5064 case X86::CMP16rm: 5065 case X86::CMP16rr: 5066 case X86::CMP32i32: 5067 case X86::CMP32ri: 5068 case X86::CMP32ri8: 5069 case X86::CMP32rm: 5070 case X86::CMP32rr: 5071 case X86::CMP64i32: 5072 case X86::CMP64ri32: 5073 case X86::CMP64ri8: 5074 case X86::CMP64rm: 5075 case X86::CMP64rr: 5076 case X86::CMP8i8: 5077 case X86::CMP8ri: 5078 case X86::CMP8rm: 5079 case X86::CMP8rr: 5080 case X86::ADD16i16: 5081 case X86::ADD16ri: 5082 case X86::ADD16ri8: 5083 case X86::ADD16ri8_DB: 5084 case X86::ADD16ri_DB: 5085 case X86::ADD16rm: 5086 case X86::ADD16rr: 5087 case X86::ADD16rr_DB: 5088 case X86::ADD32i32: 5089 case X86::ADD32ri: 5090 case X86::ADD32ri8: 5091 case X86::ADD32ri8_DB: 5092 case X86::ADD32ri_DB: 5093 case X86::ADD32rm: 5094 case X86::ADD32rr: 5095 case X86::ADD32rr_DB: 5096 case X86::ADD64i32: 5097 case X86::ADD64ri32: 5098 case X86::ADD64ri32_DB: 5099 case X86::ADD64ri8: 5100 case X86::ADD64ri8_DB: 5101 case X86::ADD64rm: 5102 case X86::ADD64rr: 5103 case X86::ADD64rr_DB: 5104 case X86::ADD8i8: 5105 case X86::ADD8mi: 5106 case X86::ADD8mr: 5107 case X86::ADD8ri: 5108 case X86::ADD8rm: 5109 case X86::ADD8rr: 5110 case X86::SUB16i16: 5111 case X86::SUB16ri: 5112 case X86::SUB16ri8: 5113 case X86::SUB16rm: 5114 case X86::SUB16rr: 5115 case X86::SUB32i32: 5116 case X86::SUB32ri: 5117 case X86::SUB32ri8: 5118 case X86::SUB32rm: 5119 case X86::SUB32rr: 5120 case X86::SUB64i32: 5121 case X86::SUB64ri32: 5122 case X86::SUB64ri8: 5123 case X86::SUB64rm: 5124 case X86::SUB64rr: 5125 case X86::SUB8i8: 5126 case X86::SUB8ri: 5127 case X86::SUB8rm: 5128 case X86::SUB8rr: 5129 return FuseKind == FuseCmp || FuseKind == FuseInc; 5130 case X86::INC16r: 5131 case X86::INC32r: 5132 case X86::INC64_16r: 5133 case X86::INC64_32r: 5134 case X86::INC64r: 5135 case X86::INC8r: 5136 case X86::DEC16r: 5137 case X86::DEC32r: 5138 case X86::DEC64_16r: 5139 case X86::DEC64_32r: 5140 case X86::DEC64r: 5141 case X86::DEC8r: 5142 return FuseKind == FuseInc; 5143 } 5144 } 5145 5146 bool X86InstrInfo:: 5147 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 5148 assert(Cond.size() == 1 && "Invalid X86 branch condition!"); 5149 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm()); 5150 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E) 5151 return true; 5152 Cond[0].setImm(GetOppositeBranchCondition(CC)); 5153 return false; 5154 } 5155 5156 bool X86InstrInfo:: 5157 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 5158 // FIXME: Return false for x87 stack register classes for now. We can't 5159 // allow any loads of these registers before FpGet_ST0_80. 5160 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass || 5161 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass); 5162 } 5163 5164 /// getGlobalBaseReg - Return a virtual register initialized with the 5165 /// the global base register value. Output instructions required to 5166 /// initialize the register in the function entry block, if necessary. 5167 /// 5168 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo. 5169 /// 5170 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const { 5171 assert(!Subtarget.is64Bit() && 5172 "X86-64 PIC uses RIP relative addressing"); 5173 5174 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>(); 5175 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg(); 5176 if (GlobalBaseReg != 0) 5177 return GlobalBaseReg; 5178 5179 // Create the register. The code to initialize it is inserted 5180 // later, by the CGBR pass (below). 5181 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 5182 GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass); 5183 X86FI->setGlobalBaseReg(GlobalBaseReg); 5184 return GlobalBaseReg; 5185 } 5186 5187 // These are the replaceable SSE instructions. Some of these have Int variants 5188 // that we don't include here. We don't want to replace instructions selected 5189 // by intrinsics. 5190 static const uint16_t ReplaceableInstrs[][3] = { 5191 //PackedSingle PackedDouble PackedInt 5192 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr }, 5193 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm }, 5194 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr }, 5195 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr }, 5196 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm }, 5197 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr }, 5198 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm }, 5199 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr }, 5200 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm }, 5201 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr }, 5202 { X86::ORPSrm, X86::ORPDrm, X86::PORrm }, 5203 { X86::ORPSrr, X86::ORPDrr, X86::PORrr }, 5204 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm }, 5205 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr }, 5206 // AVX 128-bit support 5207 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr }, 5208 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm }, 5209 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr }, 5210 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr }, 5211 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm }, 5212 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr }, 5213 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm }, 5214 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr }, 5215 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm }, 5216 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr }, 5217 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm }, 5218 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr }, 5219 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm }, 5220 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr }, 5221 // AVX 256-bit support 5222 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr }, 5223 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm }, 5224 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr }, 5225 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr }, 5226 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm }, 5227 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr } 5228 }; 5229 5230 static const uint16_t ReplaceableInstrsAVX2[][3] = { 5231 //PackedSingle PackedDouble PackedInt 5232 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm }, 5233 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr }, 5234 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm }, 5235 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr }, 5236 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm }, 5237 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr }, 5238 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm }, 5239 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr }, 5240 { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr }, 5241 { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr }, 5242 { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm }, 5243 { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr }, 5244 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm }, 5245 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr }, 5246 { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm}, 5247 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr}, 5248 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr}, 5249 { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm}, 5250 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr}, 5251 { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm} 5252 }; 5253 5254 // FIXME: Some shuffle and unpack instructions have equivalents in different 5255 // domains, but they require a bit more work than just switching opcodes. 5256 5257 static const uint16_t *lookup(unsigned opcode, unsigned domain) { 5258 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i) 5259 if (ReplaceableInstrs[i][domain-1] == opcode) 5260 return ReplaceableInstrs[i]; 5261 return nullptr; 5262 } 5263 5264 static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) { 5265 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i) 5266 if (ReplaceableInstrsAVX2[i][domain-1] == opcode) 5267 return ReplaceableInstrsAVX2[i]; 5268 return nullptr; 5269 } 5270 5271 std::pair<uint16_t, uint16_t> 5272 X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const { 5273 uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3; 5274 bool hasAVX2 = Subtarget.hasAVX2(); 5275 uint16_t validDomains = 0; 5276 if (domain && lookup(MI->getOpcode(), domain)) 5277 validDomains = 0xe; 5278 else if (domain && lookupAVX2(MI->getOpcode(), domain)) 5279 validDomains = hasAVX2 ? 0xe : 0x6; 5280 return std::make_pair(domain, validDomains); 5281 } 5282 5283 void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const { 5284 assert(Domain>0 && Domain<4 && "Invalid execution domain"); 5285 uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3; 5286 assert(dom && "Not an SSE instruction"); 5287 const uint16_t *table = lookup(MI->getOpcode(), dom); 5288 if (!table) { // try the other table 5289 assert((Subtarget.hasAVX2() || Domain < 3) && 5290 "256-bit vector operations only available in AVX2"); 5291 table = lookupAVX2(MI->getOpcode(), dom); 5292 } 5293 assert(table && "Cannot change domain"); 5294 MI->setDesc(get(table[Domain-1])); 5295 } 5296 5297 /// getNoopForMachoTarget - Return the noop instruction to use for a noop. 5298 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const { 5299 NopInst.setOpcode(X86::NOOP); 5300 } 5301 5302 void X86InstrInfo::getUnconditionalBranch( 5303 MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const { 5304 Branch.setOpcode(X86::JMP_4); 5305 Branch.addOperand(MCOperand::CreateExpr(BranchTarget)); 5306 } 5307 5308 void X86InstrInfo::getTrap(MCInst &MI) const { 5309 MI.setOpcode(X86::TRAP); 5310 } 5311 5312 bool X86InstrInfo::isHighLatencyDef(int opc) const { 5313 switch (opc) { 5314 default: return false; 5315 case X86::DIVSDrm: 5316 case X86::DIVSDrm_Int: 5317 case X86::DIVSDrr: 5318 case X86::DIVSDrr_Int: 5319 case X86::DIVSSrm: 5320 case X86::DIVSSrm_Int: 5321 case X86::DIVSSrr: 5322 case X86::DIVSSrr_Int: 5323 case X86::SQRTPDm: 5324 case X86::SQRTPDr: 5325 case X86::SQRTPSm: 5326 case X86::SQRTPSr: 5327 case X86::SQRTSDm: 5328 case X86::SQRTSDm_Int: 5329 case X86::SQRTSDr: 5330 case X86::SQRTSDr_Int: 5331 case X86::SQRTSSm: 5332 case X86::SQRTSSm_Int: 5333 case X86::SQRTSSr: 5334 case X86::SQRTSSr_Int: 5335 // AVX instructions with high latency 5336 case X86::VDIVSDrm: 5337 case X86::VDIVSDrm_Int: 5338 case X86::VDIVSDrr: 5339 case X86::VDIVSDrr_Int: 5340 case X86::VDIVSSrm: 5341 case X86::VDIVSSrm_Int: 5342 case X86::VDIVSSrr: 5343 case X86::VDIVSSrr_Int: 5344 case X86::VSQRTPDm: 5345 case X86::VSQRTPDr: 5346 case X86::VSQRTPSm: 5347 case X86::VSQRTPSr: 5348 case X86::VSQRTSDm: 5349 case X86::VSQRTSDm_Int: 5350 case X86::VSQRTSDr: 5351 case X86::VSQRTSSm: 5352 case X86::VSQRTSSm_Int: 5353 case X86::VSQRTSSr: 5354 case X86::VSQRTPDZrm: 5355 case X86::VSQRTPDZrr: 5356 case X86::VSQRTPSZrm: 5357 case X86::VSQRTPSZrr: 5358 case X86::VSQRTSDZm: 5359 case X86::VSQRTSDZm_Int: 5360 case X86::VSQRTSDZr: 5361 case X86::VSQRTSSZm_Int: 5362 case X86::VSQRTSSZr: 5363 case X86::VSQRTSSZm: 5364 case X86::VDIVSDZrm: 5365 case X86::VDIVSDZrr: 5366 case X86::VDIVSSZrm: 5367 case X86::VDIVSSZrr: 5368 5369 case X86::VGATHERQPSZrm: 5370 case X86::VGATHERQPDZrm: 5371 case X86::VGATHERDPDZrm: 5372 case X86::VGATHERDPSZrm: 5373 case X86::VPGATHERQDZrm: 5374 case X86::VPGATHERQQZrm: 5375 case X86::VPGATHERDDZrm: 5376 case X86::VPGATHERDQZrm: 5377 case X86::VSCATTERQPDZmr: 5378 case X86::VSCATTERQPSZmr: 5379 case X86::VSCATTERDPDZmr: 5380 case X86::VSCATTERDPSZmr: 5381 case X86::VPSCATTERQDZmr: 5382 case X86::VPSCATTERQQZmr: 5383 case X86::VPSCATTERDDZmr: 5384 case X86::VPSCATTERDQZmr: 5385 return true; 5386 } 5387 } 5388 5389 bool X86InstrInfo:: 5390 hasHighOperandLatency(const InstrItineraryData *ItinData, 5391 const MachineRegisterInfo *MRI, 5392 const MachineInstr *DefMI, unsigned DefIdx, 5393 const MachineInstr *UseMI, unsigned UseIdx) const { 5394 return isHighLatencyDef(DefMI->getOpcode()); 5395 } 5396 5397 namespace { 5398 /// CGBR - Create Global Base Reg pass. This initializes the PIC 5399 /// global base register for x86-32. 5400 struct CGBR : public MachineFunctionPass { 5401 static char ID; 5402 CGBR() : MachineFunctionPass(ID) {} 5403 5404 bool runOnMachineFunction(MachineFunction &MF) override { 5405 const X86TargetMachine *TM = 5406 static_cast<const X86TargetMachine *>(&MF.getTarget()); 5407 5408 // Don't do anything if this is 64-bit as 64-bit PIC 5409 // uses RIP relative addressing. 5410 if (TM->getSubtarget<X86Subtarget>().is64Bit()) 5411 return false; 5412 5413 // Only emit a global base reg in PIC mode. 5414 if (TM->getRelocationModel() != Reloc::PIC_) 5415 return false; 5416 5417 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); 5418 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg(); 5419 5420 // If we didn't need a GlobalBaseReg, don't insert code. 5421 if (GlobalBaseReg == 0) 5422 return false; 5423 5424 // Insert the set of GlobalBaseReg into the first MBB of the function 5425 MachineBasicBlock &FirstMBB = MF.front(); 5426 MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 5427 DebugLoc DL = FirstMBB.findDebugLoc(MBBI); 5428 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 5429 const X86InstrInfo *TII = TM->getInstrInfo(); 5430 5431 unsigned PC; 5432 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) 5433 PC = RegInfo.createVirtualRegister(&X86::GR32RegClass); 5434 else 5435 PC = GlobalBaseReg; 5436 5437 // Operand of MovePCtoStack is completely ignored by asm printer. It's 5438 // only used in JIT code emission as displacement to pc. 5439 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0); 5440 5441 // If we're using vanilla 'GOT' PIC style, we should use relative addressing 5442 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external. 5443 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) { 5444 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register 5445 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg) 5446 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_", 5447 X86II::MO_GOT_ABSOLUTE_ADDRESS); 5448 } 5449 5450 return true; 5451 } 5452 5453 const char *getPassName() const override { 5454 return "X86 PIC Global Base Reg Initialization"; 5455 } 5456 5457 void getAnalysisUsage(AnalysisUsage &AU) const override { 5458 AU.setPreservesCFG(); 5459 MachineFunctionPass::getAnalysisUsage(AU); 5460 } 5461 }; 5462 } 5463 5464 char CGBR::ID = 0; 5465 FunctionPass* 5466 llvm::createX86GlobalBaseRegPass() { return new CGBR(); } 5467 5468 namespace { 5469 struct LDTLSCleanup : public MachineFunctionPass { 5470 static char ID; 5471 LDTLSCleanup() : MachineFunctionPass(ID) {} 5472 5473 bool runOnMachineFunction(MachineFunction &MF) override { 5474 X86MachineFunctionInfo* MFI = MF.getInfo<X86MachineFunctionInfo>(); 5475 if (MFI->getNumLocalDynamicTLSAccesses() < 2) { 5476 // No point folding accesses if there isn't at least two. 5477 return false; 5478 } 5479 5480 MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>(); 5481 return VisitNode(DT->getRootNode(), 0); 5482 } 5483 5484 // Visit the dominator subtree rooted at Node in pre-order. 5485 // If TLSBaseAddrReg is non-null, then use that to replace any 5486 // TLS_base_addr instructions. Otherwise, create the register 5487 // when the first such instruction is seen, and then use it 5488 // as we encounter more instructions. 5489 bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) { 5490 MachineBasicBlock *BB = Node->getBlock(); 5491 bool Changed = false; 5492 5493 // Traverse the current block. 5494 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; 5495 ++I) { 5496 switch (I->getOpcode()) { 5497 case X86::TLS_base_addr32: 5498 case X86::TLS_base_addr64: 5499 if (TLSBaseAddrReg) 5500 I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg); 5501 else 5502 I = SetRegister(I, &TLSBaseAddrReg); 5503 Changed = true; 5504 break; 5505 default: 5506 break; 5507 } 5508 } 5509 5510 // Visit the children of this block in the dominator tree. 5511 for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end(); 5512 I != E; ++I) { 5513 Changed |= VisitNode(*I, TLSBaseAddrReg); 5514 } 5515 5516 return Changed; 5517 } 5518 5519 // Replace the TLS_base_addr instruction I with a copy from 5520 // TLSBaseAddrReg, returning the new instruction. 5521 MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I, 5522 unsigned TLSBaseAddrReg) { 5523 MachineFunction *MF = I->getParent()->getParent(); 5524 const X86TargetMachine *TM = 5525 static_cast<const X86TargetMachine *>(&MF->getTarget()); 5526 const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit(); 5527 const X86InstrInfo *TII = TM->getInstrInfo(); 5528 5529 // Insert a Copy from TLSBaseAddrReg to RAX/EAX. 5530 MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(), 5531 TII->get(TargetOpcode::COPY), 5532 is64Bit ? X86::RAX : X86::EAX) 5533 .addReg(TLSBaseAddrReg); 5534 5535 // Erase the TLS_base_addr instruction. 5536 I->eraseFromParent(); 5537 5538 return Copy; 5539 } 5540 5541 // Create a virtal register in *TLSBaseAddrReg, and populate it by 5542 // inserting a copy instruction after I. Returns the new instruction. 5543 MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) { 5544 MachineFunction *MF = I->getParent()->getParent(); 5545 const X86TargetMachine *TM = 5546 static_cast<const X86TargetMachine *>(&MF->getTarget()); 5547 const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit(); 5548 const X86InstrInfo *TII = TM->getInstrInfo(); 5549 5550 // Create a virtual register for the TLS base address. 5551 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 5552 *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit 5553 ? &X86::GR64RegClass 5554 : &X86::GR32RegClass); 5555 5556 // Insert a copy from RAX/EAX to TLSBaseAddrReg. 5557 MachineInstr *Next = I->getNextNode(); 5558 MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(), 5559 TII->get(TargetOpcode::COPY), 5560 *TLSBaseAddrReg) 5561 .addReg(is64Bit ? X86::RAX : X86::EAX); 5562 5563 return Copy; 5564 } 5565 5566 const char *getPassName() const override { 5567 return "Local Dynamic TLS Access Clean-up"; 5568 } 5569 5570 void getAnalysisUsage(AnalysisUsage &AU) const override { 5571 AU.setPreservesCFG(); 5572 AU.addRequired<MachineDominatorTree>(); 5573 MachineFunctionPass::getAnalysisUsage(AU); 5574 } 5575 }; 5576 } 5577 5578 char LDTLSCleanup::ID = 0; 5579 FunctionPass* 5580 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); } 5581
