1 ; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s 2 ; Check that we generate absolute addressing mode instructions 3 ; with immediate value. 4 5 define i32 @f1(i32 %i) nounwind { 6 ; CHECK: memw(##786432){{ *}}={{ *}}r{{[0-9]+}} 7 entry: 8 store volatile i32 %i, i32* inttoptr (i32 786432 to i32*), align 262144 9 ret i32 %i 10 } 11 12 define i32* @f2(i32* nocapture %i) nounwind { 13 entry: 14 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(##786432) 15 %0 = load volatile i32* inttoptr (i32 786432 to i32*), align 262144 16 %1 = inttoptr i32 %0 to i32* 17 ret i32* %1 18 } 19
