1 ; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s 2 ; Check that we generate compare to general register. 3 4 define i32 @compare1(i32 %a) nounwind { 5 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}cmp.eq(r{{[0-9]+}},{{ *}}#120) 6 entry: 7 %cmp = icmp eq i32 %a, 120 8 %conv = zext i1 %cmp to i32 9 ret i32 %conv 10 } 11 12 define i32 @compare2(i32 %a) nounwind readnone { 13 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}!cmp.eq(r{{[0-9]+}},{{ *}}#120) 14 entry: 15 %cmp = icmp ne i32 %a, 120 16 %conv = zext i1 %cmp to i32 17 ret i32 %conv 18 } 19 20 define i32 @compare3(i32 %a, i32 %b) nounwind readnone { 21 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}cmp.eq(r{{[0-9]+}},{{ *}}r{{[0-9]+}}) 22 entry: 23 %cmp = icmp eq i32 %a, %b 24 %conv = zext i1 %cmp to i32 25 ret i32 %conv 26 } 27 28 define i32 @compare4(i32 %a, i32 %b) nounwind readnone { 29 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}!cmp.eq(r{{[0-9]+}},{{ *}}r{{[0-9]+}}) 30 entry: 31 %cmp = icmp ne i32 %a, %b 32 %conv = zext i1 %cmp to i32 33 ret i32 %conv 34 } 35
