1 ; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s 2 ; Check that we generate load instruction with (base + register offset << 0) 3 4 ; load word 5 6 define i32 @load_w(i32* nocapture %a, i32 %n) nounwind { 7 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}+r{{[0-9]+}}<<#0) 8 entry: 9 %tmp = shl i32 %n, 4 10 %scevgep9 = getelementptr i32* %a, i32 %tmp 11 %val = load i32* %scevgep9, align 4 12 ret i32 %val 13 } 14 15 ; load unsigned half word 16 17 define i16 @load_uh(i16* nocapture %a, i32 %n) nounwind { 18 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memuh(r{{[0-9]+}}+r{{[0-9]+}}<<#0) 19 entry: 20 %tmp = shl i32 %n, 4 21 %scevgep9 = getelementptr i16* %a, i32 %tmp 22 %val = load i16* %scevgep9, align 2 23 ret i16 %val 24 } 25 26 ; load signed half word 27 28 define i32 @load_h(i16* nocapture %a, i32 %n) nounwind { 29 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memh(r{{[0-9]+}}+r{{[0-9]+}}<<#0) 30 entry: 31 %tmp = shl i32 %n, 4 32 %scevgep9 = getelementptr i16* %a, i32 %tmp 33 %val = load i16* %scevgep9, align 2 34 %conv = sext i16 %val to i32 35 ret i32 %conv 36 } 37 38 ; load unsigned byte 39 40 define i8 @load_ub(i8* nocapture %a, i32 %n) nounwind { 41 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memub(r{{[0-9]+}}+r{{[0-9]+}}<<#0) 42 entry: 43 %tmp = shl i32 %n, 4 44 %scevgep9 = getelementptr i8* %a, i32 %tmp 45 %val = load i8* %scevgep9, align 1 46 ret i8 %val 47 } 48 49 ; load signed byte 50 51 define i32 @foo_2(i8* nocapture %a, i32 %n) nounwind { 52 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memb(r{{[0-9]+}}+r{{[0-9]+}}<<#0) 53 entry: 54 %tmp = shl i32 %n, 4 55 %scevgep9 = getelementptr i8* %a, i32 %tmp 56 %val = load i8* %scevgep9, align 1 57 %conv = sext i8 %val to i32 58 ret i32 %conv 59 } 60 61 ; load doubleword 62 63 define i64 @load_d(i64* nocapture %a, i32 %n) nounwind { 64 ; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}memd(r{{[0-9]+}}+r{{[0-9]+}}<<#0) 65 entry: 66 %tmp = shl i32 %n, 4 67 %scevgep9 = getelementptr i64* %a, i32 %tmp 68 %val = load i64* %scevgep9, align 8 69 ret i64 %val 70 } 71
