1 ; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s 2 ; Generate MemOps for V4 and above. 3 4 5 define void @f(i32* %p) nounwind { 6 entry: 7 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#40){{ *}}-={{ *}}#1 8 %p.addr = alloca i32*, align 4 9 store i32* %p, i32** %p.addr, align 4 10 %0 = load i32** %p.addr, align 4 11 %add.ptr = getelementptr inbounds i32* %0, i32 10 12 %1 = load i32* %add.ptr, align 4 13 %sub = sub nsw i32 %1, 1 14 store i32 %sub, i32* %add.ptr, align 4 15 ret void 16 } 17 18 define void @g(i32* %p, i32 %i) nounwind { 19 entry: 20 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#40){{ *}}-={{ *}}#1 21 %p.addr = alloca i32*, align 4 22 %i.addr = alloca i32, align 4 23 store i32* %p, i32** %p.addr, align 4 24 store i32 %i, i32* %i.addr, align 4 25 %0 = load i32** %p.addr, align 4 26 %1 = load i32* %i.addr, align 4 27 %add.ptr = getelementptr inbounds i32* %0, i32 %1 28 %add.ptr1 = getelementptr inbounds i32* %add.ptr, i32 10 29 %2 = load i32* %add.ptr1, align 4 30 %sub = sub nsw i32 %2, 1 31 store i32 %sub, i32* %add.ptr1, align 4 32 ret void 33 } 34
