1 ; RUN: llc -march=mipsel -mattr=+dspr2 < %s | FileCheck %s 2 3 define i64 @test__builtin_mips_dpa_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone { 4 entry: 5 ; CHECK: dpa.w.ph 6 7 %1 = bitcast i32 %a1.coerce to <2 x i16> 8 %2 = bitcast i32 %a2.coerce to <2 x i16> 9 %3 = tail call i64 @llvm.mips.dpa.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2) 10 ret i64 %3 11 } 12 13 declare i64 @llvm.mips.dpa.w.ph(i64, <2 x i16>, <2 x i16>) nounwind readnone 14 15 define i64 @test__builtin_mips_dps_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone { 16 entry: 17 ; CHECK: dps.w.ph 18 19 %1 = bitcast i32 %a1.coerce to <2 x i16> 20 %2 = bitcast i32 %a2.coerce to <2 x i16> 21 %3 = tail call i64 @llvm.mips.dps.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2) 22 ret i64 %3 23 } 24 25 declare i64 @llvm.mips.dps.w.ph(i64, <2 x i16>, <2 x i16>) nounwind readnone 26 27 define i64 @test__builtin_mips_mulsa_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone { 28 entry: 29 ; CHECK: mulsa.w.ph 30 31 %1 = bitcast i32 %a1.coerce to <2 x i16> 32 %2 = bitcast i32 %a2.coerce to <2 x i16> 33 %3 = tail call i64 @llvm.mips.mulsa.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2) 34 ret i64 %3 35 } 36 37 declare i64 @llvm.mips.mulsa.w.ph(i64, <2 x i16>, <2 x i16>) nounwind readnone 38 39 define i64 @test__builtin_mips_dpax_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone { 40 entry: 41 ; CHECK: dpax.w.ph 42 43 %1 = bitcast i32 %a1.coerce to <2 x i16> 44 %2 = bitcast i32 %a2.coerce to <2 x i16> 45 %3 = tail call i64 @llvm.mips.dpax.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2) 46 ret i64 %3 47 } 48 49 declare i64 @llvm.mips.dpax.w.ph(i64, <2 x i16>, <2 x i16>) nounwind readnone 50 51 define i64 @test__builtin_mips_dpsx_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone { 52 entry: 53 ; CHECK: dpsx.w.ph 54 55 %1 = bitcast i32 %a1.coerce to <2 x i16> 56 %2 = bitcast i32 %a2.coerce to <2 x i16> 57 %3 = tail call i64 @llvm.mips.dpsx.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2) 58 ret i64 %3 59 } 60 61 declare i64 @llvm.mips.dpsx.w.ph(i64, <2 x i16>, <2 x i16>) nounwind readnone 62 63 define i64 @test__builtin_mips_dpaqx_s_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind { 64 entry: 65 ; CHECK: dpaqx_s.w.ph 66 67 %1 = bitcast i32 %a1.coerce to <2 x i16> 68 %2 = bitcast i32 %a2.coerce to <2 x i16> 69 %3 = tail call i64 @llvm.mips.dpaqx.s.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2) 70 ret i64 %3 71 } 72 73 declare i64 @llvm.mips.dpaqx.s.w.ph(i64, <2 x i16>, <2 x i16>) nounwind 74 75 define i64 @test__builtin_mips_dpaqx_sa_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind { 76 entry: 77 ; CHECK: dpaqx_sa.w.ph 78 79 %1 = bitcast i32 %a1.coerce to <2 x i16> 80 %2 = bitcast i32 %a2.coerce to <2 x i16> 81 %3 = tail call i64 @llvm.mips.dpaqx.sa.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2) 82 ret i64 %3 83 } 84 85 declare i64 @llvm.mips.dpaqx.sa.w.ph(i64, <2 x i16>, <2 x i16>) nounwind 86 87 define i64 @test__builtin_mips_dpsqx_s_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind { 88 entry: 89 ; CHECK: dpsqx_s.w.ph 90 91 %1 = bitcast i32 %a1.coerce to <2 x i16> 92 %2 = bitcast i32 %a2.coerce to <2 x i16> 93 %3 = tail call i64 @llvm.mips.dpsqx.s.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2) 94 ret i64 %3 95 } 96 97 declare i64 @llvm.mips.dpsqx.s.w.ph(i64, <2 x i16>, <2 x i16>) nounwind 98 99 define i64 @test__builtin_mips_dpsqx_sa_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind { 100 entry: 101 ; CHECK: dpsqx_sa.w.ph 102 103 %1 = bitcast i32 %a1.coerce to <2 x i16> 104 %2 = bitcast i32 %a2.coerce to <2 x i16> 105 %3 = tail call i64 @llvm.mips.dpsqx.sa.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2) 106 ret i64 %3 107 } 108 109 declare i64 @llvm.mips.dpsqx.sa.w.ph(i64, <2 x i16>, <2 x i16>) nounwind 110 111 define { i32 } @test__builtin_mips_addu_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind { 112 entry: 113 ; CHECK: addu.ph 114 115 %0 = bitcast i32 %a0.coerce to <2 x i16> 116 %1 = bitcast i32 %a1.coerce to <2 x i16> 117 %2 = tail call <2 x i16> @llvm.mips.addu.ph(<2 x i16> %0, <2 x i16> %1) 118 %3 = bitcast <2 x i16> %2 to i32 119 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0 120 ret { i32 } %.fca.0.insert 121 } 122 123 declare <2 x i16> @llvm.mips.addu.ph(<2 x i16>, <2 x i16>) nounwind 124 125 define { i32 } @test__builtin_mips_addu_s_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind { 126 entry: 127 ; CHECK: addu_s.ph 128 129 %0 = bitcast i32 %a0.coerce to <2 x i16> 130 %1 = bitcast i32 %a1.coerce to <2 x i16> 131 %2 = tail call <2 x i16> @llvm.mips.addu.s.ph(<2 x i16> %0, <2 x i16> %1) 132 %3 = bitcast <2 x i16> %2 to i32 133 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0 134 ret { i32 } %.fca.0.insert 135 } 136 137 declare <2 x i16> @llvm.mips.addu.s.ph(<2 x i16>, <2 x i16>) nounwind 138 139 define { i32 } @test__builtin_mips_mulq_s_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind { 140 entry: 141 ; CHECK: mulq_s.ph 142 143 %0 = bitcast i32 %a0.coerce to <2 x i16> 144 %1 = bitcast i32 %a1.coerce to <2 x i16> 145 %2 = tail call <2 x i16> @llvm.mips.mulq.s.ph(<2 x i16> %0, <2 x i16> %1) 146 %3 = bitcast <2 x i16> %2 to i32 147 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0 148 ret { i32 } %.fca.0.insert 149 } 150 151 declare <2 x i16> @llvm.mips.mulq.s.ph(<2 x i16>, <2 x i16>) nounwind 152 153 define { i32 } @test__builtin_mips_subu_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind { 154 entry: 155 ; CHECK: subu.ph 156 157 %0 = bitcast i32 %a0.coerce to <2 x i16> 158 %1 = bitcast i32 %a1.coerce to <2 x i16> 159 %2 = tail call <2 x i16> @llvm.mips.subu.ph(<2 x i16> %0, <2 x i16> %1) 160 %3 = bitcast <2 x i16> %2 to i32 161 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0 162 ret { i32 } %.fca.0.insert 163 } 164 165 declare <2 x i16> @llvm.mips.subu.ph(<2 x i16>, <2 x i16>) nounwind 166 167 define { i32 } @test__builtin_mips_subu_s_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind { 168 entry: 169 ; CHECK: subu_s.ph 170 171 %0 = bitcast i32 %a0.coerce to <2 x i16> 172 %1 = bitcast i32 %a1.coerce to <2 x i16> 173 %2 = tail call <2 x i16> @llvm.mips.subu.s.ph(<2 x i16> %0, <2 x i16> %1) 174 %3 = bitcast <2 x i16> %2 to i32 175 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0 176 ret { i32 } %.fca.0.insert 177 } 178 179 declare <2 x i16> @llvm.mips.subu.s.ph(<2 x i16>, <2 x i16>) nounwind 180 181 define i32 @test__builtin_mips_cmpgdu_eq_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind { 182 entry: 183 ; CHECK: cmpgdu.eq.qb 184 185 %0 = bitcast i32 %a0.coerce to <4 x i8> 186 %1 = bitcast i32 %a1.coerce to <4 x i8> 187 %2 = tail call i32 @llvm.mips.cmpgdu.eq.qb(<4 x i8> %0, <4 x i8> %1) 188 ret i32 %2 189 } 190 191 declare i32 @llvm.mips.cmpgdu.eq.qb(<4 x i8>, <4 x i8>) nounwind 192 193 define i32 @test__builtin_mips_cmpgdu_lt_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind { 194 entry: 195 ; CHECK: cmpgdu.lt.qb 196 197 %0 = bitcast i32 %a0.coerce to <4 x i8> 198 %1 = bitcast i32 %a1.coerce to <4 x i8> 199 %2 = tail call i32 @llvm.mips.cmpgdu.lt.qb(<4 x i8> %0, <4 x i8> %1) 200 ret i32 %2 201 } 202 203 declare i32 @llvm.mips.cmpgdu.lt.qb(<4 x i8>, <4 x i8>) nounwind 204 205 define i32 @test__builtin_mips_cmpgdu_le_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind { 206 entry: 207 ; CHECK: cmpgdu.le.qb 208 209 %0 = bitcast i32 %a0.coerce to <4 x i8> 210 %1 = bitcast i32 %a1.coerce to <4 x i8> 211 %2 = tail call i32 @llvm.mips.cmpgdu.le.qb(<4 x i8> %0, <4 x i8> %1) 212 ret i32 %2 213 } 214 215 declare i32 @llvm.mips.cmpgdu.le.qb(<4 x i8>, <4 x i8>) nounwind 216 217 define { i32 } @test__builtin_mips_precr_qb_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind { 218 entry: 219 ; CHECK: precr.qb.ph 220 221 %0 = bitcast i32 %a0.coerce to <2 x i16> 222 %1 = bitcast i32 %a1.coerce to <2 x i16> 223 %2 = tail call <4 x i8> @llvm.mips.precr.qb.ph(<2 x i16> %0, <2 x i16> %1) 224 %3 = bitcast <4 x i8> %2 to i32 225 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0 226 ret { i32 } %.fca.0.insert 227 } 228 229 declare <4 x i8> @llvm.mips.precr.qb.ph(<2 x i16>, <2 x i16>) nounwind 230 231 define { i32 } @test__builtin_mips_precr_sra_ph_w1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone { 232 entry: 233 ; CHECK: precr_sra.ph.w 234 235 %0 = tail call <2 x i16> @llvm.mips.precr.sra.ph.w(i32 %a0, i32 %a1, i32 15) 236 %1 = bitcast <2 x i16> %0 to i32 237 %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0 238 ret { i32 } %.fca.0.insert 239 } 240 241 declare <2 x i16> @llvm.mips.precr.sra.ph.w(i32, i32, i32) nounwind readnone 242 243 define { i32 } @test__builtin_mips_precr_sra_r_ph_w1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone { 244 entry: 245 ; CHECK: precr_sra_r.ph.w 246 247 %0 = tail call <2 x i16> @llvm.mips.precr.sra.r.ph.w(i32 %a0, i32 %a1, i32 15) 248 %1 = bitcast <2 x i16> %0 to i32 249 %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0 250 ret { i32 } %.fca.0.insert 251 } 252 253 declare <2 x i16> @llvm.mips.precr.sra.r.ph.w(i32, i32, i32) nounwind readnone 254 255 define { i32 } @test__builtin_mips_shra_qb1(i32 %i0, i32 %a0.coerce) nounwind readnone { 256 entry: 257 ; CHECK: shra.qb 258 259 %0 = bitcast i32 %a0.coerce to <4 x i8> 260 %1 = tail call <4 x i8> @llvm.mips.shra.qb(<4 x i8> %0, i32 3) 261 %2 = bitcast <4 x i8> %1 to i32 262 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 263 ret { i32 } %.fca.0.insert 264 } 265 266 declare <4 x i8> @llvm.mips.shra.qb(<4 x i8>, i32) nounwind readnone 267 268 define { i32 } @test__builtin_mips_shra_r_qb1(i32 %i0, i32 %a0.coerce) nounwind readnone { 269 entry: 270 ; CHECK: shra_r.qb 271 272 %0 = bitcast i32 %a0.coerce to <4 x i8> 273 %1 = tail call <4 x i8> @llvm.mips.shra.r.qb(<4 x i8> %0, i32 3) 274 %2 = bitcast <4 x i8> %1 to i32 275 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 276 ret { i32 } %.fca.0.insert 277 } 278 279 declare <4 x i8> @llvm.mips.shra.r.qb(<4 x i8>, i32) nounwind readnone 280 281 define { i32 } @test__builtin_mips_shra_qb2(i32 %i0, i32 %a0.coerce, i32 %a1) nounwind readnone { 282 entry: 283 ; CHECK: shrav.qb 284 285 %0 = bitcast i32 %a0.coerce to <4 x i8> 286 %1 = tail call <4 x i8> @llvm.mips.shra.qb(<4 x i8> %0, i32 %a1) 287 %2 = bitcast <4 x i8> %1 to i32 288 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 289 ret { i32 } %.fca.0.insert 290 } 291 292 define { i32 } @test__builtin_mips_shra_r_qb2(i32 %i0, i32 %a0.coerce, i32 %a1) nounwind readnone { 293 entry: 294 ; CHECK: shrav_r.qb 295 296 %0 = bitcast i32 %a0.coerce to <4 x i8> 297 %1 = tail call <4 x i8> @llvm.mips.shra.r.qb(<4 x i8> %0, i32 %a1) 298 %2 = bitcast <4 x i8> %1 to i32 299 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 300 ret { i32 } %.fca.0.insert 301 } 302 303 define { i32 } @test__builtin_mips_shrl_ph1(i32 %i0, i32 %a0.coerce) nounwind readnone { 304 entry: 305 ; CHECK: shrl.ph 306 307 %0 = bitcast i32 %a0.coerce to <2 x i16> 308 %1 = tail call <2 x i16> @llvm.mips.shrl.ph(<2 x i16> %0, i32 7) 309 %2 = bitcast <2 x i16> %1 to i32 310 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 311 ret { i32 } %.fca.0.insert 312 } 313 314 declare <2 x i16> @llvm.mips.shrl.ph(<2 x i16>, i32) nounwind readnone 315 316 define { i32 } @test__builtin_mips_shrl_ph2(i32 %i0, i32 %a0.coerce, i32 %a1) nounwind readnone { 317 entry: 318 ; CHECK: shrlv.ph 319 320 %0 = bitcast i32 %a0.coerce to <2 x i16> 321 %1 = tail call <2 x i16> @llvm.mips.shrl.ph(<2 x i16> %0, i32 %a1) 322 %2 = bitcast <2 x i16> %1 to i32 323 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 324 ret { i32 } %.fca.0.insert 325 } 326 327 define { i32 } @test__builtin_mips_absq_s_qb1(i32 %i0, i32 %a0.coerce) nounwind { 328 entry: 329 ; CHECK: absq_s.qb 330 331 %0 = bitcast i32 %a0.coerce to <4 x i8> 332 %1 = tail call <4 x i8> @llvm.mips.absq.s.qb(<4 x i8> %0) 333 %2 = bitcast <4 x i8> %1 to i32 334 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 335 ret { i32 } %.fca.0.insert 336 } 337 338 declare <4 x i8> @llvm.mips.absq.s.qb(<4 x i8>) nounwind 339 340 define { i32 } @test__builtin_mips_mul_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind { 341 entry: 342 ; CHECK: mul.ph 343 344 %0 = bitcast i32 %a0.coerce to <2 x i16> 345 %1 = bitcast i32 %a1.coerce to <2 x i16> 346 %2 = tail call <2 x i16> @llvm.mips.mul.ph(<2 x i16> %0, <2 x i16> %1) 347 %3 = bitcast <2 x i16> %2 to i32 348 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0 349 ret { i32 } %.fca.0.insert 350 } 351 352 declare <2 x i16> @llvm.mips.mul.ph(<2 x i16>, <2 x i16>) nounwind 353 354 define { i32 } @test__builtin_mips_mul_s_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind { 355 entry: 356 ; CHECK: mul_s.ph 357 358 %0 = bitcast i32 %a0.coerce to <2 x i16> 359 %1 = bitcast i32 %a1.coerce to <2 x i16> 360 %2 = tail call <2 x i16> @llvm.mips.mul.s.ph(<2 x i16> %0, <2 x i16> %1) 361 %3 = bitcast <2 x i16> %2 to i32 362 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0 363 ret { i32 } %.fca.0.insert 364 } 365 366 declare <2 x i16> @llvm.mips.mul.s.ph(<2 x i16>, <2 x i16>) nounwind 367 368 define i32 @test__builtin_mips_mulq_rs_w1(i32 %i0, i32 %a0, i32 %a1) nounwind { 369 entry: 370 ; CHECK: mulq_rs.w 371 372 %0 = tail call i32 @llvm.mips.mulq.rs.w(i32 %a0, i32 %a1) 373 ret i32 %0 374 } 375 376 declare i32 @llvm.mips.mulq.rs.w(i32, i32) nounwind 377 378 define i32 @test__builtin_mips_mulq_s_w1(i32 %i0, i32 %a0, i32 %a1) nounwind { 379 entry: 380 ; CHECK: mulq_s.w 381 382 %0 = tail call i32 @llvm.mips.mulq.s.w(i32 %a0, i32 %a1) 383 ret i32 %0 384 } 385 386 declare i32 @llvm.mips.mulq.s.w(i32, i32) nounwind 387 388 define { i32 } @test__builtin_mips_adduh_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readnone { 389 entry: 390 ; CHECK: adduh.qb 391 392 %0 = bitcast i32 %a0.coerce to <4 x i8> 393 %1 = bitcast i32 %a1.coerce to <4 x i8> 394 %2 = tail call <4 x i8> @llvm.mips.adduh.qb(<4 x i8> %0, <4 x i8> %1) 395 %3 = bitcast <4 x i8> %2 to i32 396 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0 397 ret { i32 } %.fca.0.insert 398 } 399 400 declare <4 x i8> @llvm.mips.adduh.qb(<4 x i8>, <4 x i8>) nounwind readnone 401 402 define { i32 } @test__builtin_mips_adduh_r_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readnone { 403 entry: 404 ; CHECK: adduh_r.qb 405 406 %0 = bitcast i32 %a0.coerce to <4 x i8> 407 %1 = bitcast i32 %a1.coerce to <4 x i8> 408 %2 = tail call <4 x i8> @llvm.mips.adduh.r.qb(<4 x i8> %0, <4 x i8> %1) 409 %3 = bitcast <4 x i8> %2 to i32 410 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0 411 ret { i32 } %.fca.0.insert 412 } 413 414 declare <4 x i8> @llvm.mips.adduh.r.qb(<4 x i8>, <4 x i8>) nounwind readnone 415 416 define { i32 } @test__builtin_mips_subuh_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readnone { 417 entry: 418 ; CHECK: subuh.qb 419 420 %0 = bitcast i32 %a0.coerce to <4 x i8> 421 %1 = bitcast i32 %a1.coerce to <4 x i8> 422 %2 = tail call <4 x i8> @llvm.mips.subuh.qb(<4 x i8> %0, <4 x i8> %1) 423 %3 = bitcast <4 x i8> %2 to i32 424 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0 425 ret { i32 } %.fca.0.insert 426 } 427 428 declare <4 x i8> @llvm.mips.subuh.qb(<4 x i8>, <4 x i8>) nounwind readnone 429 430 define { i32 } @test__builtin_mips_subuh_r_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readnone { 431 entry: 432 ; CHECK: subuh_r.qb 433 434 %0 = bitcast i32 %a0.coerce to <4 x i8> 435 %1 = bitcast i32 %a1.coerce to <4 x i8> 436 %2 = tail call <4 x i8> @llvm.mips.subuh.r.qb(<4 x i8> %0, <4 x i8> %1) 437 %3 = bitcast <4 x i8> %2 to i32 438 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0 439 ret { i32 } %.fca.0.insert 440 } 441 442 declare <4 x i8> @llvm.mips.subuh.r.qb(<4 x i8>, <4 x i8>) nounwind readnone 443 444 define { i32 } @test__builtin_mips_addqh_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readnone { 445 entry: 446 ; CHECK: addqh.ph 447 448 %0 = bitcast i32 %a0.coerce to <2 x i16> 449 %1 = bitcast i32 %a1.coerce to <2 x i16> 450 %2 = tail call <2 x i16> @llvm.mips.addqh.ph(<2 x i16> %0, <2 x i16> %1) 451 %3 = bitcast <2 x i16> %2 to i32 452 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0 453 ret { i32 } %.fca.0.insert 454 } 455 456 declare <2 x i16> @llvm.mips.addqh.ph(<2 x i16>, <2 x i16>) nounwind readnone 457 458 define { i32 } @test__builtin_mips_addqh_r_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readnone { 459 entry: 460 ; CHECK: addqh_r.ph 461 462 %0 = bitcast i32 %a0.coerce to <2 x i16> 463 %1 = bitcast i32 %a1.coerce to <2 x i16> 464 %2 = tail call <2 x i16> @llvm.mips.addqh.r.ph(<2 x i16> %0, <2 x i16> %1) 465 %3 = bitcast <2 x i16> %2 to i32 466 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0 467 ret { i32 } %.fca.0.insert 468 } 469 470 declare <2 x i16> @llvm.mips.addqh.r.ph(<2 x i16>, <2 x i16>) nounwind readnone 471 472 define i32 @test__builtin_mips_addqh_w1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone { 473 entry: 474 ; CHECK: addqh.w 475 476 %0 = tail call i32 @llvm.mips.addqh.w(i32 %a0, i32 %a1) 477 ret i32 %0 478 } 479 480 declare i32 @llvm.mips.addqh.w(i32, i32) nounwind readnone 481 482 define i32 @test__builtin_mips_addqh_r_w1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone { 483 entry: 484 ; CHECK: addqh_r.w 485 486 %0 = tail call i32 @llvm.mips.addqh.r.w(i32 %a0, i32 %a1) 487 ret i32 %0 488 } 489 490 declare i32 @llvm.mips.addqh.r.w(i32, i32) nounwind readnone 491 492 define { i32 } @test__builtin_mips_subqh_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readnone { 493 entry: 494 ; CHECK: subqh.ph 495 496 %0 = bitcast i32 %a0.coerce to <2 x i16> 497 %1 = bitcast i32 %a1.coerce to <2 x i16> 498 %2 = tail call <2 x i16> @llvm.mips.subqh.ph(<2 x i16> %0, <2 x i16> %1) 499 %3 = bitcast <2 x i16> %2 to i32 500 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0 501 ret { i32 } %.fca.0.insert 502 } 503 504 declare <2 x i16> @llvm.mips.subqh.ph(<2 x i16>, <2 x i16>) nounwind readnone 505 506 define { i32 } @test__builtin_mips_subqh_r_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readnone { 507 entry: 508 ; CHECK: subqh_r.ph 509 510 %0 = bitcast i32 %a0.coerce to <2 x i16> 511 %1 = bitcast i32 %a1.coerce to <2 x i16> 512 %2 = tail call <2 x i16> @llvm.mips.subqh.r.ph(<2 x i16> %0, <2 x i16> %1) 513 %3 = bitcast <2 x i16> %2 to i32 514 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0 515 ret { i32 } %.fca.0.insert 516 } 517 518 declare <2 x i16> @llvm.mips.subqh.r.ph(<2 x i16>, <2 x i16>) nounwind readnone 519 520 define i32 @test__builtin_mips_subqh_w1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone { 521 entry: 522 ; CHECK: subqh.w 523 524 %0 = tail call i32 @llvm.mips.subqh.w(i32 %a0, i32 %a1) 525 ret i32 %0 526 } 527 528 declare i32 @llvm.mips.subqh.w(i32, i32) nounwind readnone 529 530 define i32 @test__builtin_mips_subqh_r_w1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone { 531 entry: 532 ; CHECK: subqh_r.w 533 534 %0 = tail call i32 @llvm.mips.subqh.r.w(i32 %a0, i32 %a1) 535 ret i32 %0 536 } 537 538 declare i32 @llvm.mips.subqh.r.w(i32, i32) nounwind readnone 539 540 define i32 @test__builtin_mips_append1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone { 541 entry: 542 ; CHECK: append ${{[0-9]+}} 543 544 %0 = tail call i32 @llvm.mips.append(i32 %a0, i32 %a1, i32 15) 545 ret i32 %0 546 } 547 548 declare i32 @llvm.mips.append(i32, i32, i32) nounwind readnone 549 550 define i32 @test__builtin_mips_balign1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone { 551 entry: 552 ; CHECK: balign ${{[0-9]+}} 553 554 %0 = tail call i32 @llvm.mips.balign(i32 %a0, i32 %a1, i32 1) 555 ret i32 %0 556 } 557 558 declare i32 @llvm.mips.balign(i32, i32, i32) nounwind readnone 559 560 define i32 @test__builtin_mips_prepend1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone { 561 entry: 562 ; CHECK: prepend ${{[0-9]+}} 563 564 %0 = tail call i32 @llvm.mips.prepend(i32 %a0, i32 %a1, i32 15) 565 ret i32 %0 566 } 567 568 declare i32 @llvm.mips.prepend(i32, i32, i32) nounwind readnone 569
