1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK --check-prefix=FUNC %s 2 ; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK --check-prefix=FUNC %s 3 4 ;FUNC-LABEL: @test1: 5 ;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 6 7 ;SI-CHECK: V_ADD_I32_e32 [[REG:v[0-9]+]], {{v[0-9]+, v[0-9]+}} 8 ;SI-CHECK-NOT: [[REG]] 9 ;SI-CHECK: BUFFER_STORE_DWORD [[REG]], 10 define void @test1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { 11 %b_ptr = getelementptr i32 addrspace(1)* %in, i32 1 12 %a = load i32 addrspace(1)* %in 13 %b = load i32 addrspace(1)* %b_ptr 14 %result = add i32 %a, %b 15 store i32 %result, i32 addrspace(1)* %out 16 ret void 17 } 18 19 ;FUNC-LABEL: @test2: 20 ;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 21 ;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 22 23 ;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 24 ;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 25 26 define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { 27 %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1 28 %a = load <2 x i32> addrspace(1)* %in 29 %b = load <2 x i32> addrspace(1)* %b_ptr 30 %result = add <2 x i32> %a, %b 31 store <2 x i32> %result, <2 x i32> addrspace(1)* %out 32 ret void 33 } 34 35 ;FUNC-LABEL: @test4: 36 ;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 37 ;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 38 ;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 39 ;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 40 41 ;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 42 ;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 43 ;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 44 ;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 45 46 define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { 47 %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 48 %a = load <4 x i32> addrspace(1)* %in 49 %b = load <4 x i32> addrspace(1)* %b_ptr 50 %result = add <4 x i32> %a, %b 51 store <4 x i32> %result, <4 x i32> addrspace(1)* %out 52 ret void 53 } 54 55 ; FUNC-LABEL: @test8 56 ; EG-CHECK: ADD_INT 57 ; EG-CHECK: ADD_INT 58 ; EG-CHECK: ADD_INT 59 ; EG-CHECK: ADD_INT 60 ; EG-CHECK: ADD_INT 61 ; EG-CHECK: ADD_INT 62 ; EG-CHECK: ADD_INT 63 ; EG-CHECK: ADD_INT 64 ; SI-CHECK: S_ADD_I32 65 ; SI-CHECK: S_ADD_I32 66 ; SI-CHECK: S_ADD_I32 67 ; SI-CHECK: S_ADD_I32 68 ; SI-CHECK: S_ADD_I32 69 ; SI-CHECK: S_ADD_I32 70 ; SI-CHECK: S_ADD_I32 71 ; SI-CHECK: S_ADD_I32 72 define void @test8(<8 x i32> addrspace(1)* %out, <8 x i32> %a, <8 x i32> %b) { 73 entry: 74 %0 = add <8 x i32> %a, %b 75 store <8 x i32> %0, <8 x i32> addrspace(1)* %out 76 ret void 77 } 78 79 ; FUNC-LABEL: @test16 80 ; EG-CHECK: ADD_INT 81 ; EG-CHECK: ADD_INT 82 ; EG-CHECK: ADD_INT 83 ; EG-CHECK: ADD_INT 84 ; EG-CHECK: ADD_INT 85 ; EG-CHECK: ADD_INT 86 ; EG-CHECK: ADD_INT 87 ; EG-CHECK: ADD_INT 88 ; EG-CHECK: ADD_INT 89 ; EG-CHECK: ADD_INT 90 ; EG-CHECK: ADD_INT 91 ; EG-CHECK: ADD_INT 92 ; EG-CHECK: ADD_INT 93 ; EG-CHECK: ADD_INT 94 ; EG-CHECK: ADD_INT 95 ; EG-CHECK: ADD_INT 96 ; SI-CHECK: S_ADD_I32 97 ; SI-CHECK: S_ADD_I32 98 ; SI-CHECK: S_ADD_I32 99 ; SI-CHECK: S_ADD_I32 100 ; SI-CHECK: S_ADD_I32 101 ; SI-CHECK: S_ADD_I32 102 ; SI-CHECK: S_ADD_I32 103 ; SI-CHECK: S_ADD_I32 104 ; SI-CHECK: S_ADD_I32 105 ; SI-CHECK: S_ADD_I32 106 ; SI-CHECK: S_ADD_I32 107 ; SI-CHECK: S_ADD_I32 108 ; SI-CHECK: S_ADD_I32 109 ; SI-CHECK: S_ADD_I32 110 ; SI-CHECK: S_ADD_I32 111 ; SI-CHECK: S_ADD_I32 112 define void @test16(<16 x i32> addrspace(1)* %out, <16 x i32> %a, <16 x i32> %b) { 113 entry: 114 %0 = add <16 x i32> %a, %b 115 store <16 x i32> %0, <16 x i32> addrspace(1)* %out 116 ret void 117 } 118 119 ; FUNC-LABEL: @add64 120 ; SI-CHECK: S_ADD_I32 121 ; SI-CHECK: S_ADDC_U32 122 define void @add64(i64 addrspace(1)* %out, i64 %a, i64 %b) { 123 entry: 124 %0 = add i64 %a, %b 125 store i64 %0, i64 addrspace(1)* %out 126 ret void 127 } 128 129 ; The V_ADDC_U32 and V_ADD_I32 instruction can't read SGPRs, because they 130 ; use VCC. The test is designed so that %a will be stored in an SGPR and 131 ; %0 will be stored in a VGPR, so the comiler will be forced to copy %a 132 ; to a VGPR before doing the add. 133 134 ; FUNC-LABEL: @add64_sgpr_vgpr 135 ; SI-CHECK-NOT: V_ADDC_U32_e32 s 136 define void @add64_sgpr_vgpr(i64 addrspace(1)* %out, i64 %a, i64 addrspace(1)* %in) { 137 entry: 138 %0 = load i64 addrspace(1)* %in 139 %1 = add i64 %a, %0 140 store i64 %1, i64 addrspace(1)* %out 141 ret void 142 } 143 144 ; Test i64 add inside a branch. We don't allow SALU instructions inside of 145 ; branches. 146 ; FIXME: We are being conservative here. We could allow this in some cases. 147 ; FUNC-LABEL: @add64_in_branch 148 ; SI-CHECK-NOT: S_ADD_I32 149 ; SI-CHECK-NOT: S_ADDC_U32 150 define void @add64_in_branch(i64 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %a, i64 %b, i64 %c) { 151 entry: 152 %0 = icmp eq i64 %a, 0 153 br i1 %0, label %if, label %else 154 155 if: 156 %1 = load i64 addrspace(1)* %in 157 br label %endif 158 159 else: 160 %2 = add i64 %a, %b 161 br label %endif 162 163 endif: 164 %3 = phi i64 [%1, %if], [%2, %else] 165 store i64 %3, i64 addrspace(1)* %out 166 ret void 167 } 168
