1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK 2 ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK 3 4 ; R600-CHECK: @fmul_f32 5 ; R600-CHECK: MUL_IEEE {{\** *}}{{T[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].W 6 ; SI-CHECK: @fmul_f32 7 ; SI-CHECK: V_MUL_F32 8 define void @fmul_f32(float addrspace(1)* %out, float %a, float %b) { 9 entry: 10 %0 = fmul float %a, %b 11 store float %0, float addrspace(1)* %out 12 ret void 13 } 14 15 declare float @llvm.R600.load.input(i32) readnone 16 17 declare void @llvm.AMDGPU.store.output(float, i32) 18 19 ; R600-CHECK: @fmul_v2f32 20 ; R600-CHECK: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}} 21 ; R600-CHECK: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}} 22 ; SI-CHECK: @fmul_v2f32 23 ; SI-CHECK: V_MUL_F32 24 ; SI-CHECK: V_MUL_F32 25 define void @fmul_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) { 26 entry: 27 %0 = fmul <2 x float> %a, %b 28 store <2 x float> %0, <2 x float> addrspace(1)* %out 29 ret void 30 } 31 32 ; R600-CHECK: @fmul_v4f32 33 ; R600-CHECK: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 34 ; R600-CHECK: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 35 ; R600-CHECK: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 36 ; R600-CHECK: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 37 ; SI-CHECK: @fmul_v4f32 38 ; SI-CHECK: V_MUL_F32 39 ; SI-CHECK: V_MUL_F32 40 ; SI-CHECK: V_MUL_F32 41 ; SI-CHECK: V_MUL_F32 42 define void @fmul_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { 43 %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1 44 %a = load <4 x float> addrspace(1) * %in 45 %b = load <4 x float> addrspace(1) * %b_ptr 46 %result = fmul <4 x float> %a, %b 47 store <4 x float> %result, <4 x float> addrspace(1)* %out 48 ret void 49 } 50
