1 ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s 2 3 declare float @llvm.AMDGPU.div.fixup.f32(float, float, float) nounwind readnone 4 declare double @llvm.AMDGPU.div.fixup.f64(double, double, double) nounwind readnone 5 6 ; SI-LABEL: @test_div_fixup_f32: 7 ; SI-DAG: S_LOAD_DWORD [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb 8 ; SI-DAG: S_LOAD_DWORD [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd 9 ; SI-DAG: V_MOV_B32_e32 [[VC:v[0-9]+]], [[SC]] 10 ; SI-DAG: S_LOAD_DWORD [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc 11 ; SI: V_MOV_B32_e32 [[VB:v[0-9]+]], [[SB]] 12 ; SI: V_DIV_FIXUP_F32 [[RESULT:v[0-9]+]], [[SA]], [[VB]], [[VC]] 13 ; SI: BUFFER_STORE_DWORD [[RESULT]], 14 ; SI: S_ENDPGM 15 define void @test_div_fixup_f32(float addrspace(1)* %out, float %a, float %b, float %c) nounwind { 16 %result = call float @llvm.AMDGPU.div.fixup.f32(float %a, float %b, float %c) nounwind readnone 17 store float %result, float addrspace(1)* %out, align 4 18 ret void 19 } 20 21 ; SI-LABEL: @test_div_fixup_f64: 22 ; SI: V_DIV_FIXUP_F64 23 define void @test_div_fixup_f64(double addrspace(1)* %out, double %a, double %b, double %c) nounwind { 24 %result = call double @llvm.AMDGPU.div.fixup.f64(double %a, double %b, double %c) nounwind readnone 25 store double %result, double addrspace(1)* %out, align 8 26 ret void 27 } 28
