1 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=R600 -check-prefix=FUNC %s 2 ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s 3 4 ; FUNC-LABEL: @rotl_i32: 5 ; R600: SUB_INT {{\** T[0-9]+\.[XYZW]}}, literal.x 6 ; R600-NEXT: 32 7 ; R600: BIT_ALIGN_INT {{T[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].Z, PV.{{[XYZW]}} 8 9 ; SI: S_SUB_I32 [[SDST:s[0-9]+]], 32, {{[s][0-9]+}} 10 ; SI: V_MOV_B32_e32 [[VDST:v[0-9]+]], [[SDST]] 11 ; SI: V_ALIGNBIT_B32 {{v[0-9]+, [s][0-9]+, v[0-9]+}}, [[VDST]] 12 define void @rotl_i32(i32 addrspace(1)* %in, i32 %x, i32 %y) { 13 entry: 14 %0 = shl i32 %x, %y 15 %1 = sub i32 32, %y 16 %2 = lshr i32 %x, %1 17 %3 = or i32 %0, %2 18 store i32 %3, i32 addrspace(1)* %in 19 ret void 20 } 21 22 ; FUNC-LABEL: @rotl_v2i32 23 ; SI: S_SUB_I32 24 ; SI: V_ALIGNBIT_B32 25 ; SI: S_SUB_I32 26 ; SI: V_ALIGNBIT_B32 27 define void @rotl_v2i32(<2 x i32> addrspace(1)* %in, <2 x i32> %x, <2 x i32> %y) { 28 entry: 29 %0 = shl <2 x i32> %x, %y 30 %1 = sub <2 x i32> <i32 32, i32 32>, %y 31 %2 = lshr <2 x i32> %x, %1 32 %3 = or <2 x i32> %0, %2 33 store <2 x i32> %3, <2 x i32> addrspace(1)* %in 34 ret void 35 } 36 37 ; FUNC-LABEL: @rotl_v4i32 38 ; SI: S_SUB_I32 39 ; SI: V_ALIGNBIT_B32 40 ; SI: S_SUB_I32 41 ; SI: V_ALIGNBIT_B32 42 ; SI: S_SUB_I32 43 ; SI: V_ALIGNBIT_B32 44 ; SI: S_SUB_I32 45 ; SI: V_ALIGNBIT_B32 46 define void @rotl_v4i32(<4 x i32> addrspace(1)* %in, <4 x i32> %x, <4 x i32> %y) { 47 entry: 48 %0 = shl <4 x i32> %x, %y 49 %1 = sub <4 x i32> <i32 32, i32 32, i32 32, i32 32>, %y 50 %2 = lshr <4 x i32> %x, %1 51 %3 = or <4 x i32> %0, %2 52 store <4 x i32> %3, <4 x i32> addrspace(1)* %in 53 ret void 54 } 55
