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      1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl -fp-contract=fast | FileCheck %s
      2 
      3 ; CHECK-LABEL: test_x86_fmadd_ps_z
      4 ; CHECK: vfmadd213ps     %zmm2, %zmm1, %zmm0
      5 ; CHECK: ret
      6 define <16 x float> @test_x86_fmadd_ps_z(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) {
      7   %x = fmul <16 x float> %a0, %a1
      8   %res = fadd <16 x float> %x, %a2
      9   ret <16 x float> %res
     10 }
     11 
     12 ; CHECK-LABEL: test_x86_fmsub_ps_z
     13 ; CHECK: vfmsub213ps     %zmm2, %zmm1, %zmm0
     14 ; CHECK: ret
     15 define <16 x float> @test_x86_fmsub_ps_z(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) {
     16   %x = fmul <16 x float> %a0, %a1
     17   %res = fsub <16 x float> %x, %a2
     18   ret <16 x float> %res
     19 }
     20 
     21 ; CHECK-LABEL: test_x86_fnmadd_ps_z
     22 ; CHECK: vfnmadd213ps     %zmm2, %zmm1, %zmm0
     23 ; CHECK: ret
     24 define <16 x float> @test_x86_fnmadd_ps_z(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) {
     25   %x = fmul <16 x float> %a0, %a1
     26   %res = fsub <16 x float> %a2, %x
     27   ret <16 x float> %res
     28 }
     29 
     30 ; CHECK-LABEL: test_x86_fnmsub_ps_z
     31 ; CHECK: vfnmsub213ps     %zmm2, %zmm1, %zmm0
     32 ; CHECK: ret
     33 define <16 x float> @test_x86_fnmsub_ps_z(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) {
     34   %x = fmul <16 x float> %a0, %a1
     35   %y = fsub <16 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, 
     36                           float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00,
     37 						  float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, 
     38 						  float -0.000000e+00>, %x
     39   %res = fsub <16 x float> %y, %a2
     40   ret <16 x float> %res
     41 }
     42 
     43 ; CHECK-LABEL: test_x86_fmadd_pd_z
     44 ; CHECK: vfmadd213pd     %zmm2, %zmm1, %zmm0
     45 ; CHECK: ret
     46 define <8 x double> @test_x86_fmadd_pd_z(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) {
     47   %x = fmul <8 x double> %a0, %a1
     48   %res = fadd <8 x double> %x, %a2
     49   ret <8 x double> %res
     50 }
     51 
     52 ; CHECK-LABEL: test_x86_fmsub_pd_z
     53 ; CHECK: vfmsub213pd     %zmm2, %zmm1, %zmm0
     54 ; CHECK: ret
     55 define <8 x double> @test_x86_fmsub_pd_z(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) {
     56   %x = fmul <8 x double> %a0, %a1
     57   %res = fsub <8 x double> %x, %a2
     58   ret <8 x double> %res
     59 }
     60 
     61 define double @test_x86_fmsub_sd_z(double %a0, double %a1, double %a2) {
     62   %x = fmul double %a0, %a1
     63   %res = fsub double %x, %a2
     64   ret double %res
     65 }
     66 
     67 ;CHECK-LABEL: test132_br
     68 ;CHECK: vfmadd132ps  LCP{{.*}}(%rip){1to16}
     69 ;CHECK: ret
     70 define <16 x float> @test132_br(<16 x float> %a1, <16 x float> %a2) nounwind {
     71   %b1 = fmul <16 x float> %a1, <float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000>
     72   %b2 = fadd <16 x float> %b1, %a2
     73   ret <16 x float> %b2
     74 }
     75 
     76 ;CHECK-LABEL: test213_br
     77 ;CHECK: vfmadd213ps  LCP{{.*}}(%rip){1to16}
     78 ;CHECK: ret
     79 define <16 x float> @test213_br(<16 x float> %a1, <16 x float> %a2) nounwind {
     80   %b1 = fmul <16 x float> %a1, %a2
     81   %b2 = fadd <16 x float> %b1, <float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000>
     82   ret <16 x float> %b2
     83 }
     84