1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl --show-mc-encoding| FileCheck %s 2 3 ;CHECK-LABEL: _inreg16xi32: 4 ;CHECK: vpbroadcastd {{.*}}, %zmm 5 ;CHECK: ret 6 define <16 x i32> @_inreg16xi32(i32 %a) { 7 %b = insertelement <16 x i32> undef, i32 %a, i32 0 8 %c = shufflevector <16 x i32> %b, <16 x i32> undef, <16 x i32> zeroinitializer 9 ret <16 x i32> %c 10 } 11 12 ;CHECK-LABEL: _inreg8xi64: 13 ;CHECK: vpbroadcastq {{.*}}, %zmm 14 ;CHECK: ret 15 define <8 x i64> @_inreg8xi64(i64 %a) { 16 %b = insertelement <8 x i64> undef, i64 %a, i32 0 17 %c = shufflevector <8 x i64> %b, <8 x i64> undef, <8 x i32> zeroinitializer 18 ret <8 x i64> %c 19 } 20 21 ;CHECK-LABEL: _inreg16xfloat: 22 ;CHECK: vbroadcastss {{.*}}, %zmm 23 ;CHECK: ret 24 define <16 x float> @_inreg16xfloat(float %a) { 25 %b = insertelement <16 x float> undef, float %a, i32 0 26 %c = shufflevector <16 x float> %b, <16 x float> undef, <16 x i32> zeroinitializer 27 ret <16 x float> %c 28 } 29 30 ;CHECK-LABEL: _inreg8xdouble: 31 ;CHECK: vbroadcastsd {{.*}}, %zmm 32 ;CHECK: ret 33 define <8 x double> @_inreg8xdouble(double %a) { 34 %b = insertelement <8 x double> undef, double %a, i32 0 35 %c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer 36 ret <8 x double> %c 37 } 38 39 ;CHECK-LABEL: _xmm16xi32 40 ;CHECK: vpbroadcastd 41 ;CHECK: ret 42 define <16 x i32> @_xmm16xi32(<16 x i32> %a) { 43 %b = shufflevector <16 x i32> %a, <16 x i32> undef, <16 x i32> zeroinitializer 44 ret <16 x i32> %b 45 } 46 47 ;CHECK-LABEL: _xmm16xfloat 48 ;CHECK: vbroadcastss {{.*}}## encoding: [0x62 49 ;CHECK: ret 50 define <16 x float> @_xmm16xfloat(<16 x float> %a) { 51 %b = shufflevector <16 x float> %a, <16 x float> undef, <16 x i32> zeroinitializer 52 ret <16 x float> %b 53 } 54 55 define <16 x i32> @test_vbroadcast() { 56 ; CHECK: vpbroadcastd 57 entry: 58 %0 = sext <16 x i1> zeroinitializer to <16 x i32> 59 %1 = fcmp uno <16 x float> undef, zeroinitializer 60 %2 = sext <16 x i1> %1 to <16 x i32> 61 %3 = select <16 x i1> %1, <16 x i32> %0, <16 x i32> %2 62 ret <16 x i32> %3 63 } 64 65
