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      1 ; RUN: llc < %s -mattr=+sha -mtriple=x86_64-unknown-unknown | FileCheck %s
      2 ; RUN: not llc < %s -mtriple=x86_64-unknown-unknown
      3 
      4 declare <4 x i32> @llvm.x86.sha1rnds4(<4 x i32>, <4 x i32>, i8) nounwind readnone
      5 
      6 define <4 x i32> @test_sha1rnds4rr(<4 x i32> %a, <4 x i32> %b) nounwind uwtable {
      7 entry:
      8   %0 = tail call <4 x i32> @llvm.x86.sha1rnds4(<4 x i32> %a, <4 x i32> %b, i8 3)
      9   ret <4 x i32> %0
     10   ; CHECK: test_sha1rnds4rr
     11   ; CHECK: sha1rnds4 $3, %xmm1, %xmm0
     12 }
     13 
     14 define <4 x i32> @test_sha1rnds4rm(<4 x i32> %a, <4 x i32>* %b) nounwind uwtable {
     15 entry:
     16   %0 = load <4 x i32>* %b
     17   %1 = tail call <4 x i32> @llvm.x86.sha1rnds4(<4 x i32> %a, <4 x i32> %0, i8 3)
     18   ret <4 x i32> %1
     19   ; CHECK: test_sha1rnds4rm
     20   ; CHECK: sha1rnds4 $3, (%rdi), %xmm0
     21 }
     22 
     23 declare <4 x i32> @llvm.x86.sha1nexte(<4 x i32>, <4 x i32>) nounwind readnone
     24 
     25 define <4 x i32> @test_sha1nexterr(<4 x i32> %a, <4 x i32> %b) nounwind uwtable {
     26 entry:
     27   %0 = tail call <4 x i32> @llvm.x86.sha1nexte(<4 x i32> %a, <4 x i32> %b)
     28   ret <4 x i32> %0
     29   ; CHECK: test_sha1nexterr
     30   ; CHECK: sha1nexte %xmm1, %xmm0
     31 }
     32 
     33 define <4 x i32> @test_sha1nexterm(<4 x i32> %a, <4 x i32>* %b) nounwind uwtable {
     34 entry:
     35   %0 = load <4 x i32>* %b
     36   %1 = tail call <4 x i32> @llvm.x86.sha1nexte(<4 x i32> %a, <4 x i32> %0)
     37   ret <4 x i32> %1
     38   ; CHECK: test_sha1nexterm
     39   ; CHECK: sha1nexte (%rdi), %xmm0
     40 }
     41 
     42 declare <4 x i32> @llvm.x86.sha1msg1(<4 x i32>, <4 x i32>) nounwind readnone
     43 
     44 define <4 x i32> @test_sha1msg1rr(<4 x i32> %a, <4 x i32> %b) nounwind uwtable {
     45 entry:
     46   %0 = tail call <4 x i32> @llvm.x86.sha1msg1(<4 x i32> %a, <4 x i32> %b)
     47   ret <4 x i32> %0
     48   ; CHECK: test_sha1msg1rr
     49   ; CHECK: sha1msg1 %xmm1, %xmm0
     50 }
     51 
     52 define <4 x i32> @test_sha1msg1rm(<4 x i32> %a, <4 x i32>* %b) nounwind uwtable {
     53 entry:
     54   %0 = load <4 x i32>* %b
     55   %1 = tail call <4 x i32> @llvm.x86.sha1msg1(<4 x i32> %a, <4 x i32> %0)
     56   ret <4 x i32> %1
     57   ; CHECK: test_sha1msg1rm
     58   ; CHECK: sha1msg1 (%rdi), %xmm0
     59 }
     60 
     61 declare <4 x i32> @llvm.x86.sha1msg2(<4 x i32>, <4 x i32>) nounwind readnone
     62 
     63 define <4 x i32> @test_sha1msg2rr(<4 x i32> %a, <4 x i32> %b) nounwind uwtable {
     64 entry:
     65   %0 = tail call <4 x i32> @llvm.x86.sha1msg2(<4 x i32> %a, <4 x i32> %b)
     66   ret <4 x i32> %0
     67   ; CHECK: test_sha1msg2rr
     68   ; CHECK: sha1msg2 %xmm1, %xmm0
     69 }
     70 
     71 define <4 x i32> @test_sha1msg2rm(<4 x i32> %a, <4 x i32>* %b) nounwind uwtable {
     72 entry:
     73   %0 = load <4 x i32>* %b
     74   %1 = tail call <4 x i32> @llvm.x86.sha1msg2(<4 x i32> %a, <4 x i32> %0)
     75   ret <4 x i32> %1
     76   ; CHECK: test_sha1msg2rm
     77   ; CHECK: sha1msg2 (%rdi), %xmm0
     78 }
     79 
     80 declare <4 x i32> @llvm.x86.sha256rnds2(<4 x i32>, <4 x i32>, <4 x i32>) nounwind readnone
     81 
     82 define <4 x i32> @test_sha256rnds2rr(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) nounwind uwtable {
     83 entry:
     84   %0 = tail call <4 x i32> @llvm.x86.sha256rnds2(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c)
     85   ret <4 x i32> %0
     86   ; CHECK: test_sha256rnds2rr
     87   ; CHECK: movaps %xmm0, [[XMM_TMP1:%xmm[1-9][0-9]?]]
     88   ; CHECK: movaps %xmm2, %xmm0
     89   ; CHECK: sha256rnds2 %xmm1, [[XMM_TMP1]]
     90 }
     91 
     92 define <4 x i32> @test_sha256rnds2rm(<4 x i32> %a, <4 x i32>* %b, <4 x i32> %c) nounwind uwtable {
     93 entry:
     94   %0 = load <4 x i32>* %b
     95   %1 = tail call <4 x i32> @llvm.x86.sha256rnds2(<4 x i32> %a, <4 x i32> %0, <4 x i32> %c)
     96   ret <4 x i32> %1
     97   ; CHECK: test_sha256rnds2rm
     98   ; CHECK: movaps %xmm0, [[XMM_TMP2:%xmm[1-9][0-9]?]]
     99   ; CHECK: movaps %xmm1, %xmm0
    100   ; CHECK: sha256rnds2 (%rdi), [[XMM_TMP2]]
    101 }
    102 
    103 declare <4 x i32> @llvm.x86.sha256msg1(<4 x i32>, <4 x i32>) nounwind readnone
    104 
    105 define <4 x i32> @test_sha256msg1rr(<4 x i32> %a, <4 x i32> %b) nounwind uwtable {
    106 entry:
    107   %0 = tail call <4 x i32> @llvm.x86.sha256msg1(<4 x i32> %a, <4 x i32> %b)
    108   ret <4 x i32> %0
    109   ; CHECK: test_sha256msg1rr
    110   ; CHECK: sha256msg1 %xmm1, %xmm0
    111 }
    112 
    113 define <4 x i32> @test_sha256msg1rm(<4 x i32> %a, <4 x i32>* %b) nounwind uwtable {
    114 entry:
    115   %0 = load <4 x i32>* %b
    116   %1 = tail call <4 x i32> @llvm.x86.sha256msg1(<4 x i32> %a, <4 x i32> %0)
    117   ret <4 x i32> %1
    118   ; CHECK: test_sha256msg1rm
    119   ; CHECK: sha256msg1 (%rdi), %xmm0
    120 }
    121 
    122 declare <4 x i32> @llvm.x86.sha256msg2(<4 x i32>, <4 x i32>) nounwind readnone
    123 
    124 define <4 x i32> @test_sha256msg2rr(<4 x i32> %a, <4 x i32> %b) nounwind uwtable {
    125 entry:
    126   %0 = tail call <4 x i32> @llvm.x86.sha256msg2(<4 x i32> %a, <4 x i32> %b)
    127   ret <4 x i32> %0
    128   ; CHECK: test_sha256msg2rr
    129   ; CHECK: sha256msg2 %xmm1, %xmm0
    130 }
    131 
    132 define <4 x i32> @test_sha256msg2rm(<4 x i32> %a, <4 x i32>* %b) nounwind uwtable {
    133 entry:
    134   %0 = load <4 x i32>* %b
    135   %1 = tail call <4 x i32> @llvm.x86.sha256msg2(<4 x i32> %a, <4 x i32> %0)
    136   ret <4 x i32> %1
    137   ; CHECK: test_sha256msg2rm
    138   ; CHECK: sha256msg2 (%rdi), %xmm0
    139 }