1 ; RUN: llc < %s -mcpu=x86-64 -x86-experimental-vector-widening-legalization -x86-experimental-vector-shuffle-lowering | FileCheck %s 2 3 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" 4 target triple = "x86_64-unknown-unknown" 5 6 define <4 x i32> @zext_v4i8_to_v4i32(<4 x i8>* %ptr) { 7 ; CHECK-LABEL: zext_v4i8_to_v4i32: 8 ; 9 ; CHECK: movd (%{{.*}}), %[[X:xmm[0-9]+]] 10 ; CHECK-NEXT: pxor %[[Z:xmm[0-9]+]], %[[Z]] 11 ; CHECK-NEXT: punpcklbw %[[Z]], %[[X]] 12 ; CHECK-NEXT: punpcklbw %[[Z]], %[[X]] 13 ; CHECK-NEXT: ret 14 15 %val = load <4 x i8>* %ptr 16 %ext = zext <4 x i8> %val to <4 x i32> 17 ret <4 x i32> %ext 18 } 19
