1 # RUN: llvm-mc -disassemble -triple armv8 -mattr=+db -show-encoding < %s | FileCheck %s 2 3 # New v8 ARM instructions 4 5 # HLT 6 7 0x70 0x00 0x00 0xe1 8 # CHECK: hlt #0 9 10 0x7f 0xff 0x0f 0xe1 11 # CHECK: hlt #65535 12 13 0x59 0xf0 0x7f 0xf5 14 0x51 0xf0 0x7f 0xf5 15 0x55 0xf0 0x7f 0xf5 16 0x5d 0xf0 0x7f 0xf5 17 # CHECK: dmb ishld 18 # CHECK: dmb oshld 19 # CHECK: dmb nshld 20 # CHECK: dmb ld 21 22 0x05 0xf0 0x20 0xe3 23 # CHECK: sevl 24 25 26 # These are the only coprocessor instructions that remain defined in ARMv8 27 # (The operations on p10/p11 disassemble into FP/NEON instructions) 28 29 0x10 0x0e 0x00 0xee 30 # CHECK: mcr p14 31 32 0x10 0x0f 0x00 0xee 33 # CHECK: mcr p15 34 35 0x10 0x0e 0x10 0xee 36 # CHECK: mrc p14 37 38 0x10 0x0f 0x10 0xee 39 # CHECK: mrc p15 40 41 0x00 0x0e 0x40 0xec 42 # CHECK: mcrr p14 43 44 0x00 0x0f 0x40 0xec 45 # CHECK: mcrr p15 46 47 0x00 0x0e 0x50 0xec 48 # CHECK: mrrc p14 49 50 0x00 0x0f 0x50 0xec 51 # CHECK: mrrc p15 52 53 0x00 0x0e 0x80 0xec 54 # CHECK: stc p14 55 56 0x00 0x0e 0x90 0xec 57 # CHECK: ldc p14 58 59
