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      1 //===- DisassemblerEmitter.cpp - Generate a disassembler ------------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 
     10 #include "CodeGenTarget.h"
     11 #include "X86DisassemblerTables.h"
     12 #include "X86RecognizableInstr.h"
     13 #include "llvm/TableGen/Error.h"
     14 #include "llvm/TableGen/Record.h"
     15 #include "llvm/TableGen/TableGenBackend.h"
     16 
     17 using namespace llvm;
     18 using namespace llvm::X86Disassembler;
     19 
     20 /// DisassemblerEmitter - Contains disassembler table emitters for various
     21 /// architectures.
     22 
     23 /// X86 Disassembler Emitter
     24 ///
     25 /// *** IF YOU'RE HERE TO RESOLVE A "Primary decode conflict", LOOK DOWN NEAR
     26 ///     THE END OF THIS COMMENT!
     27 ///
     28 /// The X86 disassembler emitter is part of the X86 Disassembler, which is
     29 /// documented in lib/Target/X86/X86Disassembler.h.
     30 ///
     31 /// The emitter produces the tables that the disassembler uses to translate
     32 /// instructions.  The emitter generates the following tables:
     33 ///
     34 /// - One table (CONTEXTS_SYM) that contains a mapping of attribute masks to
     35 ///   instruction contexts.  Although for each attribute there are cases where
     36 ///   that attribute determines decoding, in the majority of cases decoding is
     37 ///   the same whether or not an attribute is present.  For example, a 64-bit
     38 ///   instruction with an OPSIZE prefix and an XS prefix decodes the same way in
     39 ///   all cases as a 64-bit instruction with only OPSIZE set.  (The XS prefix
     40 ///   may have effects on its execution, but does not change the instruction
     41 ///   returned.)  This allows considerable space savings in other tables.
     42 /// - Six tables (ONEBYTE_SYM, TWOBYTE_SYM, THREEBYTE38_SYM, THREEBYTE3A_SYM,
     43 ///   THREEBYTEA6_SYM, and THREEBYTEA7_SYM contain the hierarchy that the
     44 ///   decoder traverses while decoding an instruction.  At the lowest level of
     45 ///   this hierarchy are instruction UIDs, 16-bit integers that can be used to
     46 ///   uniquely identify the instruction and correspond exactly to its position
     47 ///   in the list of CodeGenInstructions for the target.
     48 /// - One table (INSTRUCTIONS_SYM) contains information about the operands of
     49 ///   each instruction and how to decode them.
     50 ///
     51 /// During table generation, there may be conflicts between instructions that
     52 /// occupy the same space in the decode tables.  These conflicts are resolved as
     53 /// follows in setTableFields() (X86DisassemblerTables.cpp)
     54 ///
     55 /// - If the current context is the native context for one of the instructions
     56 ///   (that is, the attributes specified for it in the LLVM tables specify
     57 ///   precisely the current context), then it has priority.
     58 /// - If the current context isn't native for either of the instructions, then
     59 ///   the higher-priority context wins (that is, the one that is more specific).
     60 ///   That hierarchy is determined by outranks() (X86DisassemblerTables.cpp)
     61 /// - If the current context is native for both instructions, then the table
     62 ///   emitter reports a conflict and dies.
     63 ///
     64 /// *** RESOLUTION FOR "Primary decode conflict"S
     65 ///
     66 /// If two instructions collide, typically the solution is (in order of
     67 /// likelihood):
     68 ///
     69 /// (1) to filter out one of the instructions by editing filter()
     70 ///     (X86RecognizableInstr.cpp).  This is the most common resolution, but
     71 ///     check the Intel manuals first to make sure that (2) and (3) are not the
     72 ///     problem.
     73 /// (2) to fix the tables (X86.td and its subsidiaries) so the opcodes are
     74 ///     accurate.  Sometimes they are not.
     75 /// (3) to fix the tables to reflect the actual context (for example, required
     76 ///     prefixes), and possibly to add a new context by editing
     77 ///     lib/Target/X86/X86DisassemblerDecoderCommon.h.  This is unlikely to be
     78 ///     the cause.
     79 ///
     80 /// DisassemblerEmitter.cpp contains the implementation for the emitter,
     81 ///   which simply pulls out instructions from the CodeGenTarget and pushes them
     82 ///   into X86DisassemblerTables.
     83 /// X86DisassemblerTables.h contains the interface for the instruction tables,
     84 ///   which manage and emit the structures discussed above.
     85 /// X86DisassemblerTables.cpp contains the implementation for the instruction
     86 ///   tables.
     87 /// X86ModRMFilters.h contains filters that can be used to determine which
     88 ///   ModR/M values are valid for a particular instruction.  These are used to
     89 ///   populate ModRMDecisions.
     90 /// X86RecognizableInstr.h contains the interface for a single instruction,
     91 ///   which knows how to translate itself from a CodeGenInstruction and provide
     92 ///   the information necessary for integration into the tables.
     93 /// X86RecognizableInstr.cpp contains the implementation for a single
     94 ///   instruction.
     95 
     96 namespace llvm {
     97 
     98 extern void EmitFixedLenDecoder(RecordKeeper &RK, raw_ostream &OS,
     99                                 std::string PredicateNamespace,
    100                                 std::string GPrefix,
    101                                 std::string GPostfix,
    102                                 std::string ROK,
    103                                 std::string RFail,
    104                                 std::string L);
    105 
    106 void EmitDisassembler(RecordKeeper &Records, raw_ostream &OS) {
    107   CodeGenTarget Target(Records);
    108   emitSourceFileHeader(" * " + Target.getName() + " Disassembler", OS);
    109 
    110   // X86 uses a custom disassembler.
    111   if (Target.getName() == "X86") {
    112     DisassemblerTables Tables;
    113 
    114     const std::vector<const CodeGenInstruction*> &numberedInstructions =
    115       Target.getInstructionsByEnumValue();
    116 
    117     for (unsigned i = 0, e = numberedInstructions.size(); i != e; ++i)
    118       RecognizableInstr::processInstr(Tables, *numberedInstructions[i], i);
    119 
    120     if (Tables.hasConflicts()) {
    121       PrintError(Target.getTargetRecord()->getLoc(), "Primary decode conflict");
    122       return;
    123     }
    124 
    125     Tables.emit(OS);
    126     return;
    127   }
    128 
    129   // ARM and Thumb have a CHECK() macro to deal with DecodeStatuses.
    130   if (Target.getName() == "ARM" || Target.getName() == "Thumb" ||
    131       Target.getName() == "AArch64" || Target.getName() == "ARM64") {
    132     std::string PredicateNamespace = Target.getName();
    133     if (PredicateNamespace == "Thumb")
    134       PredicateNamespace = "ARM";
    135 
    136     EmitFixedLenDecoder(Records, OS, PredicateNamespace,
    137                         "if (!Check(S, ", ")) return MCDisassembler::Fail;",
    138                         "S", "MCDisassembler::Fail",
    139                         "  MCDisassembler::DecodeStatus S = "
    140                           "MCDisassembler::Success;\n(void)S;");
    141     return;
    142   }
    143 
    144   EmitFixedLenDecoder(Records, OS, Target.getName(),
    145                       "if (", " == MCDisassembler::Fail)"
    146                        " return MCDisassembler::Fail;",
    147                       "MCDisassembler::Success", "MCDisassembler::Fail", "");
    148 }
    149 
    150 } // End llvm namespace
    151