1 # 2 # VR5500, VR5532 and VR7701 events 3 # 4 # Very similar to what the VR5432 provides. 5 # 6 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : Processor clock cycles 7 event:0x1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS_EXECUTED : Instructions executed 8 event:0x2 counters:0,1 um:zero minimum:500 name:LOAD_PREF_CACHE_INSTRUCTIONS : Execution of load/prefetch/cache instruction 9 event:0x3 counters:0,1 um:zero minimum:500 name:STORES : Execution of store instruction 10 event:0x4 counters:0,1 um:zero minimum:500 name:BRANCHES : Execution of branch instruction 11 event:0x5 counters:0,1 um:zero minimum:500 name:FP_INSTRUCTIONS : Execution of floating-point instruction 12 event:0x6 counters:0,1 um:zero minimum:500 name:DOUBLEWORDS_FLUSHED : Doubleword flush to main memory 13 event:0x7 counters:0,1 um:zero minimum:500 name:JTLB_REFILLS : TLB refill 14 event:0x8 counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : Data cache miss 15 event:0x9 counters:0,1 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache miss 16 event:0xa counters:0,1 um:zero minimum:500 name:BRANCHES_MISPREDICTED : Branch prediction miss 17
