1 /* 2 * QEMU PCI bus manager 3 * 4 * Copyright (c) 2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "cpu.h" 25 #include "hw/hw.h" 26 #include "hw/pci/pci.h" 27 #include "monitor/monitor.h" 28 #include "net/net.h" 29 #include "sysemu/sysemu.h" 30 31 //#define DEBUG_PCI 32 33 struct PCIBus { 34 BusState qbus; 35 int bus_num; 36 int devfn_min; 37 pci_set_irq_fn set_irq; 38 pci_map_irq_fn map_irq; 39 uint32_t config_reg; /* XXX: suppress */ 40 /* low level pic */ 41 SetIRQFunc *low_set_irq; 42 qemu_irq *irq_opaque; 43 PCIDevice *devices[256]; 44 PCIDevice *parent_dev; 45 PCIBus *next; 46 /* The bus IRQ state is the logical OR of the connected devices. 47 Keep a count of the number of devices with raised IRQs. */ 48 int nirq; 49 int irq_count[]; 50 }; 51 52 static void pci_update_mappings(PCIDevice *d); 53 static void pci_set_irq(void *opaque, int irq_num, int level); 54 55 hwaddr pci_mem_base; 56 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; 57 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; 58 static PCIBus *first_bus; 59 60 static void pcibus_save(QEMUFile *f, void *opaque) 61 { 62 PCIBus *bus = (PCIBus *)opaque; 63 int i; 64 65 qemu_put_be32(f, bus->nirq); 66 for (i = 0; i < bus->nirq; i++) 67 qemu_put_be32(f, bus->irq_count[i]); 68 } 69 70 static int pcibus_load(QEMUFile *f, void *opaque, int version_id) 71 { 72 PCIBus *bus = (PCIBus *)opaque; 73 int i, nirq; 74 75 if (version_id != 1) 76 return -EINVAL; 77 78 nirq = qemu_get_be32(f); 79 if (bus->nirq != nirq) { 80 fprintf(stderr, "pcibus_load: nirq mismatch: src=%d dst=%d\n", 81 nirq, bus->nirq); 82 return -EINVAL; 83 } 84 85 for (i = 0; i < nirq; i++) 86 bus->irq_count[i] = qemu_get_be32(f); 87 88 return 0; 89 } 90 91 PCIBus *pci_register_bus(DeviceState *parent, const char *name, 92 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 93 qemu_irq *pic, int devfn_min, int nirq) 94 { 95 PCIBus *bus; 96 static int nbus = 0; 97 98 bus = FROM_QBUS(PCIBus, qbus_create(BUS_TYPE_PCI, 99 sizeof(PCIBus) + (nirq * sizeof(int)), 100 parent, name)); 101 bus->set_irq = set_irq; 102 bus->map_irq = map_irq; 103 bus->irq_opaque = pic; 104 bus->devfn_min = devfn_min; 105 bus->nirq = nirq; 106 bus->next = first_bus; 107 first_bus = bus; 108 register_savevm(NULL, "PCIBUS", nbus++, 1, pcibus_save, pcibus_load, bus); 109 return bus; 110 } 111 112 static PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq) 113 { 114 PCIBus *bus; 115 bus = g_malloc0(sizeof(PCIBus)); 116 bus->map_irq = map_irq; 117 bus->parent_dev = dev; 118 bus->next = dev->bus->next; 119 dev->bus->next = bus; 120 return bus; 121 } 122 123 int pci_bus_num(PCIBus *s) 124 { 125 return s->bus_num; 126 } 127 128 void pci_device_save(PCIDevice *s, QEMUFile *f) 129 { 130 int i; 131 132 qemu_put_be32(f, 2); /* PCI device version */ 133 qemu_put_buffer(f, s->config, 256); 134 for (i = 0; i < 4; i++) 135 qemu_put_be32(f, s->irq_state[i]); 136 } 137 138 int pci_device_load(PCIDevice *s, QEMUFile *f) 139 { 140 uint32_t version_id; 141 int i; 142 143 version_id = qemu_get_be32(f); 144 if (version_id > 2) 145 return -EINVAL; 146 qemu_get_buffer(f, s->config, 256); 147 pci_update_mappings(s); 148 149 if (version_id >= 2) 150 for (i = 0; i < 4; i ++) 151 s->irq_state[i] = qemu_get_be32(f); 152 153 return 0; 154 } 155 156 static int pci_set_default_subsystem_id(PCIDevice *pci_dev) 157 { 158 uint16_t *id; 159 160 id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]); 161 id[0] = cpu_to_le16(pci_default_sub_vendor_id); 162 id[1] = cpu_to_le16(pci_default_sub_device_id); 163 return 0; 164 } 165 166 /* 167 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error 168 */ 169 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp) 170 { 171 const char *p; 172 char *e; 173 unsigned long val; 174 unsigned long dom = 0, bus = 0; 175 unsigned slot = 0; 176 177 p = addr; 178 val = strtoul(p, &e, 16); 179 if (e == p) 180 return -1; 181 if (*e == ':') { 182 bus = val; 183 p = e + 1; 184 val = strtoul(p, &e, 16); 185 if (e == p) 186 return -1; 187 if (*e == ':') { 188 dom = bus; 189 bus = val; 190 p = e + 1; 191 val = strtoul(p, &e, 16); 192 if (e == p) 193 return -1; 194 } 195 } 196 197 if (dom > 0xffff || bus > 0xff || val > 0x1f) 198 return -1; 199 200 slot = val; 201 202 if (*e) 203 return -1; 204 205 /* Note: QEMU doesn't implement domains other than 0 */ 206 if (dom != 0 || pci_find_bus(bus) == NULL) 207 return -1; 208 209 *domp = dom; 210 *busp = bus; 211 *slotp = slot; 212 return 0; 213 } 214 215 int pci_read_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp) 216 { 217 char devaddr[32]; 218 219 if (!get_param_value(devaddr, sizeof(devaddr), "pci_addr", addr)) 220 return -1; 221 222 return pci_parse_devaddr(devaddr, domp, busp, slotp); 223 } 224 225 int pci_assign_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp) 226 { 227 char devaddr[32]; 228 229 if (!get_param_value(devaddr, sizeof(devaddr), "pci_addr", addr)) 230 return -1; 231 232 if (!strcmp(devaddr, "auto")) { 233 *domp = *busp = 0; 234 *slotp = -1; 235 /* want to support dom/bus auto-assign at some point */ 236 return 0; 237 } 238 239 return pci_parse_devaddr(devaddr, domp, busp, slotp); 240 } 241 242 /* -1 for devfn means auto assign */ 243 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus, 244 const char *name, int devfn, 245 PCIConfigReadFunc *config_read, 246 PCIConfigWriteFunc *config_write) 247 { 248 if (devfn < 0) { 249 for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) { 250 if (!bus->devices[devfn]) 251 goto found; 252 } 253 return NULL; 254 found: ; 255 } 256 pci_dev->bus = bus; 257 pci_dev->devfn = devfn; 258 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); 259 memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state)); 260 pci_set_default_subsystem_id(pci_dev); 261 262 if (!config_read) 263 config_read = pci_default_read_config; 264 if (!config_write) 265 config_write = pci_default_write_config; 266 pci_dev->config_read = config_read; 267 pci_dev->config_write = config_write; 268 bus->devices[devfn] = pci_dev; 269 pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4); 270 return pci_dev; 271 } 272 273 PCIDevice *pci_register_device(PCIBus *bus, const char *name, 274 int instance_size, int devfn, 275 PCIConfigReadFunc *config_read, 276 PCIConfigWriteFunc *config_write) 277 { 278 PCIDevice *pci_dev; 279 280 pci_dev = g_malloc0(instance_size); 281 pci_dev = do_pci_register_device(pci_dev, bus, name, devfn, 282 config_read, config_write); 283 return pci_dev; 284 } 285 static hwaddr pci_to_cpu_addr(hwaddr addr) 286 { 287 return addr + pci_mem_base; 288 } 289 290 static void pci_unregister_io_regions(PCIDevice *pci_dev) 291 { 292 PCIIORegion *r; 293 int i; 294 295 for(i = 0; i < PCI_NUM_REGIONS; i++) { 296 r = &pci_dev->io_regions[i]; 297 if (!r->size || r->addr == -1) 298 continue; 299 if (r->type == PCI_ADDRESS_SPACE_IO) { 300 isa_unassign_ioport(r->addr, r->size); 301 } else { 302 cpu_register_physical_memory(pci_to_cpu_addr(r->addr), 303 r->size, 304 IO_MEM_UNASSIGNED); 305 } 306 } 307 } 308 309 int pci_unregister_device(PCIDevice *pci_dev) 310 { 311 int ret = 0; 312 313 if (pci_dev->unregister) 314 ret = pci_dev->unregister(pci_dev); 315 if (ret) 316 return ret; 317 318 pci_unregister_io_regions(pci_dev); 319 320 qemu_free_irqs(pci_dev->irq); 321 pci_dev->bus->devices[pci_dev->devfn] = NULL; 322 qdev_free(&pci_dev->qdev); 323 return 0; 324 } 325 326 void pci_register_bar(PCIDevice *pci_dev, int region_num, 327 uint32_t size, int type, 328 PCIMapIORegionFunc *map_func) 329 { 330 PCIIORegion *r; 331 uint32_t addr; 332 333 if ((unsigned int)region_num >= PCI_NUM_REGIONS) 334 return; 335 336 if (size & (size-1)) { 337 fprintf(stderr, "ERROR: PCI region size must be pow2 " 338 "type=0x%x, size=0x%x\n", type, size); 339 exit(1); 340 } 341 342 r = &pci_dev->io_regions[region_num]; 343 r->addr = -1; 344 r->size = size; 345 r->type = type; 346 r->map_func = map_func; 347 if (region_num == PCI_ROM_SLOT) { 348 addr = 0x30; 349 } else { 350 addr = 0x10 + region_num * 4; 351 } 352 pci_set_long(pci_dev->config + addr, type); 353 } 354 355 static void pci_update_mappings(PCIDevice *d) 356 { 357 PCIIORegion *r; 358 int cmd, i; 359 uint32_t last_addr, new_addr, config_ofs; 360 361 cmd = pci_get_word(d->config + PCI_COMMAND); 362 for(i = 0; i < PCI_NUM_REGIONS; i++) { 363 r = &d->io_regions[i]; 364 if (i == PCI_ROM_SLOT) { 365 config_ofs = 0x30; 366 } else { 367 config_ofs = 0x10 + i * 4; 368 } 369 if (r->size != 0) { 370 if (r->type & PCI_ADDRESS_SPACE_IO) { 371 if (cmd & PCI_COMMAND_IO) { 372 new_addr = pci_get_long(d->config + config_ofs); 373 new_addr = new_addr & ~(r->size - 1); 374 last_addr = new_addr + r->size - 1; 375 /* NOTE: we have only 64K ioports on PC */ 376 if (last_addr <= new_addr || new_addr == 0 || 377 last_addr >= 0x10000) { 378 new_addr = -1; 379 } 380 } else { 381 new_addr = -1; 382 } 383 } else { 384 if (cmd & PCI_COMMAND_MEMORY) { 385 new_addr = pci_get_long(d->config + config_ofs); 386 /* the ROM slot has a specific enable bit */ 387 if (i == PCI_ROM_SLOT && !(new_addr & 1)) 388 goto no_mem_map; 389 new_addr = new_addr & ~(r->size - 1); 390 last_addr = new_addr + r->size - 1; 391 /* NOTE: we do not support wrapping */ 392 /* XXX: as we cannot support really dynamic 393 mappings, we handle specific values as invalid 394 mappings. */ 395 if (last_addr <= new_addr || new_addr == 0 || 396 last_addr == -1) { 397 new_addr = -1; 398 } 399 } else { 400 no_mem_map: 401 new_addr = -1; 402 } 403 } 404 /* now do the real mapping */ 405 if (new_addr != r->addr) { 406 if (r->addr != -1) { 407 if (r->type & PCI_ADDRESS_SPACE_IO) { 408 int class; 409 /* NOTE: specific hack for IDE in PC case: 410 only one byte must be mapped. */ 411 class = d->config[0x0a] | (d->config[0x0b] << 8); 412 if (class == 0x0101 && r->size == 4) { 413 isa_unassign_ioport(r->addr + 2, 1); 414 } else { 415 isa_unassign_ioport(r->addr, r->size); 416 } 417 } else { 418 cpu_register_physical_memory(pci_to_cpu_addr(r->addr), 419 r->size, 420 IO_MEM_UNASSIGNED); 421 qemu_unregister_coalesced_mmio(r->addr, r->size); 422 } 423 } 424 r->addr = new_addr; 425 if (r->addr != -1) { 426 r->map_func(d, i, r->addr, r->size, r->type); 427 } 428 } 429 } 430 } 431 } 432 433 uint32_t pci_default_read_config(PCIDevice *d, 434 uint32_t address, int len) 435 { 436 uint32_t val; 437 438 switch(len) { 439 default: 440 case 4: 441 if (address <= 0xfc) { 442 val = pci_get_long(d->config + address); 443 break; 444 } 445 /* fall through */ 446 case 2: 447 if (address <= 0xfe) { 448 val = pci_get_word(d->config + address); 449 break; 450 } 451 /* fall through */ 452 case 1: 453 val = d->config[address]; 454 break; 455 } 456 return val; 457 } 458 459 void pci_default_write_config(PCIDevice *d, 460 uint32_t address, uint32_t val, int len) 461 { 462 int can_write, i; 463 uint32_t end, addr; 464 465 if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) || 466 (address >= 0x30 && address < 0x34))) { 467 PCIIORegion *r; 468 int reg; 469 470 if ( address >= 0x30 ) { 471 reg = PCI_ROM_SLOT; 472 }else{ 473 reg = (address - 0x10) >> 2; 474 } 475 r = &d->io_regions[reg]; 476 if (r->size == 0) 477 goto default_config; 478 /* compute the stored value */ 479 if (reg == PCI_ROM_SLOT) { 480 /* keep ROM enable bit */ 481 val &= (~(r->size - 1)) | 1; 482 } else { 483 val &= ~(r->size - 1); 484 val |= r->type; 485 } 486 pci_set_long(d->config + address, val); 487 pci_update_mappings(d); 488 return; 489 } 490 default_config: 491 /* not efficient, but simple */ 492 addr = address; 493 for(i = 0; i < len; i++) { 494 /* default read/write accesses */ 495 switch(d->config[0x0e]) { 496 case 0x00: 497 case 0x80: 498 switch(addr) { 499 case 0x00: 500 case 0x01: 501 case 0x02: 502 case 0x03: 503 case 0x06: 504 case 0x07: 505 case 0x08: 506 case 0x09: 507 case 0x0a: 508 case 0x0b: 509 case 0x0e: 510 case 0x10 ... 0x27: /* base */ 511 case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */ 512 case 0x30 ... 0x33: /* rom */ 513 case 0x3d: 514 can_write = 0; 515 break; 516 default: 517 can_write = 1; 518 break; 519 } 520 break; 521 default: 522 case 0x01: 523 switch(addr) { 524 case 0x00: 525 case 0x01: 526 case 0x02: 527 case 0x03: 528 case 0x06: 529 case 0x07: 530 case 0x08: 531 case 0x09: 532 case 0x0a: 533 case 0x0b: 534 case 0x0e: 535 case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */ 536 case 0x38 ... 0x3b: /* rom */ 537 case 0x3d: 538 can_write = 0; 539 break; 540 default: 541 can_write = 1; 542 break; 543 } 544 break; 545 } 546 if (can_write) { 547 /* Mask out writes to reserved bits in registers */ 548 switch (addr) { 549 case 0x05: 550 val &= ~PCI_COMMAND_RESERVED_MASK_HI; 551 break; 552 case 0x06: 553 val &= ~PCI_STATUS_RESERVED_MASK_LO; 554 break; 555 case 0x07: 556 val &= ~PCI_STATUS_RESERVED_MASK_HI; 557 break; 558 } 559 d->config[addr] = val; 560 } 561 if (++addr > 0xff) 562 break; 563 val >>= 8; 564 } 565 566 end = address + len; 567 if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) { 568 /* if the command register is modified, we must modify the mappings */ 569 pci_update_mappings(d); 570 } 571 } 572 573 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len) 574 { 575 PCIBus *s = opaque; 576 PCIDevice *pci_dev; 577 int config_addr, bus_num; 578 579 #if defined(DEBUG_PCI) && 0 580 printf("pci_data_write: addr=%08x val=%08x len=%d\n", 581 addr, val, len); 582 #endif 583 bus_num = (addr >> 16) & 0xff; 584 while (s && s->bus_num != bus_num) 585 s = s->next; 586 if (!s) 587 return; 588 pci_dev = s->devices[(addr >> 8) & 0xff]; 589 if (!pci_dev) 590 return; 591 config_addr = addr & 0xff; 592 #if defined(DEBUG_PCI) 593 printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n", 594 pci_dev->name, config_addr, val, len); 595 #endif 596 pci_dev->config_write(pci_dev, config_addr, val, len); 597 } 598 599 uint32_t pci_data_read(void *opaque, uint32_t addr, int len) 600 { 601 PCIBus *s = opaque; 602 PCIDevice *pci_dev; 603 int config_addr, bus_num; 604 uint32_t val; 605 606 bus_num = (addr >> 16) & 0xff; 607 while (s && s->bus_num != bus_num) 608 s= s->next; 609 if (!s) 610 goto fail; 611 pci_dev = s->devices[(addr >> 8) & 0xff]; 612 if (!pci_dev) { 613 fail: 614 switch(len) { 615 case 1: 616 val = 0xff; 617 break; 618 case 2: 619 val = 0xffff; 620 break; 621 default: 622 case 4: 623 val = 0xffffffff; 624 break; 625 } 626 goto the_end; 627 } 628 config_addr = addr & 0xff; 629 val = pci_dev->config_read(pci_dev, config_addr, len); 630 #if defined(DEBUG_PCI) 631 printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n", 632 pci_dev->name, config_addr, val, len); 633 #endif 634 the_end: 635 #if defined(DEBUG_PCI) && 0 636 printf("pci_data_read: addr=%08x val=%08x len=%d\n", 637 addr, val, len); 638 #endif 639 return val; 640 } 641 642 /***********************************************************/ 643 /* generic PCI irq support */ 644 645 /* 0 <= irq_num <= 3. level must be 0 or 1 */ 646 static void pci_set_irq(void *opaque, int irq_num, int level) 647 { 648 PCIDevice *pci_dev = (PCIDevice *)opaque; 649 PCIBus *bus; 650 int change; 651 652 change = level - pci_dev->irq_state[irq_num]; 653 if (!change) 654 return; 655 656 pci_dev->irq_state[irq_num] = level; 657 for (;;) { 658 bus = pci_dev->bus; 659 irq_num = bus->map_irq(pci_dev, irq_num); 660 if (bus->set_irq) 661 break; 662 pci_dev = bus->parent_dev; 663 } 664 bus->irq_count[irq_num] += change; 665 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); 666 } 667 668 /***********************************************************/ 669 /* monitor info on PCI */ 670 671 typedef struct { 672 uint16_t class; 673 const char *desc; 674 } pci_class_desc; 675 676 static const pci_class_desc pci_class_descriptions[] = 677 { 678 { 0x0100, "SCSI controller"}, 679 { 0x0101, "IDE controller"}, 680 { 0x0102, "Floppy controller"}, 681 { 0x0103, "IPI controller"}, 682 { 0x0104, "RAID controller"}, 683 { 0x0106, "SATA controller"}, 684 { 0x0107, "SAS controller"}, 685 { 0x0180, "Storage controller"}, 686 { 0x0200, "Ethernet controller"}, 687 { 0x0201, "Token Ring controller"}, 688 { 0x0202, "FDDI controller"}, 689 { 0x0203, "ATM controller"}, 690 { 0x0280, "Network controller"}, 691 { 0x0300, "VGA controller"}, 692 { 0x0301, "XGA controller"}, 693 { 0x0302, "3D controller"}, 694 { 0x0380, "Display controller"}, 695 { 0x0400, "Video controller"}, 696 { 0x0401, "Audio controller"}, 697 { 0x0402, "Phone"}, 698 { 0x0480, "Multimedia controller"}, 699 { 0x0500, "RAM controller"}, 700 { 0x0501, "Flash controller"}, 701 { 0x0580, "Memory controller"}, 702 { 0x0600, "Host bridge"}, 703 { 0x0601, "ISA bridge"}, 704 { 0x0602, "EISA bridge"}, 705 { 0x0603, "MC bridge"}, 706 { 0x0604, "PCI bridge"}, 707 { 0x0605, "PCMCIA bridge"}, 708 { 0x0606, "NUBUS bridge"}, 709 { 0x0607, "CARDBUS bridge"}, 710 { 0x0608, "RACEWAY bridge"}, 711 { 0x0680, "Bridge"}, 712 { 0x0c03, "USB controller"}, 713 { 0, NULL} 714 }; 715 716 static void pci_info_device(PCIDevice *d) 717 { 718 Monitor *mon = cur_mon; 719 int i, class; 720 PCIIORegion *r; 721 const pci_class_desc *desc; 722 723 typedef union { 724 uint16_t* ptr16; 725 void* ptr; 726 } u16; 727 728 monitor_printf(mon, " Bus %2d, device %3d, function %d:\n", 729 d->bus->bus_num, d->devfn >> 3, d->devfn & 7); 730 class = pci_get_word(d->config + PCI_CLASS_DEVICE); 731 monitor_printf(mon, " "); 732 desc = pci_class_descriptions; 733 while (desc->desc && class != desc->class) 734 desc++; 735 if (desc->desc) { 736 monitor_printf(mon, "%s", desc->desc); 737 } else { 738 monitor_printf(mon, "Class %04x", class); 739 } 740 u16 vendor_id = { .ptr = d->config + PCI_VENDOR_ID }; 741 u16 device_id = { .ptr = d->config + PCI_DEVICE_ID }; 742 743 monitor_printf(mon, ": PCI device %04x:%04x\n", 744 le16_to_cpu(*vendor_id.ptr16), 745 le16_to_cpu(*device_id.ptr16)); 746 747 if (d->config[PCI_INTERRUPT_PIN] != 0) { 748 monitor_printf(mon, " IRQ %d.\n", 749 d->config[PCI_INTERRUPT_LINE]); 750 } 751 if (class == 0x0604) { 752 monitor_printf(mon, " BUS %d.\n", d->config[0x19]); 753 } 754 for(i = 0;i < PCI_NUM_REGIONS; i++) { 755 r = &d->io_regions[i]; 756 if (r->size != 0) { 757 monitor_printf(mon, " BAR%d: ", i); 758 if (r->type & PCI_ADDRESS_SPACE_IO) { 759 monitor_printf(mon, "I/O at 0x%04x [0x%04x].\n", 760 r->addr, r->addr + r->size - 1); 761 } else { 762 monitor_printf(mon, "32 bit memory at 0x%08x [0x%08x].\n", 763 r->addr, r->addr + r->size - 1); 764 } 765 } 766 } 767 if (class == 0x0604 && d->config[0x19] != 0) { 768 pci_for_each_device(d->config[0x19], pci_info_device); 769 } 770 } 771 772 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d)) 773 { 774 PCIBus *bus = first_bus; 775 PCIDevice *d; 776 int devfn; 777 778 while (bus && bus->bus_num != bus_num) 779 bus = bus->next; 780 if (bus) { 781 for(devfn = 0; devfn < 256; devfn++) { 782 d = bus->devices[devfn]; 783 if (d) 784 fn(d); 785 } 786 } 787 } 788 789 void pci_info(Monitor *mon) 790 { 791 pci_for_each_device(0, pci_info_device); 792 } 793 794 static const char * const pci_nic_models[] = { 795 "ne2k_pci", 796 "i82551", 797 "i82557b", 798 "i82559er", 799 "rtl8139", 800 "e1000", 801 "pcnet", 802 "virtio", 803 NULL 804 }; 805 806 static const char * const pci_nic_names[] = { 807 "ne2k_pci", 808 "i82551", 809 "i82557b", 810 "i82559er", 811 "rtl8139", 812 "e1000", 813 "pcnet", 814 "virtio-net-pci", 815 NULL 816 }; 817 818 /* Initialize a PCI NIC. */ 819 PCIDevice *pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn, 820 const char *default_model) 821 { 822 DeviceState *dev; 823 int i; 824 825 qemu_check_nic_model_list(nd, pci_nic_models, default_model); 826 827 for (i = 0; pci_nic_models[i]; i++) { 828 if (strcmp(nd->model, pci_nic_models[i]) == 0) { 829 dev = qdev_create(&bus->qbus, pci_nic_names[i]); 830 qdev_set_prop_int(dev, "devfn", devfn); 831 qdev_set_netdev(dev, nd); 832 qdev_init(dev); 833 nd->private = dev; 834 return (PCIDevice *)dev; 835 } 836 } 837 838 return NULL; 839 } 840 841 struct PCIBridge { 842 PCIDevice dev; 843 PCIBus *bus; 844 }; 845 846 static void pci_bridge_write_config(PCIDevice *d, 847 uint32_t address, uint32_t val, int len) 848 { 849 PCIBridge *s = (PCIBridge *)d; 850 851 if (address == 0x19 || (address == 0x18 && len > 1)) { 852 if (address == 0x19) 853 s->bus->bus_num = val & 0xff; 854 else 855 s->bus->bus_num = (val >> 8) & 0xff; 856 #if defined(DEBUG_PCI) 857 printf ("pci-bridge: %s: Assigned bus %d\n", d->name, s->bus->bus_num); 858 #endif 859 } 860 pci_default_write_config(d, address, val, len); 861 } 862 863 PCIBus *pci_find_bus(int bus_num) 864 { 865 PCIBus *bus = first_bus; 866 867 while (bus && bus->bus_num != bus_num) 868 bus = bus->next; 869 870 return bus; 871 } 872 873 PCIDevice *pci_find_device(int bus_num, int slot, int function) 874 { 875 PCIBus *bus = pci_find_bus(bus_num); 876 877 if (!bus) 878 return NULL; 879 880 return bus->devices[PCI_DEVFN(slot, function)]; 881 } 882 883 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did, 884 pci_map_irq_fn map_irq, const char *name) 885 { 886 PCIBridge *s; 887 s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge), 888 devfn, NULL, pci_bridge_write_config); 889 890 pci_config_set_vendor_id(s->dev.config, vid); 891 pci_config_set_device_id(s->dev.config, did); 892 893 s->dev.config[0x04] = 0x06; // command = bus master, pci mem 894 s->dev.config[0x05] = 0x00; 895 s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error 896 s->dev.config[0x07] = 0x00; // status = fast devsel 897 s->dev.config[0x08] = 0x00; // revision 898 s->dev.config[0x09] = 0x00; // programming i/f 899 pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI); 900 s->dev.config[0x0D] = 0x10; // latency_timer 901 s->dev.config[PCI_HEADER_TYPE] = 902 PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE; // header_type 903 s->dev.config[0x1E] = 0xa0; // secondary status 904 905 s->bus = pci_register_secondary_bus(&s->dev, map_irq); 906 return s->bus; 907 } 908 909 typedef struct { 910 DeviceInfo qdev; 911 pci_qdev_initfn init; 912 } PCIDeviceInfo; 913 914 static void pci_qdev_init(DeviceState *qdev, DeviceInfo *base) 915 { 916 PCIDevice *pci_dev = (PCIDevice *)qdev; 917 PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev); 918 PCIBus *bus; 919 int devfn; 920 921 bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev)); 922 devfn = qdev_get_prop_int(qdev, "devfn", -1); 923 pci_dev = do_pci_register_device(pci_dev, bus, "FIXME", devfn, 924 NULL, NULL);//FIXME:config_read, config_write); 925 assert(pci_dev); 926 info->init(pci_dev); 927 } 928 929 void pci_qdev_register(const char *name, int size, pci_qdev_initfn init) 930 { 931 PCIDeviceInfo *info; 932 933 info = g_malloc0(sizeof(*info)); 934 info->qdev.name = g_strdup(name); 935 info->qdev.size = size; 936 info->init = init; 937 info->qdev.init = pci_qdev_init; 938 info->qdev.bus_type = BUS_TYPE_PCI; 939 940 qdev_register(&info->qdev); 941 } 942 943 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) 944 { 945 DeviceState *dev; 946 947 dev = qdev_create(&bus->qbus, name); 948 qdev_set_prop_int(dev, "devfn", devfn); 949 qdev_init(dev); 950 951 return (PCIDevice *)dev; 952 } 953
