1 /* Copyright (c) 2014, The Linux Foundation. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 */ 12 #ifndef __MSMB_ISP__ 13 #define __MSMB_ISP__ 14 15 #include <linux/videodev2.h> 16 17 #define MAX_PLANES_PER_STREAM 3 18 #define MAX_NUM_STREAM 7 19 20 #define ISP_VERSION_46 46 21 #define ISP_VERSION_44 44 22 #define ISP_VERSION_40 40 23 #define ISP_VERSION_32 32 24 #define ISP_NATIVE_BUF_BIT (0x10000 << 0) 25 #define ISP0_BIT (0x10000 << 1) 26 #define ISP1_BIT (0x10000 << 2) 27 #define ISP_META_CHANNEL_BIT (0x10000 << 3) 28 #define ISP_SCRATCH_BUF_BIT (0x10000 << 4) 29 #define ISP_STATS_STREAM_BIT 0x80000000 30 31 struct msm_vfe_cfg_cmd_list; 32 33 enum ISP_START_PIXEL_PATTERN { 34 ISP_BAYER_RGRGRG, 35 ISP_BAYER_GRGRGR, 36 ISP_BAYER_BGBGBG, 37 ISP_BAYER_GBGBGB, 38 ISP_YUV_YCbYCr, 39 ISP_YUV_YCrYCb, 40 ISP_YUV_CbYCrY, 41 ISP_YUV_CrYCbY, 42 ISP_PIX_PATTERN_MAX 43 }; 44 45 enum msm_vfe_plane_fmt { 46 Y_PLANE, 47 CB_PLANE, 48 CR_PLANE, 49 CRCB_PLANE, 50 CBCR_PLANE, 51 VFE_PLANE_FMT_MAX 52 }; 53 54 enum msm_vfe_input_src { 55 VFE_PIX_0, 56 VFE_RAW_0, 57 VFE_RAW_1, 58 VFE_RAW_2, 59 VFE_SRC_MAX, 60 }; 61 62 enum msm_vfe_axi_stream_src { 63 PIX_ENCODER, 64 PIX_VIEWFINDER, 65 PIX_VIDEO, 66 CAMIF_RAW, 67 IDEAL_RAW, 68 RDI_INTF_0, 69 RDI_INTF_1, 70 RDI_INTF_2, 71 VFE_AXI_SRC_MAX 72 }; 73 74 enum msm_vfe_frame_skip_pattern { 75 NO_SKIP, 76 EVERY_2FRAME, 77 EVERY_3FRAME, 78 EVERY_4FRAME, 79 EVERY_5FRAME, 80 EVERY_6FRAME, 81 EVERY_7FRAME, 82 EVERY_8FRAME, 83 EVERY_16FRAME, 84 EVERY_32FRAME, 85 SKIP_ALL, 86 MAX_SKIP, 87 }; 88 89 enum msm_vfe_camif_input { 90 CAMIF_DISABLED, 91 CAMIF_PAD_REG_INPUT, 92 CAMIF_MIDDI_INPUT, 93 CAMIF_MIPI_INPUT, 94 }; 95 96 struct msm_vfe_camif_cfg { 97 uint32_t lines_per_frame; 98 uint32_t pixels_per_line; 99 uint32_t first_pixel; 100 uint32_t last_pixel; 101 uint32_t first_line; 102 uint32_t last_line; 103 uint32_t epoch_line0; 104 uint32_t epoch_line1; 105 enum msm_vfe_camif_input camif_input; 106 }; 107 108 enum msm_vfe_inputmux { 109 CAMIF, 110 TESTGEN, 111 EXTERNAL_READ, 112 }; 113 114 enum msm_vfe_stats_composite_group { 115 STATS_COMPOSITE_GRP_NONE, 116 STATS_COMPOSITE_GRP_1, 117 STATS_COMPOSITE_GRP_2, 118 STATS_COMPOSITE_GRP_MAX, 119 }; 120 121 struct msm_vfe_pix_cfg { 122 struct msm_vfe_camif_cfg camif_cfg; 123 enum msm_vfe_inputmux input_mux; 124 enum ISP_START_PIXEL_PATTERN pixel_pattern; 125 uint32_t input_format; 126 }; 127 128 struct msm_vfe_rdi_cfg { 129 uint8_t cid; 130 uint8_t frame_based; 131 }; 132 133 struct msm_vfe_input_cfg { 134 union { 135 struct msm_vfe_pix_cfg pix_cfg; 136 struct msm_vfe_rdi_cfg rdi_cfg; 137 } d; 138 enum msm_vfe_input_src input_src; 139 uint32_t input_pix_clk; 140 }; 141 142 struct msm_vfe_axi_plane_cfg { 143 uint32_t output_width; /*Include padding*/ 144 uint32_t output_height; 145 uint32_t output_stride; 146 uint32_t output_scan_lines; 147 uint32_t output_plane_format; /*Y/Cb/Cr/CbCr*/ 148 uint32_t plane_addr_offset; 149 uint8_t csid_src; /*RDI 0-2*/ 150 uint8_t rdi_cid;/*CID 1-16*/ 151 }; 152 153 struct msm_vfe_axi_stream_request_cmd { 154 uint32_t session_id; 155 uint32_t stream_id; 156 uint32_t vt_enable; 157 uint32_t output_format;/*Planar/RAW/Misc*/ 158 enum msm_vfe_axi_stream_src stream_src; /*CAMIF/IDEAL/RDIs*/ 159 struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM]; 160 161 uint32_t burst_count; 162 uint32_t hfr_mode; 163 uint8_t frame_base; 164 165 uint32_t init_frame_drop; /*MAX 31 Frames*/ 166 enum msm_vfe_frame_skip_pattern frame_skip_pattern; 167 uint8_t buf_divert; /* if TRUE no vb2 buf done. */ 168 /*Return values*/ 169 uint32_t axi_stream_handle; 170 uint32_t controllable_output; 171 }; 172 173 struct msm_vfe_axi_stream_release_cmd { 174 uint32_t stream_handle; 175 }; 176 177 enum msm_vfe_axi_stream_cmd { 178 STOP_STREAM, 179 START_STREAM, 180 STOP_IMMEDIATELY, 181 }; 182 183 struct msm_vfe_axi_stream_cfg_cmd { 184 uint8_t num_streams; 185 uint32_t stream_handle[MAX_NUM_STREAM]; 186 enum msm_vfe_axi_stream_cmd cmd; 187 }; 188 189 enum msm_vfe_axi_stream_update_type { 190 ENABLE_STREAM_BUF_DIVERT, 191 DISABLE_STREAM_BUF_DIVERT, 192 UPDATE_STREAM_FRAMEDROP_PATTERN, 193 UPDATE_STREAM_STATS_FRAMEDROP_PATTERN, 194 UPDATE_STREAM_AXI_CONFIG, 195 UPDATE_STREAM_REQUEST_FRAMES, 196 UPDATE_STREAM_ADD_BUFQ, 197 UPDATE_STREAM_REMOVE_BUFQ, 198 }; 199 200 enum msm_vfe_iommu_type { 201 IOMMU_ATTACH, 202 IOMMU_DETACH, 203 }; 204 205 struct msm_vfe_axi_stream_cfg_update_info { 206 uint32_t stream_handle; 207 uint32_t output_format; 208 uint32_t user_stream_id; 209 uint8_t need_divert; 210 enum msm_vfe_frame_skip_pattern skip_pattern; 211 struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM]; 212 }; 213 214 struct msm_vfe_axi_stream_update_cmd { 215 uint32_t num_streams; 216 enum msm_vfe_axi_stream_update_type update_type; 217 struct msm_vfe_axi_stream_cfg_update_info update_info[MAX_NUM_STREAM]; 218 }; 219 220 struct msm_vfe_smmu_attach_cmd { 221 uint32_t security_mode; 222 uint32_t iommu_attach_mode; 223 }; 224 225 enum msm_isp_stats_type { 226 MSM_ISP_STATS_AEC, /* legacy based AEC */ 227 MSM_ISP_STATS_AF, /* legacy based AF */ 228 MSM_ISP_STATS_AWB, /* legacy based AWB */ 229 MSM_ISP_STATS_RS, /* legacy based RS */ 230 MSM_ISP_STATS_CS, /* legacy based CS */ 231 MSM_ISP_STATS_IHIST, /* legacy based HIST */ 232 MSM_ISP_STATS_SKIN, /* legacy based SKIN */ 233 MSM_ISP_STATS_BG, /* Bayer Grids */ 234 MSM_ISP_STATS_BF, /* Bayer Focus */ 235 MSM_ISP_STATS_BE, /* Bayer Exposure*/ 236 MSM_ISP_STATS_BHIST, /* Bayer Hist */ 237 MSM_ISP_STATS_BF_SCALE, /* Bayer Focus scale */ 238 MSM_ISP_STATS_HDR_BE, /* HDR Bayer Exposure */ 239 MSM_ISP_STATS_HDR_BHIST, /* HDR Bayer Hist */ 240 MSM_ISP_STATS_MAX /* MAX */ 241 }; 242 243 struct msm_vfe_stats_stream_request_cmd { 244 uint32_t session_id; 245 uint32_t stream_id; 246 enum msm_isp_stats_type stats_type; 247 uint32_t composite_flag; 248 uint32_t framedrop_pattern; 249 uint32_t init_frame_drop; /*MAX 31 Frames*/ 250 uint32_t irq_subsample_pattern; 251 uint32_t buffer_offset; 252 uint32_t stream_handle; 253 }; 254 255 struct msm_vfe_stats_stream_release_cmd { 256 uint32_t stream_handle; 257 }; 258 struct msm_vfe_stats_stream_cfg_cmd { 259 uint8_t num_streams; 260 uint32_t stream_handle[MSM_ISP_STATS_MAX]; 261 uint8_t enable; 262 }; 263 264 enum msm_vfe_reg_cfg_type { 265 VFE_WRITE, 266 VFE_WRITE_MB, 267 VFE_READ, 268 VFE_CFG_MASK, 269 VFE_WRITE_DMI_16BIT, 270 VFE_WRITE_DMI_32BIT, 271 VFE_WRITE_DMI_64BIT, 272 VFE_READ_DMI_16BIT, 273 VFE_READ_DMI_32BIT, 274 VFE_READ_DMI_64BIT, 275 GET_MAX_CLK_RATE, 276 GET_ISP_ID, 277 }; 278 279 struct msm_vfe_cfg_cmd2 { 280 uint16_t num_cfg; 281 uint16_t cmd_len; 282 void __user *cfg_data; 283 void __user *cfg_cmd; 284 }; 285 286 struct msm_vfe_cfg_cmd_list { 287 struct msm_vfe_cfg_cmd2 cfg_cmd; 288 struct msm_vfe_cfg_cmd_list *next; 289 uint32_t next_size; 290 }; 291 292 struct msm_vfe_reg_rw_info { 293 uint32_t reg_offset; 294 uint32_t cmd_data_offset; 295 uint32_t len; 296 }; 297 298 struct msm_vfe_reg_mask_info { 299 uint32_t reg_offset; 300 uint32_t mask; 301 uint32_t val; 302 }; 303 304 struct msm_vfe_reg_dmi_info { 305 uint32_t hi_tbl_offset; /*Optional*/ 306 uint32_t lo_tbl_offset; /*Required*/ 307 uint32_t len; 308 }; 309 310 struct msm_vfe_reg_cfg_cmd { 311 union { 312 struct msm_vfe_reg_rw_info rw_info; 313 struct msm_vfe_reg_mask_info mask_info; 314 struct msm_vfe_reg_dmi_info dmi_info; 315 } u; 316 317 enum msm_vfe_reg_cfg_type cmd_type; 318 }; 319 320 enum msm_isp_buf_type { 321 ISP_PRIVATE_BUF, 322 ISP_SHARE_BUF, 323 MAX_ISP_BUF_TYPE, 324 }; 325 326 struct msm_isp_buf_request { 327 uint32_t session_id; 328 uint32_t stream_id; 329 uint8_t num_buf; 330 uint32_t handle; 331 enum msm_isp_buf_type buf_type; 332 }; 333 334 struct msm_isp_qbuf_plane { 335 uint32_t addr; 336 uint32_t offset; 337 }; 338 339 struct msm_isp_qbuf_buffer { 340 struct msm_isp_qbuf_plane planes[MAX_PLANES_PER_STREAM]; 341 uint32_t num_planes; 342 }; 343 344 struct msm_isp_qbuf_info { 345 uint32_t handle; 346 int32_t buf_idx; 347 /*Only used for prepare buffer*/ 348 struct msm_isp_qbuf_buffer buffer; 349 /*Only used for diverted buffer*/ 350 uint32_t dirty_buf; 351 }; 352 353 struct msm_vfe_axi_src_state { 354 enum msm_vfe_input_src input_src; 355 uint32_t src_active; 356 }; 357 358 enum msm_isp_event_idx { 359 ISP_REG_UPDATE = 0, 360 ISP_START_ACK = 1, 361 ISP_STOP_ACK = 2, 362 ISP_IRQ_VIOLATION = 3, 363 ISP_WM_BUS_OVERFLOW = 4, 364 ISP_STATS_OVERFLOW = 5, 365 ISP_CAMIF_ERROR = 6, 366 ISP_EPOCH0_IRQ = 7, 367 ISP_BUF_DONE = 9, 368 ISP_UPDATE_AXI_DONE = 10, 369 ISP_EVENT_MAX = 11 370 }; 371 372 enum msm_isp_epoch_idx { 373 ISP_EPOCH_0 = 0, 374 ISP_EPOCH_1 = 1, 375 ISP_EPOCH_MAX = 2 376 }; 377 378 #define ISP_EVENT_OFFSET 8 379 #define ISP_EVENT_BASE (V4L2_EVENT_PRIVATE_START) 380 #define ISP_BUF_EVENT_BASE (ISP_EVENT_BASE + (1 << ISP_EVENT_OFFSET)) 381 #define ISP_STATS_EVENT_BASE (ISP_EVENT_BASE + (2 << ISP_EVENT_OFFSET)) 382 #define ISP_SOF_EVENT_BASE (ISP_EVENT_BASE + (3 << ISP_EVENT_OFFSET)) 383 #define ISP_EOF_EVENT_BASE (ISP_EVENT_BASE + (4 << ISP_EVENT_OFFSET)) 384 #define ISP_EVENT_REG_UPDATE (ISP_EVENT_BASE + ISP_REG_UPDATE) 385 #define ISP_EVENT_START_ACK (ISP_EVENT_BASE + ISP_START_ACK) 386 #define ISP_EVENT_STOP_ACK (ISP_EVENT_BASE + ISP_STOP_ACK) 387 #define ISP_EVENT_IRQ_VIOLATION (ISP_EVENT_BASE + ISP_IRQ_VIOLATION) 388 #define ISP_EVENT_WM_BUS_OVERFLOW (ISP_EVENT_BASE + ISP_WM_BUS_OVERFLOW) 389 #define ISP_EVENT_STATS_OVERFLOW (ISP_EVENT_BASE + ISP_STATS_OVERFLOW) 390 #define ISP_EVENT_CAMIF_ERROR (ISP_EVENT_BASE + ISP_CAMIF_ERROR) 391 #define ISP_EVENT_EPOCH0_IRQ (ISP_EVENT_BASE + ISP_EPOCH0_IRQ) 392 #define ISP_EVENT_UPDATE_AXI_DONE (ISP_EVENT_BASE + ISP_UPDATE_AXI_DONE) 393 #define ISP_EVENT_SOF (ISP_SOF_EVENT_BASE) 394 #define ISP_EVENT_EOF (ISP_EOF_EVENT_BASE) 395 #define ISP_EVENT_BUF_DONE (ISP_EVENT_BASE + ISP_BUF_DONE) 396 #define ISP_EVENT_BUF_DIVERT (ISP_BUF_EVENT_BASE) 397 #define ISP_EVENT_STATS_NOTIFY (ISP_STATS_EVENT_BASE) 398 #define ISP_EVENT_COMP_STATS_NOTIFY (ISP_EVENT_STATS_NOTIFY + MSM_ISP_STATS_MAX) 399 /* The msm_v4l2_event_data structure should match the 400 * v4l2_event.u.data field. 401 * should not exceed 64 bytes */ 402 403 struct msm_isp_buf_event { 404 uint32_t session_id; 405 uint32_t stream_id; 406 uint32_t handle; 407 uint32_t output_format; 408 int8_t buf_idx; 409 }; 410 struct msm_isp_stats_event { 411 uint32_t stats_mask; /* 4 bytes */ 412 uint8_t stats_buf_idxs[MSM_ISP_STATS_MAX]; /* 11 bytes */ 413 }; 414 415 struct msm_isp_stream_ack { 416 uint32_t session_id; 417 uint32_t stream_id; 418 uint32_t handle; 419 }; 420 421 struct msm_isp_epoch_event { 422 enum msm_isp_epoch_idx epoch_idx; 423 }; 424 425 struct msm_isp_event_data { 426 /*Wall clock except for buffer divert events 427 *which use monotonic clock 428 */ 429 struct timeval timestamp; 430 /* Monotonic timestamp since bootup */ 431 struct timeval mono_timestamp; 432 enum msm_vfe_input_src input_intf; 433 uint32_t frame_id; 434 union { 435 struct msm_isp_stats_event stats; 436 struct msm_isp_buf_event buf_done; 437 struct msm_isp_epoch_event epoch; 438 } u; /* union can have max 52 bytes */ 439 }; 440 441 #define V4L2_PIX_FMT_QBGGR8 v4l2_fourcc('Q', 'B', 'G', '8') 442 #define V4L2_PIX_FMT_QGBRG8 v4l2_fourcc('Q', 'G', 'B', '8') 443 #define V4L2_PIX_FMT_QGRBG8 v4l2_fourcc('Q', 'G', 'R', '8') 444 #define V4L2_PIX_FMT_QRGGB8 v4l2_fourcc('Q', 'R', 'G', '8') 445 #define V4L2_PIX_FMT_QBGGR10 v4l2_fourcc('Q', 'B', 'G', '0') 446 #define V4L2_PIX_FMT_QGBRG10 v4l2_fourcc('Q', 'G', 'B', '0') 447 #define V4L2_PIX_FMT_QGRBG10 v4l2_fourcc('Q', 'G', 'R', '0') 448 #define V4L2_PIX_FMT_QRGGB10 v4l2_fourcc('Q', 'R', 'G', '0') 449 #define V4L2_PIX_FMT_QBGGR12 v4l2_fourcc('Q', 'B', 'G', '2') 450 #define V4L2_PIX_FMT_QGBRG12 v4l2_fourcc('Q', 'G', 'B', '2') 451 #define V4L2_PIX_FMT_QGRBG12 v4l2_fourcc('Q', 'G', 'R', '2') 452 #define V4L2_PIX_FMT_QRGGB12 v4l2_fourcc('Q', 'R', 'G', '2') 453 #define V4L2_PIX_FMT_NV14 v4l2_fourcc('N', 'V', '1', '4') 454 #define V4L2_PIX_FMT_NV41 v4l2_fourcc('N', 'V', '4', '1') 455 #define V4L2_PIX_FMT_META v4l2_fourcc('Q', 'M', 'E', 'T') 456 457 #define VIDIOC_MSM_VFE_REG_CFG \ 458 _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_vfe_cfg_cmd2) 459 460 #define VIDIOC_MSM_ISP_REQUEST_BUF \ 461 _IOWR('V', BASE_VIDIOC_PRIVATE+1, struct msm_isp_buf_request) 462 463 #define VIDIOC_MSM_ISP_ENQUEUE_BUF \ 464 _IOWR('V', BASE_VIDIOC_PRIVATE+2, struct msm_isp_qbuf_info) 465 466 #define VIDIOC_MSM_ISP_RELEASE_BUF \ 467 _IOWR('V', BASE_VIDIOC_PRIVATE+3, struct msm_isp_buf_request) 468 469 #define VIDIOC_MSM_ISP_REQUEST_STREAM \ 470 _IOWR('V', BASE_VIDIOC_PRIVATE+4, struct msm_vfe_axi_stream_request_cmd) 471 472 #define VIDIOC_MSM_ISP_CFG_STREAM \ 473 _IOWR('V', BASE_VIDIOC_PRIVATE+5, struct msm_vfe_axi_stream_cfg_cmd) 474 475 #define VIDIOC_MSM_ISP_RELEASE_STREAM \ 476 _IOWR('V', BASE_VIDIOC_PRIVATE+6, struct msm_vfe_axi_stream_release_cmd) 477 478 #define VIDIOC_MSM_ISP_INPUT_CFG \ 479 _IOWR('V', BASE_VIDIOC_PRIVATE+7, struct msm_vfe_input_cfg) 480 481 #define VIDIOC_MSM_ISP_SET_SRC_STATE \ 482 _IOWR('V', BASE_VIDIOC_PRIVATE+8, struct msm_vfe_axi_src_state) 483 484 #define VIDIOC_MSM_ISP_REQUEST_STATS_STREAM \ 485 _IOWR('V', BASE_VIDIOC_PRIVATE+9, \ 486 struct msm_vfe_stats_stream_request_cmd) 487 488 #define VIDIOC_MSM_ISP_CFG_STATS_STREAM \ 489 _IOWR('V', BASE_VIDIOC_PRIVATE+10, struct msm_vfe_stats_stream_cfg_cmd) 490 491 #define VIDIOC_MSM_ISP_RELEASE_STATS_STREAM \ 492 _IOWR('V', BASE_VIDIOC_PRIVATE+11, \ 493 struct msm_vfe_stats_stream_release_cmd) 494 495 #define VIDIOC_MSM_ISP_UPDATE_STREAM \ 496 _IOWR('V', BASE_VIDIOC_PRIVATE+13, struct msm_vfe_axi_stream_update_cmd) 497 498 #define VIDIOC_MSM_VFE_REG_LIST_CFG \ 499 _IOWR('V', BASE_VIDIOC_PRIVATE+14, struct msm_vfe_cfg_cmd_list) 500 501 #define VIDIOC_MSM_ISP_SMMU_ATTACH \ 502 _IOWR('V', BASE_VIDIOC_PRIVATE+15, struct msm_vfe_smmu_attach_cmd) 503 504 #define VIDIOC_MSM_ISP_UPDATE_STATS_STREAM \ 505 _IOWR('V', BASE_VIDIOC_PRIVATE+16, struct msm_vfe_axi_stream_update_cmd) 506 507 #endif /* __MSMB_ISP__ */ 508
