Lines Matching refs:MBB
38 const MachineBasicBlock &MBB = *MI->getParent();
39 const MachineFunction *MF = MBB.getParent();
92 bool AArch64InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
98 MachineBasicBlock::iterator I = MBB.end();
99 if (I == MBB.begin())
103 if (I == MBB.begin())
115 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
139 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
151 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
225 unsigned AArch64InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
226 MachineBasicBlock::iterator I = MBB.end();
227 if (I == MBB.begin())
231 if (I == MBB.begin())
242 I = MBB.end();
244 if (I == MBB.begin())
256 MachineBasicBlock &MBB, DebugLoc DL, MachineBasicBlock *TBB,
260 BuildMI(&MBB, DL, get(AArch64::Bcc)).addImm(Cond[0].getImm()).addMBB(TBB);
264 BuildMI(&MBB, DL, get(Cond[1].getImm())).addReg(Cond[2].getReg());
272 MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
279 BuildMI(&MBB, DL, get(AArch64::B)).addMBB(TBB);
281 instantiateCondBranch(MBB, DL, TBB, Cond);
286 instantiateCondBranch(MBB, DL, TBB, Cond);
287 BuildMI(&MBB, DL, get(AArch64::B)).addMBB(FBB);
370 const MachineBasicBlock &MBB, const SmallVectorImpl<MachineOperand> &Cond,
374 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
410 void AArch64InstrInfo::insertSelect(MachineBasicBlock &MBB,
415 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
452 BuildMI(MBB, I, DL, get(AArch64::SUBSXri), AArch64::XZR)
458 BuildMI(MBB, I, DL, get(AArch64::SUBSWri), AArch64::WZR)
481 BuildMI(MBB, I, DL, get(AArch64::ANDSWri), AArch64::WZR)
486 BuildMI(MBB, I, DL, get(AArch64::ANDSXri), AArch64::XZR)
540 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(TrueReg).addReg(FalseReg).addImm(
617 MachineBasicBlock *MBB = Instr->getParent();
618 assert(MBB && "Can't get MachineBasicBlock here");
619 MachineFunction *MF = MBB->getParent();
836 for (auto *MBB : ParentBlock->successors())
837 if (MBB->isLiveIn(AArch64::NZCV))
1230 MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL,
1248 const MachineInstrBuilder &MIB = BuildMI(MBB, I, DL, get(Opcode));
1255 void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
1275 BuildMI(MBB, I, DL, get(AArch64::ADDXri), DestRegX)
1281 BuildMI(MBB, I, DL, get(AArch64::ADDWri), DestReg)
1287 BuildMI(MBB, I, DL, get(AArch64::MOVZWi), DestReg).addImm(0).addImm(
1300 BuildMI(MBB, I, DL, get(AArch64::ORRXrr), DestRegX)
1306 BuildMI(MBB, I, DL, get(AArch64::ORRWrr), DestReg)
1318 BuildMI(MBB, I, DL, get(AArch64::ADDXri), DestReg)
1323 BuildMI(MBB, I, DL, get(AArch64::MOVZXi), DestReg).addImm(0).addImm(
1327 BuildMI(MBB, I, DL, get(AArch64::ORRXrr), DestReg)
1339 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv8i8,
1349 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv8i8,
1358 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv8i8,
1368 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv16i8,
1378 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv16i8,
1387 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv16i8,
1395 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
1399 BuildMI(MBB, I, DL, get(AArch64::STRQpre))
1404 BuildMI(MBB, I, DL, get(AArch64::LDRQpre))
1420 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
1424 BuildMI(MBB, I, DL, get(AArch64::FMOVDr), DestReg)
1437 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
1441 BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg)
1454 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
1462 BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg)
1475 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
1483 BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg)
1492 BuildMI(MBB, I, DL, get(AArch64::FMOVXDr), DestReg)
1498 BuildMI(MBB, I, DL, get(AArch64::FMOVDXr), DestReg)
1505 BuildMI(MBB, I, DL, get(AArch64::FMOVWSr), DestReg)
1511 BuildMI(MBB, I, DL, get(AArch64::FMOVSWr), DestReg)
1518 BuildMI(MBB, I, DL, get(AArch64::MSR))
1527 BuildMI(MBB, I, DL, get(AArch64::MRS))
1538 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg,
1542 if (MBBI != MBB.end())
1544 MachineFunction &MF = *MBB.getParent();
1626 const MachineInstrBuilder &MI = BuildMI(MBB, MBBI, DL, get(Opc))
1636 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg,
1640 if (MBBI != MBB.end())
1642 MachineFunction &MF = *MBB.getParent();
1724 const MachineInstrBuilder &MI = BuildMI(MBB, MBBI, DL, get(Opc))
1732 void llvm::emitFrameOffset(MachineBasicBlock &MBB,
1772 BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg)
1783 BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg)
