Lines Matching refs:MBB
122 HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
149 MachineInstr *Term = MBB.getFirstTerminator();
150 if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond,
153 std::next(MachineFunction::iterator(&MBB));
156 RemoveBranch(MBB);
157 return InsertBranch(MBB, TBB, nullptr, Cond, DL);
160 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
162 BuildMI(&MBB, DL,
168 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
169 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
175 bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
184 MachineBasicBlock::instr_iterator I = MBB.instr_end();
185 if (I == MBB.instr_begin())
204 } while (I != MBB.instr_begin());
206 I = MBB.instr_end();
210 if (I == MBB.instr_begin())
217 MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
220 I = MBB.instr_end();
221 if (I == MBB.instr_begin())
240 if (I == MBB.instr_begin())
310 unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
315 MachineBasicBlock::iterator I = MBB.end();
316 if (I == MBB.begin()) return 0;
325 I = MBB.end();
327 if (I == MBB.begin()) return 1;
416 void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
421 BuildMI(MBB, I, DL, get(Hexagon::TFR), DestReg).addReg(SrcReg);
425 BuildMI(MBB, I, DL, get(Hexagon::TFR64), DestReg).addReg(SrcReg);
430 BuildMI(MBB, I, DL, get(Hexagon::OR_pp),
439 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
443 BuildMI(MBB, I, DL, get(Hexagon::TFR), (RI.getSubReg(DestReg,
445 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
452 BuildMI(MBB, I, DL, get(Hexagon::TFCR), DestReg).addReg(SrcReg);
457 BuildMI(MBB, I, DL, get(Hexagon::TFR_RsPd), DestReg).
463 BuildMI(MBB, I, DL, get(Hexagon::TFR_PdRs), DestReg).
473 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
478 DebugLoc DL = MBB.findDebugLoc(I);
479 MachineFunction &MF = *MBB.getParent();
491 BuildMI(MBB, I, DL, get(Hexagon::STriw))
495 BuildMI(MBB, I, DL, get(Hexagon::STrid))
499 BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
520 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
524 DebugLoc DL = MBB.findDebugLoc(I);
525 MachineFunction &MF = *MBB.getParent();
536 BuildMI(MBB, I, DL, get(Hexagon::LDriw), DestReg)
539 BuildMI(MBB, I, DL, get(Hexagon::LDrid), DestReg)
542 BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
956 isProfitableToIfCvt(MachineBasicBlock &MBB,
1077 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs,
1647 const MachineBasicBlock *MBB,
