| /external/llvm/examples/OCaml-Kaleidoscope/Chapter2/ |
| token.ml | 9 | Def | Extern
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| /external/llvm/examples/OCaml-Kaleidoscope/Chapter3/ |
| token.ml | 9 | Def | Extern
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| /external/llvm/examples/OCaml-Kaleidoscope/Chapter4/ |
| token.ml | 9 | Def | Extern
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| /external/llvm/examples/OCaml-Kaleidoscope/Chapter5/ |
| token.ml | 9 | Def | Extern
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| /external/llvm/examples/OCaml-Kaleidoscope/Chapter6/ |
| token.ml | 9 | Def | Extern
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| /external/llvm/examples/OCaml-Kaleidoscope/Chapter7/ |
| token.ml | 9 | Def | Extern
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| /external/llvm/lib/CodeGen/ |
| LiveInterval.cpp | 52 VNInfo *LiveRange::createDeadDef(SlotIndex Def,
54 assert(!Def.isDead() && "Cannot define a value at the dead slot");
55 iterator I = find(Def);
57 VNInfo *VNI = getNextValue(Def, VNInfoAllocator);
58 segments.push_back(Segment(Def, Def.getDeadSlot(), VNI));
61 if (SlotIndex::isSameInstr(Def, I->start)) {
62 assert(I->valno->def == I->start && "Inconsistent existing value def");
69 Def = std::min(Def, I->start)
[all...] |
| MachineCopyPropagation.cpp | 114 static bool isNopCopy(MachineInstr *CopyMI, unsigned Def, unsigned Src,
117 if (Def == SrcSrc)
119 if (TRI->isSubRegister(SrcSrc, Def)) {
121 unsigned SubIdx = TRI->getSubRegIndex(SrcSrc, Def);
132 // maintain imp-use/imp-def chains.
139 DenseMap<unsigned, MachineInstr*> AvailCopyMap; // Def -> available copies map
140 DenseMap<unsigned, MachineInstr*> CopyMap; // Def -> copies map
141 SourceMap SrcMap; // Src -> Def map
151 unsigned Def = MI->getOperand(0).getReg();
154 if (TargetRegisterInfo::isVirtualRegister(Def) ||
[all...] |
| ExecutionDepsFix.cpp | 121 int Def;
365 LiveRegs[rx].Def = -(1 << 20);
378 LiveRegs[rx].Def = -1;
395 // Use the most recent predecessor def for each register.
396 LiveRegs[rx].Def = std::max(LiveRegs[rx].Def, fi->second[rx].Def);
436 LiveRegs[i].Def -= CurInstr;
465 /// \brief Return true to if it makes sense to break dependence on a partial def
473 unsigned Clearance = CurInstr - LiveRegs[rx].Def;
[all...] |
| LiveVariables.cpp | 114 assert(MBB != &MF->front() && "Can't find reaching def for virtreg");
133 assert(MRI->getVRegDef(reg) && "Register use before def!");
190 /// FindLastPartialDef - Return the last partial def of the specified register.
199 MachineInstr *Def = PhysRegDef[SubReg];
200 if (!Def)
202 unsigned Dist = DistanceMap[Def];
205 LastDef = Def;
228 /// HandlePhysRegUse - Turn previous partial def's into read/mod/writes. Add
229 /// implicit defs to a machine instruction if there was an earlier def of its
233 // If there was a previous use or a "full" def all is well
[all...] |
| PeepholeOptimizer.cpp | 148 /// follows the use-def chain to find successive suitable sources.
150 /// def = COPY src.
155 /// def = COPY v2.sub0
157 /// Using a ValueTracker for def = COPY v2.sub0 will give the following
160 /// Then, def can be rewritten into def = COPY v0.
163 /// The current point into the use-def chain.
164 const MachineInstr *Def;
165 /// The index of the definition in Def.
215 : Def(&MI), DefIdx(DefIdx), DefSubReg(DefSubReg)
[all...] |
| SplitKit.cpp | 106 if (!SlotIndex::isEarlierInstr(VNI->def, LSP.second) && VNI->def < MBBEnd)
131 UseSlots.push_back((*I)->def);
133 // Get use slots form the use-def chain.
214 // When not live in, the first use should be a def.
216 assert(LVI->start == LVI->valno->def && "Dangling Segment start");
217 assert(LVI->start == BI.FirstInstr && "First instr should be a def");
247 // A Segment that starts in the middle of the block must be a def.
248 assert(LVI->start == LVI->valno->def && "Dangling Segment start");
390 // Keep it as a simple def without any liveness
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIFixSGPRCopies.cpp | 168 MachineInstr *Def = MRI.getVRegDef(Reg);
169 if (Def->getOpcode() != AMDGPU::COPY) {
173 return inferRegClassFromDef(TRI, MRI, Def->getOperand(1).getReg(),
174 Def->getOperand(1).getSubReg());
|
| SITypeRewriter.cpp | 122 InsertElementInst *Def = cast<InsertElementInst>(Arg);
123 Args.push_back(Def->getOperand(1));
|
| /external/llvm/lib/Analysis/ |
| MemDepPrinter.cpp | 29 Def,
67 return InstTypePair(dep.getInst(), Def);
91 = {"Clobber", "Def", "NonFuncLocal", "Unknown"};
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| /external/llvm/lib/Target/AArch64/ |
| AArch64AdvSIMDScalarPass.cpp | 199 MachineRegisterInfo::def_instr_iterator Def =
201 assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!");
202 Src0 = getSrcFromCopy(&*Def, MRI, SubReg0);
212 MachineRegisterInfo::def_instr_iterator Def =
214 assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!");
215 Src1 = getSrcFromCopy(&*Def, MRI, SubReg1);
292 MachineRegisterInfo::def_instr_iterator Def =
294 assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!")
[all...] |
| AArch64CollectLOH.cpp | 205 /// mapping def to reachable uses or use to definitions.
303 // Treat ADRP def as use, as the goal of the analysis is to find
375 /// Reaching def core algorithm:
443 /// def algorithm.
444 /// \param ADRPMode specify whether the reaching def algorithm should be tuned
493 DEBUG(dbgs() << "Def:\n");
504 /// Answer the following question: Can Def be one of the definition
506 static bool canDefBePartOfLOH(const MachineInstr *Def) {
507 unsigned Opc = Def->getOpcode();
516 switch (Def->getOperand(2).getType())
[all...] |
| /external/clang/lib/Lex/ |
| PPMacroExpansion.cpp | 219 MacroDirective::DefInfo Def = MD->getDefinition();
220 assert(Def.isValid());
221 MacroInfo *MI = Def.getMacroInfo();
295 if (Def.getDirective()->isAmbiguous()) {
300 for (MacroDirective::DefInfo PrevDef = Def.getPreviousDefinition();
[all...] |
| PreprocessingRecord.cpp | 323 MacroDefinition *Def) {
324 MacroDefinitions[Macro] = Def;
379 else if (MacroDefinition *Def = findMacroDefinition(MI))
381 new (*this) MacroExpansion(Def, Range));
423 MacroDefinition *Def
425 addPreprocessedEntity(Def);
426 MacroDefinitions[MI] = Def;
|
| Preprocessor.cpp | 312 Def = I->second->findDirectiveAtLoc(Loc, SourceMgr);
313 if (!Def)
315 if (!MacroDefinitionEquals(Def.getMacroInfo(), Tokens))
317 SourceLocation Location = Def.getLocation();
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZElimCompare.cpp | 40 : Def(false), Use(false), IndirectDef(false), IndirectUse(false) {}
43 Def |= Other.Def;
50 operator bool() const { return Def || Use; }
54 bool Def;
151 Ref.Def = true;
347 (!CCRefs.Def && adjustCCMasksForInstr(MI, Compare, CCUsers))) {
353 if (SrcRefs.Def)
356 if (CCRefs.Use && CCRefs.Def)
450 if (CCRefs.Def) {
[all...] |
| /external/llvm/include/llvm/Analysis/ |
| MemoryDependenceAnalysis.h | 56 /// Def - This is a dependence on the specified instruction which
64 /// that the def may not be the same type as the query, the pointers
69 /// 3. Dependence queries on calls return Def only when they are
73 Def,
105 assert(Inst && "Def requires inst");
106 return MemDepResult(PairTy(Inst, Def));
131 bool isDef() const { return Value.getInt() == Def; }
|
| /external/llvm/lib/TableGen/ |
| TGLexer.h | 46 Bit, Bits, Class, Code, Dag, Def, Foreach, Defm, Field, In, Int, Let, List,
|
| /external/llvm/lib/Target/ARM/ |
| A15SDOptimizer.cpp | 204 MachineInstr *Def = Op->getParent();
208 if (DeadInstr.find(Def) != DeadInstr.end())
215 for (unsigned int j = 0; j < Def->getNumOperands(); ++j) {
216 MachineOperand &MODef = Def->getOperand(j);
228 if (&*II == Def)
239 DEBUG(dbgs() << "Deleting instruction " << *Def << "\n");
240 DeadInstr.insert(Def);
309 MachineInstr *Def = MRI->getVRegDef(OpReg);
310 if (!Def)
312 if (Def->isImplicitDef()
[all...] |
| /external/llvm/utils/TableGen/ |
| DAGISelMatcherGen.cpp | 623 Record *Def = DI->getDef();
624 if (Def->isSubClassOf("Register")) {
626 CGP.getTargetInfo().getRegBank().getReg(Def);
632 if (Def->getName() == "zero_reg") {
640 if (Def->isSubClassOf("RegisterOperand"))
641 Def = Def->getValueAsDef("RegClass");
642 if (Def->isSubClassOf("RegisterClass")) {
643 std::string Value = getQualifiedName(Def) + "RegClassID";
650 if (Def->isSubClassOf("SubRegIndex"))
[all...] |
