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      1 //===- PseudoLoweringEmitter.cpp - PseudoLowering Generator -----*- C++ -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 
     10 #include "CodeGenInstruction.h"
     11 #include "CodeGenTarget.h"
     12 #include "llvm/ADT/IndexedMap.h"
     13 #include "llvm/ADT/SmallVector.h"
     14 #include "llvm/ADT/StringMap.h"
     15 #include "llvm/Support/Debug.h"
     16 #include "llvm/Support/ErrorHandling.h"
     17 #include "llvm/TableGen/Error.h"
     18 #include "llvm/TableGen/Record.h"
     19 #include "llvm/TableGen/TableGenBackend.h"
     20 #include <vector>
     21 using namespace llvm;
     22 
     23 #define DEBUG_TYPE "pseudo-lowering"
     24 
     25 namespace {
     26 class PseudoLoweringEmitter {
     27   struct OpData {
     28     enum MapKind { Operand, Imm, Reg };
     29     MapKind Kind;
     30     union {
     31       unsigned Operand;   // Operand number mapped to.
     32       uint64_t Imm;       // Integer immedate value.
     33       Record *Reg;        // Physical register.
     34     } Data;
     35   };
     36   struct PseudoExpansion {
     37     CodeGenInstruction Source;  // The source pseudo instruction definition.
     38     CodeGenInstruction Dest;    // The destination instruction to lower to.
     39     IndexedMap<OpData> OperandMap;
     40 
     41     PseudoExpansion(CodeGenInstruction &s, CodeGenInstruction &d,
     42                     IndexedMap<OpData> &m) :
     43       Source(s), Dest(d), OperandMap(m) {}
     44   };
     45 
     46   RecordKeeper &Records;
     47 
     48   // It's overkill to have an instance of the full CodeGenTarget object,
     49   // but it loads everything on demand, not in the constructor, so it's
     50   // lightweight in performance, so it works out OK.
     51   CodeGenTarget Target;
     52 
     53   SmallVector<PseudoExpansion, 64> Expansions;
     54 
     55   unsigned addDagOperandMapping(Record *Rec, DagInit *Dag,
     56                                 CodeGenInstruction &Insn,
     57                                 IndexedMap<OpData> &OperandMap,
     58                                 unsigned BaseIdx);
     59   void evaluateExpansion(Record *Pseudo);
     60   void emitLoweringEmitter(raw_ostream &o);
     61 public:
     62   PseudoLoweringEmitter(RecordKeeper &R) : Records(R), Target(R) {}
     63 
     64   /// run - Output the pseudo-lowerings.
     65   void run(raw_ostream &o);
     66 };
     67 } // End anonymous namespace
     68 
     69 // FIXME: This pass currently can only expand a pseudo to a single instruction.
     70 //        The pseudo expansion really should take a list of dags, not just
     71 //        a single dag, so we can do fancier things.
     72 
     73 unsigned PseudoLoweringEmitter::
     74 addDagOperandMapping(Record *Rec, DagInit *Dag, CodeGenInstruction &Insn,
     75                      IndexedMap<OpData> &OperandMap, unsigned BaseIdx) {
     76   unsigned OpsAdded = 0;
     77   for (unsigned i = 0, e = Dag->getNumArgs(); i != e; ++i) {
     78     if (DefInit *DI = dyn_cast<DefInit>(Dag->getArg(i))) {
     79       // Physical register reference. Explicit check for the special case
     80       // "zero_reg" definition.
     81       if (DI->getDef()->isSubClassOf("Register") ||
     82           DI->getDef()->getName() == "zero_reg") {
     83         OperandMap[BaseIdx + i].Kind = OpData::Reg;
     84         OperandMap[BaseIdx + i].Data.Reg = DI->getDef();
     85         ++OpsAdded;
     86         continue;
     87       }
     88 
     89       // Normal operands should always have the same type, or we have a
     90       // problem.
     91       // FIXME: We probably shouldn't ever get a non-zero BaseIdx here.
     92       assert(BaseIdx == 0 && "Named subargument in pseudo expansion?!");
     93       if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec)
     94         PrintFatalError(Rec->getLoc(),
     95                       "Pseudo operand type '" + DI->getDef()->getName() +
     96                       "' does not match expansion operand type '" +
     97                       Insn.Operands[BaseIdx + i].Rec->getName() + "'");
     98       // Source operand maps to destination operand. The Data element
     99       // will be filled in later, just set the Kind for now. Do it
    100       // for each corresponding MachineInstr operand, not just the first.
    101       for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I)
    102         OperandMap[BaseIdx + i + I].Kind = OpData::Operand;
    103       OpsAdded += Insn.Operands[i].MINumOperands;
    104     } else if (IntInit *II = dyn_cast<IntInit>(Dag->getArg(i))) {
    105       OperandMap[BaseIdx + i].Kind = OpData::Imm;
    106       OperandMap[BaseIdx + i].Data.Imm = II->getValue();
    107       ++OpsAdded;
    108     } else if (DagInit *SubDag = dyn_cast<DagInit>(Dag->getArg(i))) {
    109       // Just add the operands recursively. This is almost certainly
    110       // a constant value for a complex operand (> 1 MI operand).
    111       unsigned NewOps =
    112         addDagOperandMapping(Rec, SubDag, Insn, OperandMap, BaseIdx + i);
    113       OpsAdded += NewOps;
    114       // Since we added more than one, we also need to adjust the base.
    115       BaseIdx += NewOps - 1;
    116     } else
    117       llvm_unreachable("Unhandled pseudo-expansion argument type!");
    118   }
    119   return OpsAdded;
    120 }
    121 
    122 void PseudoLoweringEmitter::evaluateExpansion(Record *Rec) {
    123   DEBUG(dbgs() << "Pseudo definition: " << Rec->getName() << "\n");
    124 
    125   // Validate that the result pattern has the corrent number and types
    126   // of arguments for the instruction it references.
    127   DagInit *Dag = Rec->getValueAsDag("ResultInst");
    128   assert(Dag && "Missing result instruction in pseudo expansion!");
    129   DEBUG(dbgs() << "  Result: " << *Dag << "\n");
    130 
    131   DefInit *OpDef = dyn_cast<DefInit>(Dag->getOperator());
    132   if (!OpDef)
    133     PrintFatalError(Rec->getLoc(), Rec->getName() +
    134                   " has unexpected operator type!");
    135   Record *Operator = OpDef->getDef();
    136   if (!Operator->isSubClassOf("Instruction"))
    137     PrintFatalError(Rec->getLoc(), "Pseudo result '" + Operator->getName() +
    138                     "' is not an instruction!");
    139 
    140   CodeGenInstruction Insn(Operator);
    141 
    142   if (Insn.isCodeGenOnly || Insn.isPseudo)
    143     PrintFatalError(Rec->getLoc(), "Pseudo result '" + Operator->getName() +
    144                     "' cannot be another pseudo instruction!");
    145 
    146   if (Insn.Operands.size() != Dag->getNumArgs())
    147     PrintFatalError(Rec->getLoc(), "Pseudo result '" + Operator->getName() +
    148                     "' operand count mismatch");
    149 
    150   unsigned NumMIOperands = 0;
    151   for (unsigned i = 0, e = Insn.Operands.size(); i != e; ++i)
    152     NumMIOperands += Insn.Operands[i].MINumOperands;
    153   IndexedMap<OpData> OperandMap;
    154   OperandMap.grow(NumMIOperands);
    155 
    156   addDagOperandMapping(Rec, Dag, Insn, OperandMap, 0);
    157 
    158   // If there are more operands that weren't in the DAG, they have to
    159   // be operands that have default values, or we have an error. Currently,
    160   // Operands that are a subclass of OperandWithDefaultOp have default values.
    161 
    162   // Validate that each result pattern argument has a matching (by name)
    163   // argument in the source instruction, in either the (outs) or (ins) list.
    164   // Also check that the type of the arguments match.
    165   //
    166   // Record the mapping of the source to result arguments for use by
    167   // the lowering emitter.
    168   CodeGenInstruction SourceInsn(Rec);
    169   StringMap<unsigned> SourceOperands;
    170   for (unsigned i = 0, e = SourceInsn.Operands.size(); i != e; ++i)
    171     SourceOperands[SourceInsn.Operands[i].Name] = i;
    172 
    173   DEBUG(dbgs() << "  Operand mapping:\n");
    174   for (unsigned i = 0, e = Insn.Operands.size(); i != e; ++i) {
    175     // We've already handled constant values. Just map instruction operands
    176     // here.
    177     if (OperandMap[Insn.Operands[i].MIOperandNo].Kind != OpData::Operand)
    178       continue;
    179     StringMap<unsigned>::iterator SourceOp =
    180       SourceOperands.find(Dag->getArgName(i));
    181     if (SourceOp == SourceOperands.end())
    182       PrintFatalError(Rec->getLoc(),
    183                       "Pseudo output operand '" + Dag->getArgName(i) +
    184                       "' has no matching source operand.");
    185     // Map the source operand to the destination operand index for each
    186     // MachineInstr operand.
    187     for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I)
    188       OperandMap[Insn.Operands[i].MIOperandNo + I].Data.Operand =
    189         SourceOp->getValue();
    190 
    191     DEBUG(dbgs() << "    " << SourceOp->getValue() << " ==> " << i << "\n");
    192   }
    193 
    194   Expansions.push_back(PseudoExpansion(SourceInsn, Insn, OperandMap));
    195 }
    196 
    197 void PseudoLoweringEmitter::emitLoweringEmitter(raw_ostream &o) {
    198   // Emit file header.
    199   emitSourceFileHeader("Pseudo-instruction MC lowering Source Fragment", o);
    200 
    201   o << "bool " << Target.getName() + "AsmPrinter" << "::\n"
    202     << "emitPseudoExpansionLowering(MCStreamer &OutStreamer,\n"
    203     << "                            const MachineInstr *MI) {\n";
    204 
    205   if (!Expansions.empty()) {
    206     o << "  switch (MI->getOpcode()) {\n"
    207       << "    default: return false;\n";
    208     for (auto &Expansion : Expansions) {
    209       CodeGenInstruction &Source = Expansion.Source;
    210       CodeGenInstruction &Dest = Expansion.Dest;
    211       o << "    case " << Source.Namespace << "::"
    212         << Source.TheDef->getName() << ": {\n"
    213         << "      MCInst TmpInst;\n"
    214         << "      MCOperand MCOp;\n"
    215         << "      TmpInst.setOpcode(" << Dest.Namespace << "::"
    216         << Dest.TheDef->getName() << ");\n";
    217 
    218       // Copy the operands from the source instruction.
    219       // FIXME: Instruction operands with defaults values (predicates and cc_out
    220       //        in ARM, for example shouldn't need explicit values in the
    221       //        expansion DAG.
    222       unsigned MIOpNo = 0;
    223       for (const auto &DestOperand : Dest.Operands) {
    224         o << "      // Operand: " << DestOperand.Name << "\n";
    225         for (unsigned i = 0, e = DestOperand.MINumOperands; i != e; ++i) {
    226           switch (Expansion.OperandMap[MIOpNo + i].Kind) {
    227             case OpData::Operand:
    228             o << "      lowerOperand(MI->getOperand("
    229               << Source.Operands[Expansion.OperandMap[MIOpNo].Data
    230               .Operand].MIOperandNo + i
    231               << "), MCOp);\n"
    232               << "      TmpInst.addOperand(MCOp);\n";
    233             break;
    234             case OpData::Imm:
    235             o << "      TmpInst.addOperand(MCOperand::CreateImm("
    236               << Expansion.OperandMap[MIOpNo + i].Data.Imm << "));\n";
    237             break;
    238             case OpData::Reg: {
    239               Record *Reg = Expansion.OperandMap[MIOpNo + i].Data.Reg;
    240               o << "      TmpInst.addOperand(MCOperand::CreateReg(";
    241               // "zero_reg" is special.
    242               if (Reg->getName() == "zero_reg")
    243                 o << "0";
    244               else
    245                 o << Reg->getValueAsString("Namespace") << "::"
    246                   << Reg->getName();
    247               o << "));\n";
    248               break;
    249             }
    250           }
    251         }
    252         MIOpNo += DestOperand.MINumOperands;
    253       }
    254       if (Dest.Operands.isVariadic) {
    255         MIOpNo = Source.Operands.size() + 1;
    256         o << "      // variable_ops\n";
    257         o << "      for (unsigned i = " << MIOpNo
    258           << ", e = MI->getNumOperands(); i != e; ++i)\n"
    259           << "        if (lowerOperand(MI->getOperand(i), MCOp))\n"
    260           << "          TmpInst.addOperand(MCOp);\n";
    261       }
    262       o << "      EmitToStreamer(OutStreamer, TmpInst);\n"
    263         << "      break;\n"
    264         << "    }\n";
    265     }
    266     o << "  }\n  return true;";
    267   } else
    268     o << "  return false;";
    269 
    270   o << "\n}\n\n";
    271 }
    272 
    273 void PseudoLoweringEmitter::run(raw_ostream &o) {
    274   Record *ExpansionClass = Records.getClass("PseudoInstExpansion");
    275   Record *InstructionClass = Records.getClass("Instruction");
    276   assert(ExpansionClass && "PseudoInstExpansion class definition missing!");
    277   assert(InstructionClass && "Instruction class definition missing!");
    278 
    279   std::vector<Record*> Insts;
    280   for (std::map<std::string, Record*>::const_iterator I =
    281          Records.getDefs().begin(), E = Records.getDefs().end(); I != E; ++I) {
    282     if (I->second->isSubClassOf(ExpansionClass) &&
    283         I->second->isSubClassOf(InstructionClass))
    284       Insts.push_back(I->second);
    285   }
    286 
    287   // Process the pseudo expansion definitions, validating them as we do so.
    288   for (unsigned i = 0, e = Insts.size(); i != e; ++i)
    289     evaluateExpansion(Insts[i]);
    290 
    291   // Generate expansion code to lower the pseudo to an MCInst of the real
    292   // instruction.
    293   emitLoweringEmitter(o);
    294 }
    295 
    296 namespace llvm {
    297 
    298 void EmitPseudoLowering(RecordKeeper &RK, raw_ostream &OS) {
    299   PseudoLoweringEmitter(RK).run(OS);
    300 }
    301 
    302 } // End llvm namespace
    303