| /external/llvm/lib/CodeGen/ |
| LivePhysRegs.cpp | 42 unsigned Reg = O->getReg();
43 if (Reg == 0)
45 removeReg(Reg);
54 unsigned Reg = O->getReg();
55 if (Reg == 0)
57 addReg(Reg);
70 unsigned Reg = O->getReg();
71 if (Reg == 0)
75 Defs.push_back(Reg);
80 removeReg(Reg);
[all...] |
| AllocationOrder.h | 54 unsigned Reg = Order[Pos++];
55 if (!isHint(Reg))
56 return Reg;
|
| DeadMachineInstructionElim.cpp | 70 unsigned Reg = MO.getReg();
71 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
73 if (LivePhysRegs.test(Reg) || MRI->isReserved(Reg))
76 if (!MRI->use_nodbg_empty(Reg))
131 unsigned Reg = MO.getReg();
132 if (!TargetRegisterInfo::isVirtualRegister(Reg))
134 MRI->markUsesInDebugValueAsUndef(Reg);
149 unsigned Reg = MO.getReg();
150 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
[all...] |
| RegAllocBase.cpp | 75 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
76 if (MRI->reg_nodbg_empty(Reg))
78 enqueue(&LIS->getInterval(Reg));
89 assert(!VRM->hasPhys(VirtReg->reg) && "Register already assigned");
92 if (MRI->reg_nodbg_empty(VirtReg->reg)) {
94 LIS->removeInterval(VirtReg->reg);
105 << MRI->getRegClass(VirtReg->reg)->getName()
116 I = MRI->reg_instr_begin(VirtReg->reg), E = MRI->reg_instr_end();
129 VRM->assignVirt2Phys(VirtReg->reg,
130 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front())
[all...] |
| ProcessImplicitDefs.cpp | 78 unsigned Reg = MI->getOperand(0).getReg();
80 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
83 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
107 !TRI->regsOverlap(Reg, UserReg))
109 // UserMI uses or redefines Reg. Set <undef> flags on all uses.
|
| AggressiveAntiDepBreaker.cpp | 61 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) {
62 unsigned Node = GroupNodeIndices[Reg];
74 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) {
75 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0))
76 Regs.push_back(Reg);
83 assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!");
96 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg)
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZShortenInst.cpp | 78 unsigned Reg = MI.getOperand(0).getReg();
79 assert(Reg < SystemZ::NUM_TARGET_REGS && "Invalid register number");
80 unsigned GPRs = GPRMap[Reg];
88 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
93 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
110 unsigned Reg = *LI;
111 assert(Reg < SystemZ::NUM_TARGET_REGS && "Invalid register number");
112 LiveLow |= LowGPRs[Reg];
113 LiveHigh |= HighGPRs[Reg];
133 if (unsigned Reg = MO.getReg())
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreFrameToArgsOffsetElim.cpp | 55 unsigned Reg = OldInst->getOperand(0).getReg();
56 MBBI = TII.loadImmediate(MBB, MBBI, Reg, StackSize);
|
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64MCTargetDesc.cpp | 73 unsigned Reg = MRI.getDwarfRegNum(AArch64::SP, true);
74 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonCallingConvLower.cpp | 57 void Hexagon_CCState::MarkAllocated(unsigned Reg) {
59 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
101 unsigned Reg = Hexagon::R0;
102 addLoc(CCValAssign::getReg(0, MVT::i32, Reg, MVT::i32,
107 unsigned Reg = Hexagon::D0;
108 addLoc(CCValAssign::getReg(0, MVT::i64, Reg, MVT::i64,
|
| HexagonCallingConvLower.h | 72 bool isAllocated(unsigned Reg) const {
73 return UsedRegs[Reg/32] & (1 << (Reg&31));
119 unsigned AllocateReg(unsigned Reg) {
120 if (isAllocated(Reg)) return 0;
121 MarkAllocated(Reg);
122 return Reg;
126 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) {
127 if (isAllocated(Reg)) return 0;
128 MarkAllocated(Reg);
[all...] |
| /external/llvm/lib/Target/NVPTX/InstPrinter/ |
| NVPTXInstPrinter.cpp | 86 unsigned Reg = Op.getReg();
87 printRegName(O, Reg);
|
| /external/llvm/lib/Target/Sparc/MCTargetDesc/ |
| SparcMCTargetDesc.cpp | 39 unsigned Reg = MRI.getDwarfRegNum(SP::O6, true);
40 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0);
48 unsigned Reg = MRI.getDwarfRegNum(SP::O6, true);
49 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 2047);
|
| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.cpp | 128 unsigned Reg = MO.getReg();
129 if (!Reg)
131 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
170 unsigned Reg = isSub
173 if (Reg) {
178 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
299 unsigned Reg = II->first;
301 if (Reg == X86::EAX || Reg == X86::AX ||
302 Reg == X86::AH || Reg == X86::AL
[all...] |
| X86FloatingPoint.cpp | 1 //===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===//
119 unsigned Reg = *I;
120 if (Reg < X86::FP0 || Reg > X86::FP6)
122 Mask |= 1 << (Reg - X86::FP0);
229 void pushReg(unsigned Reg) {
230 assert(Reg < NumFPRegs && "Register number out of range!");
233 Stack[StackTop] = Reg;
234 RegMap[Reg] = StackTop++;
290 void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg);
[all...] |
| X86InstrBuilder.h | 44 unsigned Reg;
57 Base.Reg = 0;
65 MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false,
91 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) {
93 // values, this adds: Reg, 1, NoReg, 0, NoReg to the instruction.
94 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
104 /// [Reg + Offset], i.e., one with no scale or index, but with a
109 unsigned Reg, bool isKill, int Offset) {
110 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
114 /// [Reg + Reg]
[all...] |
| /prebuilts/python/darwin-x86/2.7.5/lib/python2.7/distutils/tests/ |
| test_msvc9compiler.py | 124 from distutils.msvc9compiler import Reg
125 self.assertRaises(KeyError, Reg.get_value, 'xxx', 'xxx')
130 v = Reg.get_value(path, u'dragfullwindows')
135 keys = Reg.read_keys(HKCU, 'xxxx')
138 keys = Reg.read_keys(HKCU, r'Control Panel')
|
| /prebuilts/python/linux-x86/2.7.5/lib/python2.7/distutils/tests/ |
| test_msvc9compiler.py | 124 from distutils.msvc9compiler import Reg
125 self.assertRaises(KeyError, Reg.get_value, 'xxx', 'xxx')
130 v = Reg.get_value(path, u'dragfullwindows')
135 keys = Reg.read_keys(HKCU, 'xxxx')
138 keys = Reg.read_keys(HKCU, r'Control Panel')
|
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| AsmPrinterDwarf.cpp | 59 OutStreamer.AddComment("DW_CFA_offset + Reg (" +
190 static void emitDwarfRegOp(ByteStreamer &Streamer, int Reg) {
191 assert(Reg >= 0);
192 if (Reg < 32) {
193 Streamer.EmitInt8(dwarf::DW_OP_reg0 + Reg,
194 dwarf::OperationEncodingString(dwarf::DW_OP_reg0 + Reg));
197 Streamer.EmitULEB128(Reg, Twine(Reg));
202 static void emitDwarfRegOpIndirect(ByteStreamer &Streamer, int Reg, int Offset,
204 assert(Reg >= 0)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMCallingConv.h | 34 if (unsigned Reg = State.AllocateReg(RegList, 4))
35 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
49 if (unsigned Reg = State.AllocateReg(RegList, 4))
50 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
79 unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList, 2);
80 if (Reg == 0) {
83 Reg = State.AllocateReg(GPRArgRegs, 4);
84 assert((!Reg || Reg == ARM::R3) && "Wrong GPRs usage for f64");
99 if (HiRegList[i] == Reg)
[all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 71 OS << markup("<reg:")
267 // a single GPRPair reg operand is used in the .td file to replace the two
275 unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg();
276 if (MRC.contains(Reg)) {
283 NewReg = MCOperand::CreateReg(MRI.getMatchingSuperReg(Reg, ARM::gsub_0,
303 unsigned Reg = Op.getReg();
304 printRegName(O, Reg);
369 // REG 0 0 - e.g. R5
370 // REG REG 0,SH_OPC - e.g. R5, ROR R
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCTargetDesc.cpp | 250 unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);
251 MAI->addInitialFrameState(MCCFIInstruction::createDefCfa(nullptr, Reg, 0));
|
| /external/llvm/lib/Target/R600/ |
| SIFixSGPRCopies.cpp | 89 unsigned Reg,
93 unsigned Reg,
130 /// This functions walks the use list of Reg until it finds an Instruction
136 unsigned Reg,
138 // The Reg parameter to the function must always be defined by either a PHI
140 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
141 "Reg cannot be a physical register");
143 const TargetRegisterClass *RC = MRI.getRegClass(Reg);
146 I = MRI.use_instr_begin(Reg), E = MRI.use_instr_end(); I != E; ++I) {
162 unsigned Reg,
[all...] |
| /external/qemu/target-i386/ |
| ops_sse_header.h | 20 #define Reg MMXReg
23 #define Reg XMMReg
30 #define dh_ctype_Reg Reg *
37 DEF_HELPER_3(glue(psrlw, SUFFIX), void, env, Reg, Reg)
38 DEF_HELPER_3(glue(psraw, SUFFIX), void, env, Reg, Reg)
39 DEF_HELPER_3(glue(psllw, SUFFIX), void, env, Reg, Reg)
40 DEF_HELPER_3(glue(psrld, SUFFIX), void, env, Reg, Reg
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| FunctionLoweringInfo.h | 154 const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg) {
155 if (!LiveOutRegInfo.inBounds(Reg))
158 const LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
170 const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth);
173 void AddLiveOutRegInfo(unsigned Reg, unsigned NumSignBits,
179 LiveOutRegInfo.grow(Reg);
180 LiveOutInfo &LOI = LiveOutRegInfo[Reg];
198 unsigned Reg = It->second;
199 LiveOutRegInfo.grow(Reg);
200 LiveOutRegInfo[Reg].IsValid = false
[all...] |
