| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 64 /// SHL, SRA, SRL - Non-constant shifts.
65 SHL, SRA, SRL
|
| /external/valgrind/main/none/tests/mips64/ |
| shift_instructions.c | 10 SRA, SRAV, SRL, SRLV
189 case SRL:
190 TEST2("srl $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
191 TEST2("srl $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
192 TEST2("srl $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
193 TEST2("srl $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZSelectionDAGInfo.cpp | 184 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i32, IPM,
186 SDValue ROTL = DAG.getNode(ISD::ROTL, DL, MVT::i32, SRL,
|
| /external/linux-tools-perf/perf-3.12.0/arch/mips/lib/ |
| memcpy.S | 111 #define SRL dsrl
147 #define SRL srl
238 SRL t0, len, LOG_NBYTES+3 # +3 for 8 units/iter
360 SRL t0, len, LOG_NBYTES+2 # +2 for 4 units/iter
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.h | 95 SRL, SRA, SHL,
|
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 311 SHL, SRA, SRL, ROTL, ROTR,
[all...] |
| /external/llvm/include/llvm/TableGen/ |
| Record.h | 931 enum BinaryOp { ADD, SHL, SRA, SRL, LISTCONCAT, STRCONCAT, CONCAT, EQ };
[all...] |
| /system/core/libpixelflinger/codeflinger/ |
| MIPSAssembler.cpp | 398 case LSR: mMips->SRL(tmpReg, amode.reg, amode.value); break;
509 case LSR: mMips->SRL(Rd, amode.reg, amode.value); break;
541 case LSR: mMips->SRL(Rd, amode.reg, amode.value); break;
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 621 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
630 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | [all...] |
