| /external/llvm/lib/Target/R600/ |
| AMDGPUMCInstLower.h | 29 const AMDGPUSubtarget &ST;
39 AMDGPUMCInstLower(MCContext &ctx, const AMDGPUSubtarget &ST);
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| AMDGPURegisterInfo.h | 33 const AMDGPUSubtarget &ST;
35 AMDGPURegisterInfo(const AMDGPUSubtarget &st);
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| AMDGPUInstrInfo.h | 48 const AMDGPUSubtarget &ST;
50 explicit AMDGPUInstrInfo(const AMDGPUSubtarget &st);
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| AMDGPUTargetTransformInfo.cpp | 41 const AMDGPUSubtarget *ST;
49 AMDGPUTTI() : ImmutablePass(ID), TM(nullptr), ST(nullptr), TLI(nullptr) {
54 : ImmutablePass(ID), TM(TM), ST(TM->getSubtargetImpl()),
|
| AMDGPUTargetMachine.cpp | 52 static std::string computeDataLayout(const AMDGPUSubtarget &ST) {
55 if (ST.is64bit()) {
106 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
107 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
139 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
140 addPass(createAMDGPUPromoteAlloca(ST));
147 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
149 if (ST.IsIRStructurizerEnabled())
151 if (ST.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
168 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>()
[all...] |
| /external/clang/test/CodeGenCXX/ |
| reference-in-block-args.cpp | 6 struct ST {
11 void OUTER_BLOCK(void (^fixer)(ST& ref)) {
12 ST ref = {2, 100};
21 OUTER_BLOCK(^(ST &ref) {
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| mangle-lambdas.cpp | 78 struct ST {
85 void test_ST(ST<double> st) {
91 st.f();
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDGPUTargetMachine.cpp | 98 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
99 if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
113 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
115 if (ST.device()->getGeneration() > AMDGPUDeviceInfo::HD6XXX) {
136 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
137 if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
|
| R600KernelParameters.cpp | 406 StructType *ST = NULL;
409 ST = dyn_cast<StructType>(PT->getElementType());
412 if (ST) {
415 std::string Name = ST->getName().str();
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| /external/clang/test/OpenMP/ |
| parallel_copyin_messages.cpp | 38 class ST {
63 #pragma omp parallel copyin(ST<int>::s) // expected-error {{copyin variable must be threadprivate}}
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| parallel_for_copyin_messages.cpp | 42 class ST {
88 #pragma omp parallel for copyin(ST < int > ::s) // expected-error {{copyin variable must be threadprivate}}
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| parallel_sections_copyin_messages.cpp | 42 class ST {
99 #pragma omp parallel sections copyin(ST < int > ::s) // expected-error {{copyin variable must be threadprivate}}
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| threadprivate_ast_print.cpp | 9 struct St{
30 struct ST {
38 v = ST<T>::m;
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUTargetMachine.cpp | 98 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
99 if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
113 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
115 if (ST.device()->getGeneration() > AMDGPUDeviceInfo::HD6XXX) {
136 const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
137 if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
|
| /external/llvm/lib/Target/Mips/ |
| MipsMachineFunction.cpp | 81 const MipsSubtarget &ST = MF.getTarget().getSubtarget<MipsSubtarget>();
84 if (ST.inMips16Mode())
87 RC = ST.isABI_N64() ?
108 const MipsSubtarget &ST = MF.getTarget().getSubtarget<MipsSubtarget>();
109 const TargetRegisterClass *RC = ST.isABI_N64() ?
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXTargetMachine.cpp | 159 const NVPTXSubtarget &ST =
166 if (!ST.hasImageHandles())
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| /external/llvm/lib/Target/AArch64/ |
| AArch64StorePairSuppress.cpp | 68 /// critical resource height. STP is good to form in Ld/St limited blocks and
124 const TargetSubtargetInfo &ST =
126 SchedModel.init(*ST.getSchedModel(), &ST, TII);
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| AArch64TargetTransformInfo.cpp | 40 const AArch64Subtarget *ST;
48 AArch64TTI() : ImmutablePass(ID), TM(nullptr), ST(nullptr), TLI(nullptr) {
53 : ImmutablePass(ID), TM(TM), ST(TM->getSubtargetImpl()),
91 if (ST->hasNEON())
100 if (ST->hasNEON())
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCTargetTransformInfo.cpp | 41 const PPCSubtarget *ST;
45 PPCTTI() : ImmutablePass(ID), ST(nullptr), TLI(nullptr) {
50 : ImmutablePass(ID), ST(TM->getSubtargetImpl()),
133 if (ST->hasPOPCNTD() && TyWidth <= 64)
258 if (ST->isPPC64() &&
275 if (ST->getDarwinDirective() == PPC::DIR_A2) {
283 if (Vector && !ST->hasAltivec())
285 return ST->hasVSX() ? 64 : 32;
290 if (ST->hasAltivec()) return 128;
294 if (ST->isPPC64()
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86VZeroUpper.cpp | 51 static const char* getBlockExitStateName(BlockExitState ST);
95 const char* VZeroUpperInserter::getBlockExitStateName(BlockExitState ST) {
96 switch (ST) {
250 const X86Subtarget &ST = MF.getTarget().getSubtarget<X86Subtarget>();
251 if (!ST.hasAVX() || ST.hasAVX512())
|
| /libcore/luni/src/main/java/org/apache/harmony/security/x501/ |
| AttributeTypeAndValue.java | 114 private static final ObjectIdentifier ST
115 = new ObjectIdentifier(new int[] { 2, 5, 4, 8 }, "ST", RFC1779_NAMES);
145 RFC1779_NAMES.put(ST.getName(), ST);
|
| /external/llvm/lib/CodeGen/ |
| BasicTargetTransformInfo.cpp | 226 const TargetSubtargetInfo *ST = &TM->getSubtarget<TargetSubtargetInfo>();
229 else if (ST->getSchedModel()->LoopMicroOpBufferSize > 0)
230 MaxOps = ST->getSchedModel()->LoopMicroOpBufferSize;
|
| MachineTraceMetrics.cpp | 59 const TargetSubtargetInfo &ST =
61 SchedModel.init(*ST.getSchedModel(), &ST, TII);
[all...] |
| Passes.cpp | 246 const TargetSubtargetInfo &ST = TM->getSubtarget<TargetSubtargetInfo>();
247 if (!ST.useMachineScheduler())
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| PostRASchedulerList.cpp | 270 const TargetSubtargetInfo &ST = Fn.getTarget().getSubtarget<TargetSubtargetInfo>();
271 if (!ST.enablePostRAScheduler(PassConfig->getOptLevel(), AntiDepMode,
|
