/external/llvm/include/llvm/CodeGen/ |
ISDOpcodes.h | 60 BasicBlock, VALUETYPE, CONDCODE, Register, RegisterMask, [all...] |
Analysis.h | 72 ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred); 76 ISD::CondCode getFCmpCodeWithoutNaN(ISD::CondCode CC); 81 ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred);
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/external/llvm/lib/Target/Mips/InstPrinter/ |
MipsInstPrinter.h | 33 enum CondCode { 73 const char *MipsFCCToString(Mips::CondCode CC);
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MipsInstPrinter.cpp | 37 const char* Mips::MipsFCCToString(Mips::CondCode CC) { 247 O << MipsFCCToString((Mips::CondCode)MO.getImm());
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/external/llvm/lib/Target/XCore/ |
XCoreInstrInfo.cpp | 38 enum CondCode { 137 static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc) 150 static inline unsigned GetCondBranchFromCond(XCore::CondCode CC) 161 static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC) 221 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode()); 243 XCore::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc); 297 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); 306 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); 420 Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm())) [all...] |
/external/llvm/lib/Target/X86/ |
X86InstrInfo.h | 32 enum CondCode { 63 unsigned GetCondBranchFromCond(CondCode CC); 67 unsigned getSETFromCond(CondCode CC, bool HasMemoryOperand = false); 71 unsigned getCMovFromCond(CondCode CC, unsigned RegBytes, 75 CondCode getCondFromCMovOpc(unsigned Opc); 79 CondCode GetOppositeBranchCondition(CondCode CC);
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/ |
nv50_ir_inlines.h | 26 static inline CondCode reverseCondCode(CondCode cc) 30 return static_cast<CondCode>(ccRev[cc & 7] | (cc & ~7)); 33 static inline CondCode inverseCondCode(CondCode cc) 35 return static_cast<CondCode>(cc ^ 7);
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nv50_ir.h | 168 enum CondCode 587 bool compare(CondCode cc, float fval) const; 629 bool setPredicate(CondCode ccode, Value *); 679 CondCode cc; 826 void setCondition(CondCode cond) { setCond = cond; } 827 CondCode getCondition() const { return setCond; } 830 CondCode setCond;
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nv50_ir_build_util.h | 73 CmpInstruction *mkCmp(operation, CondCode, DataType, 80 FlowInstruction *mkFlow(operation, void *target, CondCode, Value *pred);
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nv50_ir_build_util.cpp | 223 BuildUtil::mkCmp(operation op, CondCode cc, DataType ty, Value *dst, 307 BuildUtil::mkFlow(operation op, void *targ, CondCode cc, Value *pred)
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/external/mesa3d/src/gallium/drivers/nv50/codegen/ |
nv50_ir_inlines.h | 26 static inline CondCode reverseCondCode(CondCode cc) 30 return static_cast<CondCode>(ccRev[cc & 7] | (cc & ~7)); 33 static inline CondCode inverseCondCode(CondCode cc) 35 return static_cast<CondCode>(cc ^ 7);
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nv50_ir.h | 168 enum CondCode 587 bool compare(CondCode cc, float fval) const; 629 bool setPredicate(CondCode ccode, Value *); 679 CondCode cc; 826 void setCondition(CondCode cond) { setCond = cond; } 827 CondCode getCondition() const { return setCond; } 830 CondCode setCond;
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nv50_ir_build_util.h | 73 CmpInstruction *mkCmp(operation, CondCode, DataType, 80 FlowInstruction *mkFlow(operation, void *target, CondCode, Value *pred);
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nv50_ir_build_util.cpp | 223 BuildUtil::mkCmp(operation op, CondCode cc, DataType ty, Value *dst, 307 BuildUtil::mkFlow(operation op, void *targ, CondCode cc, Value *pred)
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/external/llvm/lib/CodeGen/ |
Analysis.cpp | 151 ISD::CondCode llvm::getFCmpCondCode(FCmpInst::Predicate Pred) { 173 ISD::CondCode llvm::getFCmpCodeWithoutNaN(ISD::CondCode CC) { 188 ISD::CondCode llvm::getICmpCondCode(ICmpInst::Predicate Pred) {
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/external/llvm/lib/Target/AArch64/ |
AArch64ConditionalCompares.cpp | 165 AArch64CC::CondCode HeadCmpBBCC; 171 AArch64CC::CondCode CmpBBTailCC; 269 // Parse a condition code returned by AnalyzeBranch, and compute the CondCode 272 static bool parseCond(ArrayRef<MachineOperand> Cond, AArch64CC::CondCode &CC) { 276 CC = (AArch64CC::CondCode)(int)Cond[0].getImm();
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AArch64ISelLowering.cpp | [all...] |
AArch64BranchRelaxation.cpp | 346 AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(0).getImm();
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/external/llvm/include/llvm/Target/ |
TargetLowering.h | 589 getCondCodeAction(ISD::CondCode CC, MVT VT) const { 602 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const { [all...] |
/external/llvm/lib/Target/AArch64/Utils/ |
AArch64BaseInfo.h | 192 enum CondCode { // Meaning (integer) Meaning (floating-point) 213 inline static const char *getCondCodeName(CondCode Code) { 235 inline static CondCode getInvertedCondCode(CondCode Code) { 238 return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1); 245 inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) { [all...] |
/external/llvm/lib/Target/Sparc/ |
SparcISelLowering.h | 174 unsigned CondCode = 0) const;
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/external/llvm/lib/Target/PowerPC/ |
PPCISelDAGToDAG.cpp | 121 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDLoc dl); 493 ISD::CondCode CC, SDLoc dl) { 590 static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) { 621 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert) { 653 static unsigned int getVCmpInst(MVT::SimpleValueType VecVT, ISD::CondCode CC, 747 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get(); [all...] |
/external/llvm/lib/Target/AArch64/AsmParser/ |
AArch64AsmParser.cpp | 60 AArch64CC::CondCode parseCondCodeString(StringRef Cond); 198 AArch64CC::CondCode Code; 242 struct CondCodeOp CondCode; 274 CondCode = o.CondCode; 336 AArch64CC::CondCode getCondCode() const { 338 return CondCode.Code; [all...] |
/external/llvm/lib/Target/ARM/ |
ARMISelLowering.cpp | 263 const ISD::CondCode Cond; [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
SelectionDAGBuilder.h | 209 CaseBlock(ISD::CondCode cc, const Value *cmplhs, const Value *cmprhs, 219 ISD::CondCode CC;
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