| /external/chromium_org/third_party/mesa/src/src/mesa/sparc/ |
| sparc_matrix.h | 35 #define M0 %f16
53 ldd [BASE + ( 0 * 0x4)], M0; \
59 ldd [BASE + ( 0 * 0x4)], M0; \
63 ld [BASE + ( 0 * 0x4)], M0; \
67 ldd [BASE + ( 0 * 0x4)], M0; \
73 ld [BASE + ( 0 * 0x4)], M0; \
78 ld [BASE + ( 0 * 0x4)], M0; \
82 ldd [BASE + ( 0 * 0x4)], M0; \
90 ld [BASE + ( 0 * 0x4)], M0; \
95 ldd [BASE + ( 0 * 0x4)], M0; \
[all...] |
| norm.S | 56 /* tx (f3) = (ux * m0) + (uy * m1) + (uz * m2)
60 fmuls %f0, M0, %f3 ! FGM Group
104 fmuls M0, %f15, M0
121 /* tx (f3) = (ux * m0) + (uy * m1) + (uz * m2)
125 fmuls %f0, M0, %f3 ! FGM Group
195 /* tx (f3) = (ux * m0)
199 fmuls %f0, M0, %f3 ! FGM Group
231 fmuls M0, %f15, M0
[all...] |
| xform.S | 82 fmuls %f0, M0, %f1 ! FGM Group 1-cycle stall on %f0
86 fmuls %f8, M0, %f9 ! FGM Group f1 available
115 fmuls %f0, M0, %f1 ! FGM Group 1-cycle stall on %f0
197 fmuls %f0, M0, %f1 ! FGM Group
199 fmuls %f8, M0, %f9 ! FGM Group
218 fmuls %f0, M0, %f1
251 fmuls %f0, M0, %f1 ! FGM Group
252 fmuls %f4, M0, %f5 ! FGM Group
268 fmuls %f0, M0, %f1
299 fmuls %f0, M0, %f1 ! FGM Grou
[all...] |
| /external/mesa3d/src/mesa/sparc/ |
| sparc_matrix.h | 35 #define M0 %f16
53 ldd [BASE + ( 0 * 0x4)], M0; \
59 ldd [BASE + ( 0 * 0x4)], M0; \
63 ld [BASE + ( 0 * 0x4)], M0; \
67 ldd [BASE + ( 0 * 0x4)], M0; \
73 ld [BASE + ( 0 * 0x4)], M0; \
78 ld [BASE + ( 0 * 0x4)], M0; \
82 ldd [BASE + ( 0 * 0x4)], M0; \
90 ld [BASE + ( 0 * 0x4)], M0; \
95 ldd [BASE + ( 0 * 0x4)], M0; \
[all...] |
| norm.S | 56 /* tx (f3) = (ux * m0) + (uy * m1) + (uz * m2)
60 fmuls %f0, M0, %f3 ! FGM Group
104 fmuls M0, %f15, M0
121 /* tx (f3) = (ux * m0) + (uy * m1) + (uz * m2)
125 fmuls %f0, M0, %f3 ! FGM Group
195 /* tx (f3) = (ux * m0)
199 fmuls %f0, M0, %f3 ! FGM Group
231 fmuls M0, %f15, M0
[all...] |
| xform.S | 82 fmuls %f0, M0, %f1 ! FGM Group 1-cycle stall on %f0
86 fmuls %f8, M0, %f9 ! FGM Group f1 available
115 fmuls %f0, M0, %f1 ! FGM Group 1-cycle stall on %f0
197 fmuls %f0, M0, %f1 ! FGM Group
199 fmuls %f8, M0, %f9 ! FGM Group
218 fmuls %f0, M0, %f1
251 fmuls %f0, M0, %f1 ! FGM Group
252 fmuls %f4, M0, %f5 ! FGM Group
268 fmuls %f0, M0, %f1
299 fmuls %f0, M0, %f1 ! FGM Grou
[all...] |
| /external/llvm/include/llvm/Support/ |
| CommandLine.h | [all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| SIRegisterInfo.cpp | 36 case AMDGPU::M0: return 124;
|
| SIISelLowering.cpp | 153 unsigned M0 = MRI.createVirtualRegister(&AMDGPU::M0RegRegClass);
161 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_MOV_B32), M0)
168 .addReg(M0);
176 .addReg(M0);
189 unsigned M0 = MRI.createVirtualRegister(&AMDGPU::M0RegRegClass);
191 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_MOV_B32), M0)
198 .addReg(M0);
|
| SIGenRegisterInfo.pl | 95 def M0 : SIReg <"M0">;
143 (add (sequence "SGPR%u", 0, $SGPR_MAX_IDX), SREG_LIT_0, M0)
174 def M0Reg : RegisterClass<"AMDGPU", [i32], 32, (add M0)>;
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIRegisterInfo.cpp | 36 case AMDGPU::M0: return 124;
|
| SIISelLowering.cpp | 153 unsigned M0 = MRI.createVirtualRegister(&AMDGPU::M0RegRegClass);
161 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_MOV_B32), M0)
168 .addReg(M0);
176 .addReg(M0);
189 unsigned M0 = MRI.createVirtualRegister(&AMDGPU::M0RegRegClass);
191 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_MOV_B32), M0)
198 .addReg(M0);
|
| SIGenRegisterInfo.pl | 95 def M0 : SIReg <"M0">;
143 (add (sequence "SGPR%u", 0, $SGPR_MAX_IDX), SREG_LIT_0, M0)
174 def M0Reg : RegisterClass<"AMDGPU", [i32], 32, (add M0)>;
|
| /external/llvm/unittests/Support/ |
| CommandLineTest.cpp | 51 explicit StackOption(const M0t &M0) : Base(M0) {}
55 StackOption(const M0t &M0, const M1t &M1) : Base(M0, M1) {}
59 StackOption(const M0t &M0, const M1t &M1, const M2t &M2) : Base(M0, M1, M2) {}
63 StackOption(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3)
64 : Base(M0, M1, M2, M3) {}
|
| /external/chromium_org/third_party/openssl/openssl/crypto/md5/asm/ |
| md5-ia64.S | 35 // {in,out}4 Block Value 0 M0
125 #define M0 in4
310 // loading into M12 here produces the M0 value, M13 -> M1, etc.
441 // Passed the first 4 words (M0 - M3) and initial (A, B, C, D) values,
542 G(A, B, C, D, M0) \
543 COMPUTE(A, B, 5, M0, RotateM0) \
552 H(A, B, C, D, M0) \
553 COMPUTE(A, B, 4, M0, RotateM0) \
562 I(A, B, C, D, M0) \
563 COMPUTE(A, B, 6, M0, RotateM0)
[all...] |
| /external/openssl/crypto/md5/asm/ |
| md5-ia64.S | 35 // {in,out}4 Block Value 0 M0
125 #define M0 in4
310 // loading into M12 here produces the M0 value, M13 -> M1, etc.
441 // Passed the first 4 words (M0 - M3) and initial (A, B, C, D) values,
542 G(A, B, C, D, M0) \
543 COMPUTE(A, B, 5, M0, RotateM0) \
552 H(A, B, C, D, M0) \
553 COMPUTE(A, B, 4, M0, RotateM0) \
562 I(A, B, C, D, M0) \
563 COMPUTE(A, B, 6, M0, RotateM0)
[all...] |
| /libcore/luni/src/test/java/libcore/java/lang/ |
| ClassCastExceptionTest.java | 81 A0, B0, C0, D0, E0, F0, G0, H0, I0, J0, K0, L0, M0, N0, O0, P0, Q0, R0, S0, T0, U0, V0, W0, X0, Y0, Z0,
86 A0, B0, C0, D0, E0, F0, G0, H0, I0, J0, K0, L0, M0, N0, O0, P0, Q0, R0, S0, T0, U0, V0, W0, X0, Y0, Z0,
|
| /external/llvm/lib/Target/R600/ |
| SILowerControlFlow.cpp | 324 /// The m0 register stores the maximum allowable address for LDS reads and
329 AMDGPU::M0).addImm(0xffffffff);
342 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
359 // Move index from VCC into M0
360 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
363 // Compare the just read M0 value to all possible Idx values
365 .addReg(AMDGPU::M0)
391 // be stored in the m0 register and may be live for more than a few
392 // instructions? If so, we should save the m0 register at the beginning
414 .addReg(AMDGPU::M0, RegState::Implicit
[all...] |
| AMDGPUAsmPrinter.cpp | 251 case AMDGPU::M0:
|
| /external/llvm/unittests/Analysis/ |
| ScalarEvolutionTest.cpp | 64 const SCEVMulExpr *M0 = cast<SCEVMulExpr>(P0);
68 EXPECT_EQ(cast<SCEVConstant>(M0->getOperand(0))->getValue()->getZExtValue(),
76 EXPECT_EQ(cast<SCEVUnknown>(M0->getOperand(1))->getValue(), V0);
85 EXPECT_EQ(cast<SCEVUnknown>(M0->getOperand(1))->getValue(), V0);
|
| /external/chromium_org/third_party/openssl/openssl/crypto/poly1305/ |
| poly1305_vec.c | 333 xmmi M0,M1,M2,M3,M4;
367 M0 = _mm_and_si128(MMASK, T5);
375 T5 = _mm_mul_epu32(M0, p->R20.v); T6 = _mm_mul_epu32(M0, p->R21.v); T0 = _mm_add_epi64(T0, T5); T1 = _mm_add_epi64(T1, T6);
380 T5 = _mm_mul_epu32(M0, p->R22.v); T6 = _mm_mul_epu32(M0, p->R23.v); T2 = _mm_add_epi64(T2, T5); T3 = _mm_add_epi64(T3, T6);
385 T5 = _mm_mul_epu32(M0, p->R24.v); T4 = _mm_add_epi64(T4, T5);
394 M0 = _mm_and_si128(MMASK, T5);
401 T0 = _mm_add_epi64(T0, M0);
441 xmmi M0,M1,M2,M3,M4
[all...] |
| /external/opencv/cvaux/src/ |
| cvbgfg_codebook.cpp | 238 uchar m0, m1, m2, M0, M1, M2; local
256 m0 = model->modMin[0]; M0 = model->modMax[0];
271 int l0 = p0 + m0, l1 = p1 + m1, l2 = p2 + m2;
272 int h0 = p0 - M0, h1 = p1 - M1, h2 = p2 - M2;
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/ |
| SIMCCodeEmitter.cpp | 295 case AMDGPU::M0: return 124;
|
| /external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
| SIMCCodeEmitter.cpp | 295 case AMDGPU::M0: return 124;
|
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineMulDivRem.cpp | 495 Value *M0 = isNormalFp(cast<Constant>(M1)) ?
498 if (M0 && M1) {
500 std::swap(M0, M1);
503 ? BinaryOperator::CreateFAdd(M0, M1)
504 : BinaryOperator::CreateFSub(M0, M1);
[all...] |
