| /external/llvm/lib/MC/ |
| MCRegisterInfo.cpp | 61 int MCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
65 DwarfLLVMRegPair Key = { RegNum, 0 };
67 if (I == M+Size || I->FromReg != RegNum)
72 int MCRegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const {
76 DwarfLLVMRegPair Key = { RegNum, 0 };
78 assert(I != M+Size && I->FromReg == RegNum && "Invalid RegNum");
82 int MCRegisterInfo::getSEHRegNum(unsigned RegNum) const {
83 const DenseMap<unsigned, int>::const_iterator I = L2SEHRegs.find(RegNum);
84 if (I == L2SEHRegs.end()) return (int)RegNum;
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCRegisterInfo.h | 381 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
384 int getLLVMRegNum(unsigned RegNum, bool isEH) const;
388 int getSEHRegNum(unsigned RegNum) const;
|
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | 173 unsigned RegNum;
178 unsigned RegNum;
353 return Reg.RegNum;
358 return VectorList.RegNum;
885 Reg.RegNum);
889 AArch64MCRegisterClasses[AArch64::GPR64RegClassID].contains(Reg.RegNum);
894 AArch64MCRegisterClasses[AArch64::GPR64spRegClassID].contains(Reg.RegNum);
[all...] |
| /external/llvm/lib/Target/Sparc/AsmParser/ |
| SparcAsmParser.cpp | 158 unsigned RegNum;
205 return Reg.RegNum;
299 static std::unique_ptr<SparcOperand> CreateReg(unsigned RegNum, unsigned Kind,
302 Op->Reg.RegNum = RegNum;
324 Op.Reg.RegNum = DoubleRegs[regIdx / 2];
347 Op.Reg.RegNum = Reg;
|
| /art/compiler/dex/quick/x86/ |
| assemble_x86.cc | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsAsmPrinter.cpp | 267 unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg);
269 FPUBitmask |= (3 << RegNum);
275 FPUBitmask |= (1 << RegNum);
282 unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg);
283 CPUBitmask |= (1 << RegNum);
[all...] |
| /art/compiler/dex/quick/mips/ |
| target_mips.cc | 221 snprintf(tbuf, arraysize(tbuf), "$f%d", RegStorage::RegNum(operand));
224 DCHECK_EQ(RegStorage::RegNum(operand) & 1, 0);
225 snprintf(tbuf, arraysize(tbuf), "$f%d", RegStorage::RegNum(operand));
|
| assemble_mips.cc | 678 value = (RegStorage::RegNum(operand) << encoder->field_loc[i].start) &
685 value = (RegStorage::RegNum(operand) << encoder->field_loc[i].start) &
[all...] |
| /art/compiler/dex/quick/ |
| local_optimizations.cc | 239 if (RegStorage::RegNum(check_lir->operands[1]) == RegStorage::RegNum(reg)) {
|
| /external/clang/lib/Basic/ |
| TargetInfo.cpp | 346 if (AddlNames[i].Names[j] == Name && AddlNames[i].RegNum < NumNames)
399 if (AddlNames[i].Names[j] == Name && AddlNames[i].RegNum < NumNames)
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 444 unsigned RegNum;
449 unsigned RegNum;
478 unsigned RegNum;
643 return Reg.RegNum;
[all...] |
| /art/compiler/dex/ |
| reg_storage.h | 316 static constexpr uint16_t RegNum(int raw_reg_bits) {
|
| /external/llvm/lib/Target/R600/ |
| AMDILCFGStructurizer.cpp | 236 MachineBasicBlock::iterator I, int NewOpcode, int RegNum,
238 void insertCondBranchEnd(MachineBasicBlock *MBB, int NewOpcode, int RegNum);
515 MachineBasicBlock::iterator I, int NewOpcode, int RegNum,
521 MachineInstrBuilder(*MF, NewInstr).addReg(RegNum, false);
526 int NewOpcode, int RegNum) {
531 MachineInstrBuilder(*MF, NewInstr).addReg(RegNum, false);
[all...] |
| /external/clang/include/clang/Basic/ |
| TargetInfo.h | 596 const unsigned RegNum;
|
| /art/compiler/dex/quick/arm/ |
| target_arm.cc | 422 snprintf(tbuf, arraysize(tbuf), "s%d", RegStorage::RegNum(operand));
425 snprintf(tbuf, arraysize(tbuf), "d%d", RegStorage::RegNum(operand));
435 operand = RegStorage::RegNum(operand);
|
| assemble_arm.cc | [all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86CodeEmitter.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMCodeEmitter.cpp | [all...] |
| ARMLoadStoreOptimizer.cpp | 747 unsigned RegNum = MO.isUndef() ? UINT_MAX : TRI->getEncodingValue(Reg);
753 ((isNotVFP && RegNum > PRegNum) ||
754 ((Count < Limit) && RegNum == PRegNum+1)) &&
759 PRegNum = RegNum;
[all...] |
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 177 int matchRegisterByNumber(unsigned RegNum, unsigned RegClass);
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDILCFGStructurizer.cpp | 382 void addLoopBreakOnReg(LoopT *LoopRep, RegiT RegNum);
383 void addLoopContOnReg(LoopT *LoopRep, RegiT RegNum);
384 void addLoopBreakInitReg(LoopT *LoopRep, RegiT RegNum);
385 void addLoopContInitReg(LoopT *LoopRep, RegiT RegNum);
386 void addLoopEndbranchInitReg(LoopT *LoopRep, RegiT RegNum);
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILCFGStructurizer.cpp | 382 void addLoopBreakOnReg(LoopT *LoopRep, RegiT RegNum);
383 void addLoopContOnReg(LoopT *LoopRep, RegiT RegNum);
384 void addLoopBreakInitReg(LoopT *LoopRep, RegiT RegNum);
385 void addLoopContInitReg(LoopT *LoopRep, RegiT RegNum);
386 void addLoopEndbranchInitReg(LoopT *LoopRep, RegiT RegNum);
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.cpp | [all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 1002 if (unsigned RegNum = MO2.getReg()) {
1004 printRegName(O, RegNum);
[all...] |
