| /external/llvm/lib/Target/X86/Utils/ |
| X86ShuffleDecode.h | 39 void DecodePALIGNRMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
41 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
43 void DecodePSHUFHWMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
47 /// DecodeSHUFPMask - This decodes the shuffle masks for shufp*. VT indicates
50 void DecodeSHUFPMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
53 /// and punpckh*. VT indicates the type of the vector allowing it to handle
55 void DecodeUNPCKHMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
58 /// and punpckl*. VT indicates the type of the vector allowing it to handle
60 void DecodeUNPCKLMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
63 void DecodeVPERM2X128Mask(MVT VT, unsigned Imm
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| X86ShuffleDecode.cpp | 65 void DecodePALIGNRMask(MVT VT, unsigned Imm,
67 unsigned NumElts = VT.getVectorNumElements();
68 unsigned Offset = Imm * (VT.getVectorElementType().getSizeInBits() / 8);
70 unsigned NumLanes = VT.getSizeInBits() / 128;
84 /// VT indicates the type of the vector allowing it to handle different
86 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) {
87 unsigned NumElts = VT.getVectorNumElements();
89 unsigned NumLanes = VT.getSizeInBits() / 128;
102 void DecodePSHUFHWMask(MVT VT, unsigned Imm,
104 unsigned NumElts = VT.getVectorNumElements()
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| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 881 EVT VT = N->getValueType(0);
[all...] |
| AArch64ISelLowering.cpp | 441 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
442 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
444 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
447 setOperationAction(ISD::MULHS, (MVT::SimpleValueType)VT, Expand);
448 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
449 setOperationAction(ISD::MULHU, (MVT::SimpleValueType)VT, Expand);
450 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
452 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
456 setTruncStoreAction((MVT::SimpleValueType)VT,
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| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | 190 getPreferredVectorAction(EVT VT) const {
192 if (VT.getVectorNumElements() == 1)
208 shouldExpandBuildVectorWithShuffles(EVT /* VT */,
269 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
314 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
315 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
327 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
328 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
334 virtual uint8_t getRepRegClassCostFor(MVT VT) const {
335 return RepRegClassCostForVT[VT.SimpleTy]
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDGPUISelLowering.cpp | 106 EVT VT = Op.getValueType();
113 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
115 return DAG.getNode(ISD::FABS, DL, VT, Op.getOperand(1));
119 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
121 return DAG.getNode(AMDGPUISD::MAD, DL, VT, Op.getOperand(1),
124 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1),
127 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
130 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
133 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1),
136 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1)
[all...] |
| SIRegisterInfo.cpp | 53 MVT VT) const
55 switch(VT.SimpleTy) {
|
| R600ISelLowering.cpp | 277 EVT VT = Op.getValueType();
284 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass, Reg, VT);
288 return LowerImplicitParameter(DAG, VT, DL, 0);
290 return LowerImplicitParameter(DAG, VT, DL, 1);
292 return LowerImplicitParameter(DAG, VT, DL, 2);
294 return LowerImplicitParameter(DAG, VT, DL, 3);
296 return LowerImplicitParameter(DAG, VT, DL, 4);
298 return LowerImplicitParameter(DAG, VT, DL, 5);
300 return LowerImplicitParameter(DAG, VT, DL, 6);
302 return LowerImplicitParameter(DAG, VT, DL, 7)
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| SIRegisterInfo.h | 48 virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
|
| R600RegisterInfo.h | 47 virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUISelLowering.cpp | 106 EVT VT = Op.getValueType();
113 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
115 return DAG.getNode(ISD::FABS, DL, VT, Op.getOperand(1));
119 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
121 return DAG.getNode(AMDGPUISD::MAD, DL, VT, Op.getOperand(1),
124 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1),
127 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
130 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
133 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1),
136 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1)
[all...] |
| SIRegisterInfo.cpp | 53 MVT VT) const
55 switch(VT.SimpleTy) {
|
| R600ISelLowering.cpp | 277 EVT VT = Op.getValueType();
284 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass, Reg, VT);
288 return LowerImplicitParameter(DAG, VT, DL, 0);
290 return LowerImplicitParameter(DAG, VT, DL, 1);
292 return LowerImplicitParameter(DAG, VT, DL, 2);
294 return LowerImplicitParameter(DAG, VT, DL, 3);
296 return LowerImplicitParameter(DAG, VT, DL, 4);
298 return LowerImplicitParameter(DAG, VT, DL, 5);
300 return LowerImplicitParameter(DAG, VT, DL, 6);
302 return LowerImplicitParameter(DAG, VT, DL, 7)
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| SIRegisterInfo.h | 48 virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
|
| /external/llvm/include/llvm/CodeGen/ |
| ValueTypes.h | 42 bool operator==(EVT VT) const {
43 return !(*this != VT);
45 bool operator!=(EVT VT) const {
46 if (V.SimpleTy != VT.V.SimpleTy)
49 return LLVMTy != VT.LLVMTy;
70 /// length, where each element is of type VT.
71 static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements) {
72 MVT M = MVT::getVectorVT(VT.V, NumElements);
75 return getExtendedVectorVT(Context, VT, NumElements);
89 "Simple vector VT not representable by simple integer vector VT!")
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| SelectionDAG.h | 52 SDVTListNode(const FoldingSetNodeIDRef ID, const EVT *VT, unsigned int Num) :
53 FastID(ID), VTs(VT), NumVTs(Num) {
390 SDVTList getVTList(EVT VT);
399 SDValue getConstant(uint64_t Val, EVT VT, bool isTarget = false,
401 SDValue getConstant(const APInt &Val, EVT VT, bool isTarget = false,
403 SDValue getConstant(const ConstantInt &Val, EVT VT, bool isTarget = false,
406 SDValue getTargetConstant(uint64_t Val, EVT VT, bool isOpaque = false) {
407 return getConstant(Val, VT, true, isOpaque);
409 SDValue getTargetConstant(const APInt &Val, EVT VT, bool isOpaque = false) {
410 return getConstant(Val, VT, true, isOpaque)
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| /external/llvm/lib/Target/Mips/ |
| MipsFastISel.cpp | 72 bool EmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
74 bool EmitStore(MVT VT, unsigned SrcReg, Address &Addr,
80 bool isTypeLegal(Type *Ty, MVT &VT);
81 bool isLoadTypeLegal(Type *Ty, MVT &VT);
83 unsigned MaterializeFP(const ConstantFP *CFP, MVT VT);
84 unsigned MaterializeGV(const GlobalValue *GV, MVT VT);
85 unsigned MaterializeInt(const Constant *C, MVT VT);
119 bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) {
124 VT = evt.getSimpleVT();
128 return TLI.isTypeLegal(VT);
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| /libcore/luni/src/main/java/java/util/ |
| EnumMap.java | 51 private static class Entry<KT extends Enum<KT>, VT> extends
52 MapEntry<KT, VT> {
53 private final EnumMap<KT, VT> enumMap;
57 Entry(KT theKey, VT theValue, EnumMap<KT, VT> em) {
71 Map.Entry<KT, VT> entry = (Map.Entry<KT, VT>) object;
102 public VT getValue() {
104 return (VT) enumMap.values[ordinal];
109 public VT setValue(VT value)
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| /external/llvm/lib/CodeGen/ |
| CallingConvLower.cpp | 72 MVT ArgVT = Ins[i].VT;
90 MVT VT = Outs[i].VT;
92 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this))
104 MVT VT = Outs[i].VT;
106 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) {
109 << EVT(VT).getEVTString() << '\n'
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| /external/llvm/lib/Target/Hexagon/ |
| HexagonCallingConvLower.cpp | 81 EVT ArgVT = Ins[i].VT;
117 EVT VT = Outs[i].VT;
119 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this, -1, -1, false)){
121 << VT.getEVTString() << "\n";
147 EVT ArgVT = Outs[i].VT;
185 EVT VT = Ins[i].VT;
187 if (Fn(i, VT, VT, CCValAssign::Full, Flags, *this, -1, -1, false))
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.h | 24 SDValue LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, SDLoc DL,
51 bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AS,
55 getPreferredVectorAction(EVT VT) const override;
68 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
69 MVT getScalarShiftAmountTy(EVT VT) const override;
70 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
79 unsigned Reg, EVT VT) const override;
|
| AMDGPUISelLowering.cpp | 88 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
89 unsigned StoreSize = VT.getStoreSizeInBits();
98 EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) {
99 unsigned StoreSize = VT.getStoreSizeInBits();
246 for (MVT VT : ScalarIntVTs) {
247 setOperationAction(ISD::SREM, VT, Expand);
248 setOperationAction(ISD::SDIV, VT, Expand);
251 setOperationAction(ISD::SDIVREM, VT, Custom);
252 setOperationAction(ISD::UDIVREM, VT, Custom);
255 setOperationAction(ISD::SMUL_LOHI, VT, Expand)
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | 295 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
304 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
378 /// legalization or if the specified VT is legal.
379 bool isTypeLegal(const EVT &VT) {
381 return TLI.isTypeLegal(VT);
386 EVT getSetCCResultType(EVT VT) const {
387 return TLI.getSetCCResultType(*DAG.getContext(), VT);
674 EVT VT = N0.getValueType();
679 SDValue OpNode = DAG.FoldConstantArithmetic(Opc, VT, L, R);
682 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode)
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| SelectionDAG.cpp | 77 bool ConstantFPSDNode::isValueValidForType(EVT VT,
79 assert(VT.isFloatingPoint() && "Can only convert between FP types");
84 (void) Val2.convert(SelectionDAG::EVTToAPFloatSemantics(VT),
730 EVT VT = cast<VTSDNode>(N)->getVT();
731 if (VT.isExtended()) {
732 Erased = ExtendedValueTypeNodes.erase(VT);
734 Erased = ValueTypeNodes[VT.getSimpleVT().SimpleTy] != nullptr;
735 ValueTypeNodes[VT.getSimpleVT().SimpleTy] = nullptr;
849 EVT VT = N->getValueType(0);
851 assert(!VT.isVector() && (VT.isInteger() || VT.isFloatingPoint()) &
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 73 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
81 EVT VT = Vec.getValueType();
82 EVT ElVT = VT.getVectorElementType();
83 unsigned Factor = VT.getSizeInBits()/vectorWidth;
85 VT.getVectorNumElements()/Factor);
140 EVT VT = Vec.getValueType();
141 EVT ElVT = VT.getVectorElementType();
180 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
183 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
187 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
[all...] |
