/external/chromium_org/third_party/mesa/src/src/mesa/main/ |
stencil.c | 116 FLUSH_VERTICES(ctx, _NEW_STENCIL); 166 FLUSH_VERTICES(ctx, _NEW_STENCIL); 216 FLUSH_VERTICES(ctx, _NEW_STENCIL); 237 FLUSH_VERTICES(ctx, _NEW_STENCIL); 278 FLUSH_VERTICES(ctx, _NEW_STENCIL); 293 FLUSH_VERTICES(ctx, _NEW_STENCIL); 349 FLUSH_VERTICES(ctx, _NEW_STENCIL); 370 FLUSH_VERTICES(ctx, _NEW_STENCIL); 402 FLUSH_VERTICES(ctx, _NEW_STENCIL); 451 FLUSH_VERTICES(ctx, _NEW_STENCIL); [all...] |
state.c | 513 if (new_state & (_NEW_STENCIL | _NEW_BUFFERS)) 536 | _NEW_STENCIL | _MESA_NEW_SEPARATE_SPECULAR))
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/external/mesa3d/src/mesa/main/ |
stencil.c | 116 FLUSH_VERTICES(ctx, _NEW_STENCIL); 166 FLUSH_VERTICES(ctx, _NEW_STENCIL); 216 FLUSH_VERTICES(ctx, _NEW_STENCIL); 237 FLUSH_VERTICES(ctx, _NEW_STENCIL); 278 FLUSH_VERTICES(ctx, _NEW_STENCIL); 293 FLUSH_VERTICES(ctx, _NEW_STENCIL); 349 FLUSH_VERTICES(ctx, _NEW_STENCIL); 370 FLUSH_VERTICES(ctx, _NEW_STENCIL); 402 FLUSH_VERTICES(ctx, _NEW_STENCIL); 451 FLUSH_VERTICES(ctx, _NEW_STENCIL); [all...] |
state.c | 513 if (new_state & (_NEW_STENCIL | _NEW_BUFFERS)) 536 | _NEW_STENCIL | _MESA_NEW_SEPARATE_SPECULAR))
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/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/ |
gen6_depthstencil.c | 47 /* _NEW_STENCIL */ 96 .mesa = _NEW_DEPTH | _NEW_STENCIL | _NEW_BUFFERS,
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brw_vtbl.c | 127 * _NEW_BUFFERS | _NEW_STENCIL, but i965 code assumes that the value 128 * only changes with _NEW_STENCIL (which seems sensible). So flag it 131 intel->NewGLState |= (_NEW_DEPTH | _NEW_STENCIL);
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gen7_misc_state.c | 114 /* _NEW_STENCIL: enable stencil buffer writes */ 189 /* _NEW_DEPTH, _NEW_STENCIL */ 284 .mesa = (_NEW_BUFFERS | _NEW_DEPTH | _NEW_STENCIL),
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brw_cc.c | 106 /* _NEW_STENCIL */ 232 .mesa = _NEW_STENCIL | _NEW_COLOR | _NEW_DEPTH,
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gen6_cc.c | 224 /* _NEW_STENCIL */ 239 .mesa = _NEW_COLOR | _NEW_STENCIL,
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brw_state_upload.c | 343 DEFINE_BIT(_NEW_STENCIL),
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brw_wm.c | 516 /* _NEW_STENCIL */ 645 _NEW_STENCIL |
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/external/mesa3d/src/mesa/drivers/dri/i965/ |
gen6_depthstencil.c | 47 /* _NEW_STENCIL */ 96 .mesa = _NEW_DEPTH | _NEW_STENCIL | _NEW_BUFFERS,
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brw_vtbl.c | 127 * _NEW_BUFFERS | _NEW_STENCIL, but i965 code assumes that the value 128 * only changes with _NEW_STENCIL (which seems sensible). So flag it 131 intel->NewGLState |= (_NEW_DEPTH | _NEW_STENCIL);
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gen7_misc_state.c | 114 /* _NEW_STENCIL: enable stencil buffer writes */ 189 /* _NEW_DEPTH, _NEW_STENCIL */ 284 .mesa = (_NEW_BUFFERS | _NEW_DEPTH | _NEW_STENCIL),
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brw_cc.c | 106 /* _NEW_STENCIL */ 232 .mesa = _NEW_STENCIL | _NEW_COLOR | _NEW_DEPTH,
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gen6_cc.c | 224 /* _NEW_STENCIL */ 239 .mesa = _NEW_COLOR | _NEW_STENCIL,
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brw_state_upload.c | 343 DEFINE_BIT(_NEW_STENCIL),
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/external/chromium_org/third_party/mesa/src/src/mesa/state_tracker/ |
st_atom_depth.c | 156 (_NEW_DEPTH|_NEW_STENCIL|_NEW_COLOR), /* mesa */
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/external/mesa3d/src/mesa/state_tracker/ |
st_atom_depth.c | 156 (_NEW_DEPTH|_NEW_STENCIL|_NEW_COLOR), /* mesa */
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/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i915/ |
i915_context.c | 73 if (new_state & (_NEW_STENCIL | _NEW_BUFFERS | _NEW_POLYGON))
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/external/chromium_org/third_party/mesa/src/src/mesa/swrast/ |
s_context.h | 108 _NEW_STENCIL| \
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/external/mesa3d/src/mesa/drivers/dri/i915/ |
i915_context.c | 73 if (new_state & (_NEW_STENCIL | _NEW_BUFFERS | _NEW_POLYGON))
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/external/mesa3d/src/mesa/swrast/ |
s_context.h | 108 _NEW_STENCIL| \
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/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/radeon/ |
radeon_common.c | 294 ctx->NewState |= _NEW_STENCIL; 315 ctx->NewState |= (_NEW_DEPTH | _NEW_STENCIL);
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/external/mesa3d/src/mesa/drivers/dri/radeon/ |
radeon_common.c | 294 ctx->NewState |= _NEW_STENCIL; 315 ctx->NewState |= (_NEW_DEPTH | _NEW_STENCIL);
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