1 /* 2 * Copyright 2009 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric (at) anholt.net> 25 * 26 */ 27 28 #include "intel_fbo.h" 29 #include "brw_context.h" 30 #include "brw_state.h" 31 32 static void 33 gen6_upload_depth_stencil_state(struct brw_context *brw) 34 { 35 struct gl_context *ctx = &brw->intel.ctx; 36 struct gen6_depth_stencil_state *ds; 37 struct intel_renderbuffer *depth_irb; 38 39 /* _NEW_BUFFERS */ 40 depth_irb = intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH); 41 42 ds = brw_state_batch(brw, AUB_TRACE_DEPTH_STENCIL_STATE, 43 sizeof(*ds), 64, 44 &brw->cc.depth_stencil_state_offset); 45 memset(ds, 0, sizeof(*ds)); 46 47 /* _NEW_STENCIL */ 48 if (ctx->Stencil._Enabled) { 49 int back = ctx->Stencil._BackFace; 50 51 ds->ds0.stencil_enable = 1; 52 ds->ds0.stencil_func = 53 intel_translate_compare_func(ctx->Stencil.Function[0]); 54 ds->ds0.stencil_fail_op = 55 intel_translate_stencil_op(ctx->Stencil.FailFunc[0]); 56 ds->ds0.stencil_pass_depth_fail_op = 57 intel_translate_stencil_op(ctx->Stencil.ZFailFunc[0]); 58 ds->ds0.stencil_pass_depth_pass_op = 59 intel_translate_stencil_op(ctx->Stencil.ZPassFunc[0]); 60 ds->ds1.stencil_write_mask = ctx->Stencil.WriteMask[0]; 61 ds->ds1.stencil_test_mask = ctx->Stencil.ValueMask[0]; 62 63 if (ctx->Stencil._TestTwoSide) { 64 ds->ds0.bf_stencil_enable = 1; 65 ds->ds0.bf_stencil_func = 66 intel_translate_compare_func(ctx->Stencil.Function[back]); 67 ds->ds0.bf_stencil_fail_op = 68 intel_translate_stencil_op(ctx->Stencil.FailFunc[back]); 69 ds->ds0.bf_stencil_pass_depth_fail_op = 70 intel_translate_stencil_op(ctx->Stencil.ZFailFunc[back]); 71 ds->ds0.bf_stencil_pass_depth_pass_op = 72 intel_translate_stencil_op(ctx->Stencil.ZPassFunc[back]); 73 ds->ds1.bf_stencil_write_mask = ctx->Stencil.WriteMask[back]; 74 ds->ds1.bf_stencil_test_mask = ctx->Stencil.ValueMask[back]; 75 } 76 77 /* Not really sure about this: 78 */ 79 if (ctx->Stencil.WriteMask[0] || 80 (ctx->Stencil._TestTwoSide && ctx->Stencil.WriteMask[back])) 81 ds->ds0.stencil_write_enable = 1; 82 } 83 84 /* _NEW_DEPTH */ 85 if (ctx->Depth.Test && depth_irb) { 86 ds->ds2.depth_test_enable = ctx->Depth.Test; 87 ds->ds2.depth_test_func = intel_translate_compare_func(ctx->Depth.Func); 88 ds->ds2.depth_write_enable = ctx->Depth.Mask; 89 } 90 91 brw->state.dirty.cache |= CACHE_NEW_DEPTH_STENCIL_STATE; 92 } 93 94 const struct brw_tracked_state gen6_depth_stencil_state = { 95 .dirty = { 96 .mesa = _NEW_DEPTH | _NEW_STENCIL | _NEW_BUFFERS, 97 .brw = BRW_NEW_BATCH, 98 .cache = 0, 99 }, 100 .emit = gen6_upload_depth_stencil_state, 101 }; 102
