| /external/qemu/target-i386/ |
| helper.c | 996 int32_t sext; local
1269 int32_t sext; local
[all...] |
| /external/llvm/unittests/IR/ |
| ConstantRangeTest.cpp | 201 TEST_F(ConstantRangeTest, SExt) {
210 EXPECT_EQ(SOne, ConstantRange(One.getLower().sext(20),
211 One.getUpper().sext(20)));
212 EXPECT_EQ(SSome, ConstantRange(Some.getLower().sext(20),
213 Some.getUpper().sext(20)));
|
| /prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/lib/gcc/x86_64-w64-mingw32/4.8.3/plugin/include/ |
| double-int.h | 160 double_int sext (unsigned prec) const;
|
| /external/llvm/utils/vim/ |
| llvm.vim | 33 syn keyword llvmStatement sext sge sgt shl shufflevector sitofp sle slt srem
|
| /external/llvm/include/llvm/ADT/ |
| APSInt.h | 73 return APSInt(sext(width), IsUnsigned);
|
| APInt.h | [all...] |
| /external/llvm/lib/IR/ |
| ConstantRange.cpp | 451 return ConstantRange(Lower.sext(DstTySize), Upper.zext(DstTySize));
458 return ConstantRange(Lower.sext(DstTySize), Upper.sext(DstTySize));
|
| ConstantFold.cpp | 514 // sext(undef) = 0, because the top bits will all be the same.
516 if (opc == Instruction::ZExt || opc == Instruction::SExt ||
669 case Instruction::SExt:
673 CI->getValue().sext(BitWidth));
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineMulDivRem.cpp | 83 LHSExt = LHSExt.sext(W * 2);
84 RHSExt = RHSExt.sext(W * 2);
95 APInt Min = APInt::getSignedMinValue(W).sext(W * 2);
96 APInt Max = APInt::getSignedMaxValue(W).sext(W * 2);
[all...] |
| InstructionCombining.cpp | [all...] |
| /external/llvm/lib/Support/ |
| APInt.cpp | 865 int64_t sext = (int64_t(getWord(0)) << (64-BitWidth)) >> (64-BitWidth);
866 return double(sext);
943 APInt APInt::sext(unsigned width) const {
1013 return sext(width);
1027 return sext(width);
[all...] |
| /external/llvm/test/Bindings/Ocaml/ |
| vmcore.ml | 110 group "sext int";
286 * CHECK: const_sext{{.*}}sext
705 add_param_attr p1 Attribute.Sext;
915 * CHECK-DAG: %build_sext = sext i32 %build_zext to i64
916 * CHECK-DAG: %build_sext2 = sext i32 %build_zext to i64
917 * CHECK-DAG: %build_sext3 = sext i32 %build_zext to i64
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64TargetTransformInfo.cpp | 168 ImmVal = Imm.sext((BitSize + 63) & ~0x3fU);
226 case Instruction::SExt:
|
| /external/llvm/lib/Transforms/Scalar/ |
| SeparateConstOffsetFromGEP.cpp | 164 /// For example, to extract the 5 from sext(a + (b + 5)), we first distribute
165 /// sext to a, b and 5 so that we have
166 /// sext(a) + (sext(b) + 5).
168 /// (sext(a) + sext(b)) + 5.
169 /// Given this form, we know I' is sext(a) + sext(b).
173 /// e.g., zext(sext(a + (b + 5)) (assuming no overflow) =>
174 /// zext(sext(a)) + (zext(sext(b)) + zext(sext(5)))
[all...] |
| /external/llvm/lib/AsmParser/ |
| LLLexer.cpp | 712 INSTKEYWORD(sext, SExt);
|
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | [all...] |
| /external/llvm/bindings/ocaml/llvm/ |
| llvm.mli | 129 | Sext
236 | SExt
[all...] |
| /external/llvm/lib/ExecutionEngine/ |
| ExecutionEngine.cpp | 649 case Instruction::SExt: {
652 GV.IntVal = GV.IntVal.sext(BitWidth);
[all...] |
| /external/llvm/lib/ExecutionEngine/Interpreter/ |
| Execution.cpp | [all...] |
| /external/llvm/lib/Analysis/ |
| ScalarEvolution.cpp | 158 const SCEVSignExtendExpr *SExt = cast<SCEVSignExtendExpr>(this);
159 const SCEV *Op = SExt->getOperand();
160 OS << "(sext " << *Op->getType() << " " << *Op << " to "
161 << *SExt->getType() << ")";
845 // trunc(sext(x)) --> sext(x) if widening or trunc(x) if narrowing
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.cpp | 726 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
730 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
734 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
738 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
[all...] |
| DAGCombiner.cpp | [all...] |
| /external/clang/lib/AST/ |
| ExprConstant.cpp | [all...] |
