/external/llvm/lib/Target/R600/MCTargetDesc/ |
R600MCCodeEmitter.cpp | 92 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); 99 } else if (IS_VTX(Desc)) { 109 } else if (IS_TEX(Desc)) { 136 ((Desc.TSFlags & R600_InstFlag::OP1) || 137 Desc.TSFlags & R600_InstFlag::OP2)) {
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/external/llvm/lib/Target/X86/ |
X86CodeEmitter.cpp | 68 const MCInstrDesc *Desc) const; 72 const MCInstrDesc *Desc) const; 78 void emitInstruction(MachineInstr &MI, const MCInstrDesc *Desc); 147 const MCInstrDesc &Desc = I->getDesc(); 148 emitInstruction(*I, &Desc); 150 if (Desc.getOpcode() == X86::MOVPC32r) 165 const MCInstrDesc &Desc = MI.getDesc(); 168 if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo) 170 if (Desc.TSFlags & X86II::REX_W) 173 unsigned NumOps = Desc.getNumOperands() [all...] |
X86FixupLEAs.cpp | 232 const MCInstrDesc &Desc = MI->getDesc(); 233 int AddrOffset = X86II::getMemoryOperandNo(Desc.TSFlags, opcode); 235 AddrOffset += X86II::getOperandBias(Desc);
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/external/skia/src/gpu/effects/ |
GrTextureStripAtlas.h | 27 struct Desc { 28 Desc() { memset(this, 0, sizeof(*this)); } 38 static GrTextureStripAtlas* GetAtlas(const Desc& desc); 96 GrTextureStripAtlas(Desc desc); 139 class AtlasHashKey : public GrBinHashKey<sizeof(GrTextureStripAtlas::Desc)> { 166 const Desc fDesc;
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/external/skia/src/gpu/gl/ |
GrGLTexture.h | 60 struct Desc : public GrTextureDesc { 67 const Desc& textureDesc, 68 const GrGLRenderTarget::Desc& rtDesc); 72 const Desc& textureDesc); 105 const Desc& textureDesc, 106 const GrGLRenderTarget::Desc* rtDesc);
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/external/llvm/include/llvm/CodeGen/ |
LexicalScopes.h | 49 : Parent(P), Desc(D), InlinedAtLocation(I), AbstractScope(A), 57 const MDNode *getDesc() const { return Desc; } 59 const MDNode *getScopeNode() const { return Desc; } 119 AssertingVH<const MDNode> Desc; // Debug info descriptor.
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/external/llvm/include/llvm/Support/ |
Registry.h | 27 const char *Name, *Desc; 32 : Name(N), Desc(D), Ctor(C) 36 const char *getDesc() const { return Desc; } 204 Add(const char *Name, const char *Desc) 205 : Entry(Name, Desc, CtorFn), Node(Entry) {}
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CommandLine.h | 290 // desc - Modifier to set the description shown in the -help output... 291 struct desc { struct in namespace:llvm::cl 292 const char *Desc; 293 desc(const char *Str) : Desc(Str) {} function in struct:llvm::cl::desc 294 void apply(Option &O) const { O.setDescription(Desc); } 300 const char *Desc; 301 value_desc(const char *Str) : Desc(Str) {} 302 void apply(Option &O) const { O.setValueStr(Desc); } 477 #define clEnumVal(ENUMVAL, DESC) #ENUMVAL, int(ENUMVAL), DES [all...] |
/external/llvm/lib/CodeGen/AsmPrinter/ |
DIEHash.h | 33 const DIEAbbrevData *Desc;
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/external/llvm/lib/MC/MCDisassembler/ |
Disassembler.cpp | 188 const MCInstrDesc& Desc = DC->getInstrInfo()->get(Inst.getOpcode()); 189 unsigned SCClass = Desc.getSchedClass(); 215 const MCInstrDesc& Desc = DC->getInstrInfo()->get(Inst.getOpcode()); 216 unsigned SCClass = Desc.getSchedClass();
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/external/llvm/lib/Target/SystemZ/ |
SystemZElimCompare.cpp | 234 const MCInstrDesc &Desc = TII->get(Opcode); 235 unsigned MIFlags = Desc.TSFlags;
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/external/clang/lib/StaticAnalyzer/Checkers/ |
CallAndMessageChecker.cpp | 80 void LazyInit_BT(const char *desc, std::unique_ptr<BugType> &BT) const { 82 BT.reset(new BuiltinBug(this, desc)); 200 StringRef Desc = 202 BugReport *R = new BugReport(*BT, Desc, N); 333 StringRef Desc; 341 Desc = "Argument to 'delete[]' is uninitialized"; 343 Desc = "Argument to 'delete' is uninitialized"; 345 BugReport *R = new BugReport(*BT, Desc, N);
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/external/llvm/lib/Target/AArch64/ |
AArch64InstrInfo.cpp | 45 const MCInstrDesc &Desc = MI->getDesc(); 46 switch (Desc.getOpcode()) { [all...] |
/external/llvm/lib/Target/ARM/ |
ARMBaseRegisterInfo.cpp | 445 const MCInstrDesc &Desc = MI->getDesc(); 446 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 635 const MCInstrDesc &Desc = MI->getDesc(); 636 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
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ARMExpandPseudoInsts.cpp | 38 cl::desc("Verify machine code after expanding ARM pseudos")); 79 const MCInstrDesc &Desc = OldMI.getDesc(); 80 for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands(); [all...] |
/external/llvm/lib/Target/Mips/ |
MipsSEFrameLowering.cpp | 184 const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY); 187 BuildMI(MBB, I, DL, Desc, Lo).addReg(VR0, RegState::Kill); 189 BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill);
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MipsSEInstrInfo.cpp | 444 const MCInstrDesc &Desc = get(Opc); 445 assert(Desc.NumOperands == 2 && "Unary instruction expected."); 447 unsigned DstRegSize = getRegClass(Desc, 0, RI, MF)->getSize(); 448 unsigned SrcRegSize = getRegClass(Desc, 1, RI, MF)->getSize();
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/external/clang/include/clang/Analysis/ |
ProgramPoint.h | 664 std::string Desc;
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/external/llvm/include/llvm/MC/ |
MCRegisterInfo.h | 155 const MCRegisterDesc *Desc; // Pointer to the descriptor array 250 Desc = D; 317 return Desc[RegNo];
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/external/llvm/lib/Target/R600/ |
AMDGPUISelDAGToDAG.cpp | 128 const MCInstrDesc &Desc = TM.getInstrInfo()->get(N->getMachineOpcode()); 129 unsigned OpIdx = Desc.getNumDefs() + OpNo; 130 if (OpIdx >= Desc.getNumOperands()) 132 int RegClass = Desc.OpInfo[OpIdx].RegClass;
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/external/llvm/lib/Target/X86/MCTargetDesc/ |
X86MCCodeEmitter.cpp | 157 const MCInst &MI, const MCInstrDesc &Desc, 164 const MCInst &MI, const MCInstrDesc &Desc, 614 const MCInstrDesc &Desc, 735 unsigned NumOps = Desc.getNumOperands(); 736 unsigned CurOp = X86II::getOperandBias(Desc); [all...] |
/frameworks/compile/mclinker/include/mcld/LD/ |
ResolveInfo.h | 24 * - Desc - Defined, Reference, Common or Indirect 61 /** \enum Desc 67 enum Desc { 176 uint32_t desc() const;
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/external/jhead/ |
jhead.h | 174 char * Desc;
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/external/llvm/lib/CodeGen/SelectionDAG/ |
ScheduleDAGRRList.cpp | 69 cl::desc("Disable cycle-level precision during preRA scheduling")); 75 cl::desc("Disable regpressure priority in sched=list-ilp")); 78 cl::desc("Disable live use priority in sched=list-ilp")); 81 cl::desc("Disable virtual register cycle interference checks")); 84 cl::desc("Disable physreg def-use affinity")); 87 cl::desc("Disable no-stall priority in sched=list-ilp")); 90 cl::desc("Disable critical path priority in sched=list-ilp")); 93 cl::desc("Disable scheduled-height priority in sched=list-ilp")); 96 cl::desc("Disable scheduler's two-address hack")); 100 cl::desc("Number of instructions to allow ahead of the critical path [all...] |
/external/llvm/utils/TableGen/ |
SubtargetEmitter.cpp | 197 const std::string &Desc = Feature->getValueAsString("Desc"); 204 << "\"" << Desc << "\", " [all...] |